2017-11-24 07:15:14 +00:00
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef IRIS_BATCH_DOT_H
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#define IRIS_BATCH_DOT_H
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#include <stdint.h>
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#include <stdbool.h>
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2018-08-19 18:31:29 +01:00
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#include <string.h>
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2018-11-08 22:42:00 +00:00
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#include "util/u_dynarray.h"
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2018-04-21 08:05:57 +01:00
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#include "i915_drm.h"
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2018-04-07 00:21:21 +01:00
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#include "common/gen_decoder.h"
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2017-11-24 07:15:14 +00:00
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2018-01-21 08:16:15 +00:00
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/* The kernel assumes batchbuffers are smaller than 256kB. */
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#define MAX_BATCH_SIZE (256 * 1024)
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2018-08-19 18:31:29 +01:00
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/* Our target batch size - flush approximately at this point. */
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#define BATCH_SZ (20 * 1024)
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2018-11-20 17:00:22 +00:00
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enum iris_batch_name {
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IRIS_BATCH_RENDER,
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IRIS_BATCH_COMPUTE,
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};
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2018-11-07 05:12:30 +00:00
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#define IRIS_BATCH_COUNT 2
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2017-11-24 07:15:14 +00:00
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struct iris_address {
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struct iris_bo *bo;
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2018-04-06 08:05:24 +01:00
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uint64_t offset;
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2018-04-06 08:19:57 +01:00
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bool write;
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2017-11-24 07:15:14 +00:00
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};
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struct iris_batch {
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struct iris_screen *screen;
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2018-04-21 07:28:03 +01:00
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struct iris_vtable *vtbl;
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2017-11-24 07:15:14 +00:00
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struct pipe_debug_callback *dbg;
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2018-11-20 17:00:22 +00:00
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/** What batch is this? (e.g. IRIS_BATCH_RENDER/COMPUTE) */
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enum iris_batch_name name;
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2018-11-08 23:32:59 +00:00
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2017-11-24 07:15:14 +00:00
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/** Current batchbuffer being queued up. */
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2018-05-03 03:54:23 +01:00
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struct iris_bo *bo;
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void *map;
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void *map_next;
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/** Size of the primary batch if we've moved on to a secondary. */
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unsigned primary_batch_size;
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2018-09-09 03:43:34 +01:00
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/** Last Surface State Base Address set in this hardware context. */
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uint64_t last_surface_base_address;
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2017-11-24 07:15:14 +00:00
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uint32_t hw_ctx_id;
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2018-08-01 00:10:50 +01:00
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/** Which engine this batch targets - a I915_EXEC_RING_MASK value */
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uint8_t engine;
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2018-01-21 07:11:37 +00:00
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2017-11-24 07:15:14 +00:00
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/** The validation list */
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struct drm_i915_gem_exec_object2 *validation_list;
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struct iris_bo **exec_bos;
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int exec_count;
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int exec_array_size;
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2018-11-09 15:02:12 +00:00
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/**
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* A list of iris_syncpts associated with this batch.
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*
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* The first list entry will always be a signalling sync-point, indicating
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* that this batch has completed. The others are likely to be sync-points
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* to wait on before executing the batch.
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*/
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struct util_dynarray syncpts;
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2018-11-08 22:42:00 +00:00
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/** A list of drm_i915_exec_fences to have execbuf signal or wait on */
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struct util_dynarray exec_fences;
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2017-11-24 07:15:14 +00:00
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/** The amount of aperture space (in bytes) used by all exec_bos */
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int aperture_space;
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2018-11-20 04:41:26 +00:00
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/** A sync-point for the last batch that was submitted. */
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struct iris_syncpt *last_syncpt;
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2018-11-07 05:12:30 +00:00
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/** List of other batches which we might need to flush to use a BO */
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struct iris_batch *other_batches[IRIS_BATCH_COUNT - 1];
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2018-04-21 07:28:03 +01:00
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struct {
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/**
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* Set of struct brw_bo * that have been rendered to within this
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* batchbuffer and would need flushing before being used from another
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* cache domain that isn't coherent with it (i.e. the sampler).
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*/
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struct hash_table *render;
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/**
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* Set of struct brw_bo * that have been used as a depth buffer within
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* this batchbuffer and would need flushing before being used from
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* another cache domain that isn't coherent with it (i.e. the sampler).
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*/
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struct set *depth;
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} cache;
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2018-04-07 00:21:21 +01:00
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struct gen_batch_decode_ctx decoder;
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2018-06-13 11:07:00 +01:00
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/** Have we emitted any draw calls to this batch? */
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bool contains_draw;
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2017-11-24 07:15:14 +00:00
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};
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2018-01-21 07:11:37 +00:00
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void iris_init_batch(struct iris_batch *batch,
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2017-11-24 07:15:14 +00:00
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struct iris_screen *screen,
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2018-04-21 07:28:03 +01:00
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struct iris_vtable *vtbl,
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2018-01-21 07:11:37 +00:00
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struct pipe_debug_callback *dbg,
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2018-11-20 17:00:22 +00:00
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struct iris_batch *all_batches,
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enum iris_batch_name name,
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2018-01-21 07:11:37 +00:00
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uint8_t ring);
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2018-08-19 18:31:29 +01:00
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void iris_chain_to_new_batch(struct iris_batch *batch);
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2017-11-24 07:15:14 +00:00
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void iris_batch_free(struct iris_batch *batch);
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2018-05-03 03:54:23 +01:00
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void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
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2017-11-24 07:15:14 +00:00
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2018-11-08 22:42:00 +00:00
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void _iris_batch_flush(struct iris_batch *batch, const char *file, int line);
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#define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
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2017-11-24 07:15:14 +00:00
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bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
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#define RELOC_WRITE EXEC_OBJECT_WRITE
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2018-04-06 08:19:57 +01:00
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void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo,
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bool writable);
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2018-01-30 10:16:34 +00:00
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2018-08-19 18:31:29 +01:00
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static inline unsigned
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iris_batch_bytes_used(struct iris_batch *batch)
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{
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return batch->map_next - batch->map;
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}
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/**
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* Ensure the current command buffer has \param size bytes of space
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* remaining. If not, this creates a secondary batch buffer and emits
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* a jump from the primary batch to the start of the secondary.
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*
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* Most callers want iris_get_command_space() instead.
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*/
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static inline void
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iris_require_command_space(struct iris_batch *batch, unsigned size)
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{
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const unsigned required_bytes = iris_batch_bytes_used(batch) + size;
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if (required_bytes >= BATCH_SZ) {
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iris_chain_to_new_batch(batch);
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}
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}
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/**
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* Allocate space in the current command buffer, and return a pointer
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* to the mapped area so the caller can write commands there.
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*
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* This should be called whenever emitting commands.
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*/
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static inline void *
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iris_get_command_space(struct iris_batch *batch, unsigned bytes)
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{
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iris_require_command_space(batch, bytes);
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void *map = batch->map_next;
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batch->map_next += bytes;
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return map;
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}
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/**
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* Helper to emit GPU commands - allocates space, copies them there.
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*/
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static inline void
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iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
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{
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void *map = iris_get_command_space(batch, size);
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memcpy(map, data, size);
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}
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2017-11-24 07:15:14 +00:00
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#endif
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