iris: rewrite to use memzones and not relocs
This commit is contained in:
Kenneth Graunke
parent
68229caa38
commit
651be7cf3d
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@ -82,15 +82,6 @@ uint_key_hash(const void *key)
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return (uintptr_t) key;
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}
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static void
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init_reloc_list(struct iris_reloc_list *rlist, int count)
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{
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rlist->reloc_count = 0;
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rlist->reloc_array_size = count;
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rlist->relocs = malloc(rlist->reloc_array_size *
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sizeof(struct drm_i915_gem_relocation_entry));
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}
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static void
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create_batch_buffer(struct iris_bufmgr *bufmgr,
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struct iris_batch_buffer *buf,
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@ -116,9 +107,6 @@ iris_init_batch(struct iris_batch *batch,
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assert(util_bitcount(ring) == 1);
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batch->ring = ring;
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init_reloc_list(&batch->cmdbuf.relocs, 256);
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init_reloc_list(&batch->statebuf.relocs, 256);
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batch->exec_count = 0;
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batch->exec_array_size = 100;
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batch->exec_bos =
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@ -189,12 +177,6 @@ iris_batch_reset(struct iris_batch *batch)
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batch->last_cmd_bo = batch->cmdbuf.bo;
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create_batch_buffer(bufmgr, &batch->cmdbuf, "command buffer", BATCH_SZ);
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create_batch_buffer(bufmgr, &batch->statebuf, "state buffer", STATE_SZ);
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/* Avoid making 0 a valid state offset - otherwise the decoder will try
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* and decode data when we use offset 0 as a null pointer.
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*/
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batch->statebuf.map_next += 1;
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add_exec_bo(batch, batch->cmdbuf.bo);
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assert(batch->cmdbuf.bo->index == 0);
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@ -220,10 +202,6 @@ free_batch_buffer(struct iris_batch_buffer *buf)
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buf->bo = NULL;
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buf->map = NULL;
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buf->map_next = NULL;
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free(buf->relocs.relocs);
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buf->relocs.relocs = NULL;
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buf->relocs.reloc_array_size = 0;
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}
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void
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@ -235,7 +213,6 @@ iris_batch_free(struct iris_batch *batch)
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free(batch->exec_bos);
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free(batch->validation_list);
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free_batch_buffer(&batch->cmdbuf);
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free_batch_buffer(&batch->statebuf);
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iris_bo_unreference(batch->last_cmd_bo);
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@ -406,19 +383,6 @@ iris_require_command_space(struct iris_batch *batch, unsigned size)
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require_buffer_space(batch, &batch->cmdbuf, size, BATCH_SZ, MAX_BATCH_SIZE);
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}
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/**
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* Reserve some space in the statebuffer, or flush.
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*
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* This is used to estimate when we're near the end of the batch,
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* so we can flush early.
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*/
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void
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iris_require_state_space(struct iris_batch *batch, unsigned size)
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{
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require_buffer_space(batch, &batch->statebuf, size, STATE_SZ,
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MAX_STATE_SIZE);
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}
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void
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iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
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{
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@ -456,7 +420,6 @@ static int
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submit_batch(struct iris_batch *batch, int in_fence_fd, int *out_fence_fd)
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{
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iris_bo_unmap(batch->cmdbuf.bo);
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iris_bo_unmap(batch->statebuf.bo);
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/* The requirement for using I915_EXEC_NO_RELOC are:
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*
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@ -470,23 +433,6 @@ submit_batch(struct iris_batch *batch, int in_fence_fd, int *out_fence_fd)
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* To avoid stalling, execobject.offset should match the current
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* address of that object within the active context.
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*/
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/* Set statebuffer relocations */
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const unsigned state_index = batch->statebuf.bo->index;
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if (state_index < batch->exec_count &&
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batch->exec_bos[state_index] == batch->statebuf.bo) {
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struct drm_i915_gem_exec_object2 *entry =
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&batch->validation_list[state_index];
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assert(entry->handle == batch->statebuf.bo->gem_handle);
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entry->relocation_count = batch->statebuf.relocs.reloc_count;
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entry->relocs_ptr = (uintptr_t) batch->statebuf.relocs.relocs;
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}
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/* Set batchbuffer relocations */
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struct drm_i915_gem_exec_object2 *entry = &batch->validation_list[0];
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assert(entry->handle == batch->cmdbuf.bo->gem_handle);
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entry->relocation_count = batch->cmdbuf.relocs.reloc_count;
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entry->relocs_ptr = (uintptr_t) batch->cmdbuf.relocs.relocs;
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struct drm_i915_gem_execbuffer2 execbuf = {
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.buffers_ptr = (uintptr_t) batch->validation_list,
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.buffer_count = batch->exec_count,
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@ -568,16 +514,12 @@ _iris_batch_flush_fence(struct iris_batch *batch,
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if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT))) {
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int bytes_for_commands = buffer_bytes_used(&batch->cmdbuf);
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int bytes_for_state = buffer_bytes_used(&batch->statebuf);
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fprintf(stderr, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
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" %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
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" %4d batch relocs, %4d state relocs\n", file, line,
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fprintf(stderr, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%), "
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"%4d BOs (%0.1fMb aperture)\n",
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file, line,
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bytes_for_commands, 100.0f * bytes_for_commands / BATCH_SZ,
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bytes_for_state, 100.0f * bytes_for_state / STATE_SZ,
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batch->exec_count,
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(float) batch->aperture_space / (1024 * 1024),
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batch->cmdbuf.relocs.reloc_count,
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batch->statebuf.relocs.reloc_count);
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(float) batch->aperture_space / (1024 * 1024));
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}
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int ret = submit_batch(batch, in_fence_fd, out_fence_fd);
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@ -603,13 +545,9 @@ _iris_batch_flush_fence(struct iris_batch *batch,
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iris_bo_unreference(batch->exec_bos[i]);
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batch->exec_bos[i] = NULL;
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}
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batch->cmdbuf.relocs.reloc_count = 0;
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batch->statebuf.relocs.reloc_count = 0;
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batch->exec_count = 0;
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batch->aperture_space = 0;
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iris_bo_unreference(batch->statebuf.bo);
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/* Start a new batch buffer. */
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iris_batch_reset_and_clear_render_cache(batch);
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@ -630,46 +568,8 @@ iris_batch_references(struct iris_batch *batch, struct iris_bo *bo)
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return false;
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}
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/* This is the only way buffers get added to the validate list.
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/* This is the only way buffers get added to the validate list.
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*/
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static uint64_t
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emit_reloc(struct iris_batch *batch,
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struct iris_reloc_list *rlist, uint32_t offset,
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struct iris_bo *target, uint32_t target_offset,
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unsigned int reloc_flags)
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{
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assert(target != NULL);
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unsigned int index = add_exec_bo(batch, target);
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struct drm_i915_gem_exec_object2 *entry = &batch->validation_list[index];
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if (target->kflags & EXEC_OBJECT_PINNED) {
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assert(entry->offset == target->gtt_offset);
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return entry->offset + target_offset;
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}
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if (rlist->reloc_count == rlist->reloc_array_size) {
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rlist->reloc_array_size *= 2;
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rlist->relocs = realloc(rlist->relocs,
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rlist->reloc_array_size *
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sizeof(struct drm_i915_gem_relocation_entry));
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}
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rlist->relocs[rlist->reloc_count++] =
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(struct drm_i915_gem_relocation_entry) {
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.offset = offset,
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.delta = target_offset,
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.target_handle = index,
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.presumed_offset = entry->offset,
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};
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/* Using the old buffer offset, write in what the right data would be, in
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* case the buffer doesn't move and we can short-circuit the relocation
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* processing in the kernel
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*/
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return entry->offset + target_offset;
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}
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void
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iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo)
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{
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@ -677,79 +577,6 @@ iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo)
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add_exec_bo(batch, bo);
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}
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uint64_t
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iris_batch_reloc(struct iris_batch *batch, uint32_t batch_offset,
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struct iris_bo *target, uint32_t target_offset,
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unsigned int reloc_flags)
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{
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assert(batch_offset <= batch->cmdbuf.bo->size - sizeof(uint32_t));
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return emit_reloc(batch, &batch->cmdbuf.relocs, batch_offset,
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target, target_offset, reloc_flags);
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}
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uint64_t
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iris_state_reloc(struct iris_batch *batch, uint32_t state_offset,
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struct iris_bo *target, uint32_t target_offset,
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unsigned int reloc_flags)
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{
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assert(state_offset <= batch->statebuf.bo->size - sizeof(uint32_t));
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return emit_reloc(batch, &batch->statebuf.relocs, state_offset,
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target, target_offset, reloc_flags);
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}
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static uint32_t
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iris_state_entry_size(struct iris_batch *batch, uint32_t offset)
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{
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struct hash_entry *entry =
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_mesa_hash_table_search(batch->state_sizes, (void *)(uintptr_t) offset);
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return entry ? (uintptr_t) entry->data : 0;
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}
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/**
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* Allocates a block of space in the batchbuffer for indirect state.
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*/
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void *
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iris_alloc_state(struct iris_batch *batch,
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int size, int alignment,
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uint32_t *out_offset)
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{
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assert(size < batch->statebuf.bo->size);
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const unsigned existing_bytes = buffer_bytes_used(&batch->statebuf);
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unsigned aligned_size =
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ALIGN(existing_bytes, alignment) - existing_bytes + size;
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require_buffer_space(batch, &batch->statebuf, aligned_size,
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STATE_SZ, MAX_STATE_SIZE);
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unsigned offset = ALIGN(buffer_bytes_used(&batch->statebuf), alignment);
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if (unlikely(batch->state_sizes)) {
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_mesa_hash_table_insert(batch->state_sizes,
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(void *) (uintptr_t) offset,
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(void *) (uintptr_t) size);
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}
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batch->statebuf.map_next += aligned_size;
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*out_offset = offset;
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return batch->statebuf.map + offset;
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}
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uint32_t
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iris_emit_state(struct iris_batch *batch,
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const void *data,
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int size, int alignment)
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{
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uint32_t out_offset;
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void *dest = iris_alloc_state(batch, size, alignment, &out_offset);
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memcpy(dest, data, size);
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return out_offset;
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}
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static void
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decode_batch(struct iris_batch *batch)
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{
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@ -39,13 +39,7 @@
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struct iris_address {
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struct iris_bo *bo;
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unsigned reloc_flags;
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uint32_t offset;
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};
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struct iris_reloc_list {
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struct drm_i915_gem_relocation_entry *relocs;
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int reloc_count;
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int reloc_array_size;
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uint64_t offset;
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};
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struct iris_batch_buffer {
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@ -55,8 +49,6 @@ struct iris_batch_buffer {
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struct iris_bo *partial_bo;
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unsigned partial_bytes;
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struct iris_reloc_list relocs;
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};
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struct iris_batch {
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@ -65,8 +57,6 @@ struct iris_batch {
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/** Current batchbuffer being queued up. */
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struct iris_batch_buffer cmdbuf;
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/** Current statebuffer being queued up. */
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struct iris_batch_buffer statebuf;
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/** Last BO submitted to the hardware. Used for glFinish(). */
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struct iris_bo *last_cmd_bo;
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@ -99,12 +89,7 @@ void iris_init_batch(struct iris_batch *batch,
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uint8_t ring);
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void iris_batch_free(struct iris_batch *batch);
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void iris_require_command_space(struct iris_batch *batch, unsigned size);
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void iris_require_state_space(struct iris_batch *batch, unsigned size);
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void iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size);
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uint32_t iris_emit_state(struct iris_batch *batch, const void *data, int size,
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int alignment);
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void *iris_alloc_state(struct iris_batch *batch, int size, int alignment,
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uint32_t *out_offset);
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int _iris_batch_flush_fence(struct iris_batch *batch,
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int in_fence_fd, int *out_fence_fd,
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@ -123,15 +108,4 @@ bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
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void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo);
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uint64_t iris_batch_reloc(struct iris_batch *batch,
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uint32_t batch_offset,
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struct iris_bo *target,
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uint32_t target_offset,
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unsigned flags);
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uint64_t iris_state_reloc(struct iris_batch *batch,
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uint32_t batch_offset,
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struct iris_bo *target,
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uint32_t target_offset,
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unsigned flags);
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#endif
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@ -57,11 +57,11 @@ static uint64_t
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__gen_combine_address(struct iris_batch *batch, void *location,
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struct iris_address addr, uint32_t delta)
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{
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if (addr.bo == NULL)
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return addr.offset + delta;
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// XXX: reloc flags?
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if (addr.bo)
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iris_use_pinned_bo(batch, addr.bo);
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return iris_batch_reloc(batch, location - batch->cmdbuf.map, addr.bo,
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addr.offset + delta, addr.reloc_flags);
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return addr.offset + delta;
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}
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#define __genxml_cmd_length(cmd) cmd ## _length
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@ -105,26 +105,6 @@ get_command_space(struct iris_batch *batch, unsigned bytes)
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VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
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} while (0)
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#define iris_emit_with_addr(batch, dwords, num_dw, addr_field, addr) \
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do { \
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STATIC_ASSERT((GENX(addr_field) % 64) == 0); \
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assert(num_dw <= ARRAY_SIZE(dwords)); \
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int addr_idx = GENX(addr_field) / 32; \
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uint32_t *dw = get_command_space(batch, 4 * num_dw); \
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for (uint32_t i = 0; i < addr_idx; i++) { \
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dw[i] = (dwords)[i]; \
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} \
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uint64_t *qw = (uint64_t *) &dw[addr_idx]; \
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*qw = iris_batch_reloc(batch, (void *)qw - batch->cmdbuf.map, \
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addr.bo, \
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addr.offset + (dwords)[addr_idx + 1], \
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addr.reloc_flags); \
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for (uint32_t i = addr_idx + 1; i < num_dw; i++) { \
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dw[i] = (dwords)[i]; \
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} \
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VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dw * 4)); \
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} while (0)
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#include "genxml/genX_pack.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_bits.h"
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@ -290,11 +270,44 @@ translate_fill_mode(unsigned pipe_polymode)
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}
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static struct iris_address
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ro_bo(struct iris_bo *bo, uint32_t offset)
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ro_bo(struct iris_bo *bo, uint64_t offset)
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{
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return (struct iris_address) { .bo = bo, .offset = offset };
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}
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static uint32_t *
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stream_state(struct iris_batch *batch,
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struct u_upload_mgr *uploader,
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unsigned size,
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unsigned alignment,
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unsigned *out_offset)
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{
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struct pipe_resource *res = NULL;
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void *ptr = NULL;
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u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
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iris_use_pinned_bo(batch, ((struct iris_resource *) res)->bo);
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pipe_resource_reference(&res, NULL);
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return ptr;
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}
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static uint32_t
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emit_state(struct iris_batch *batch,
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struct u_upload_mgr *uploader,
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const void *data,
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unsigned size,
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unsigned alignment)
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{
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unsigned offset = 0;
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uint32_t *map = stream_state(batch, uploader, size, alignment, &offset);
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if (map)
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memcpy(map, data, size);
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return offset;
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}
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static void
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iris_emit_state_base_address(struct iris_batch *batch)
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{
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@ -323,13 +336,13 @@ iris_emit_state_base_address(struct iris_batch *batch)
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sba.IndirectObjectBufferSizeModifyEnable = true;
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sba.InstructionBuffersizeModifyEnable = true;
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sba.SurfaceStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
|
||||
sba.DynamicStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
|
||||
sba.SurfaceStateBaseAddress = ro_bo(NULL, 1ull << 32);
|
||||
sba.DynamicStateBaseAddress = ro_bo(NULL, 2 * (1ull << 32));
|
||||
|
||||
sba.GeneralStateBufferSize = 0xfffff;
|
||||
sba.IndirectObjectBufferSize = 0xfffff;
|
||||
sba.InstructionBufferSize = 0xfffff;
|
||||
sba.DynamicStateBufferSize = ALIGN(MAX_STATE_SIZE, 4096);
|
||||
sba.DynamicStateBufferSize = 0xfffff;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1806,32 +1819,6 @@ static const uint32_t push_constant_opcodes[] = {
|
|||
[MESA_SHADER_COMPUTE] = 0,
|
||||
};
|
||||
|
||||
static uint32_t
|
||||
emit_patched_surface_state(struct iris_batch *batch,
|
||||
uint32_t *surface_state,
|
||||
const struct iris_resource *res,
|
||||
unsigned reloc_flags)
|
||||
{
|
||||
const int num_dwords = GENX(RENDER_SURFACE_STATE_length);
|
||||
uint32_t offset;
|
||||
uint32_t *dw = iris_alloc_state(batch, 4 * num_dwords, 64, &offset);
|
||||
|
||||
STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start) % 32 == 0);
|
||||
int addr_idx = GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start) / 32;
|
||||
for (uint32_t i = 0; i < addr_idx; i++)
|
||||
dw[i] = surface_state[i];
|
||||
|
||||
uint64_t *qw = (uint64_t *) &dw[addr_idx];
|
||||
// XXX: mt->offset, if needed
|
||||
*qw = iris_state_reloc(batch, (void *)qw - batch->statebuf.map, res->bo,
|
||||
surface_state[addr_idx + 1], reloc_flags);
|
||||
|
||||
for (uint32_t i = addr_idx + 1; i < num_dwords; i++)
|
||||
dw[i] = surface_state[i];
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
static void
|
||||
iris_upload_render_state(struct iris_context *ice,
|
||||
struct iris_batch *batch,
|
||||
|
|
@ -1846,7 +1833,8 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
|
||||
iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
|
||||
ptr.CCViewportPointer =
|
||||
iris_emit_state(batch, cso->cc_vp, sizeof(cso->cc_vp), 32);
|
||||
emit_state(batch, ice->state.dynamic_uploader,
|
||||
cso->cc_vp, sizeof(cso->cc_vp), 32);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1854,9 +1842,9 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
struct iris_viewport_state *cso = ice->state.cso_vp;
|
||||
iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
|
||||
ptr.SFClipViewportPointer =
|
||||
iris_emit_state(batch, cso->sf_cl_vp,
|
||||
4 * GENX(SF_CLIP_VIEWPORT_length) *
|
||||
ice->state.num_viewports, 64);
|
||||
emit_state(batch, ice->state.dynamic_uploader, cso->sf_cl_vp,
|
||||
4 * GENX(SF_CLIP_VIEWPORT_length) *
|
||||
ice->state.num_viewports, 64);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1874,7 +1862,8 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
cso_fb->nr_cbufs * GENX(BLEND_STATE_ENTRY_length));
|
||||
uint32_t blend_offset;
|
||||
uint32_t *blend_map =
|
||||
iris_alloc_state(batch, num_dwords, 64, &blend_offset);
|
||||
stream_state(batch, ice->state.dynamic_uploader, 4 * num_dwords, 64,
|
||||
&blend_offset);
|
||||
|
||||
uint32_t blend_state_header;
|
||||
iris_pack_state(GENX(BLEND_STATE), &blend_state_header, bs) {
|
||||
|
|
@ -1896,9 +1885,9 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
|
||||
uint32_t cc_offset;
|
||||
void *cc_map =
|
||||
iris_alloc_state(batch,
|
||||
sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length),
|
||||
64, &cc_offset);
|
||||
stream_state(batch, ice->state.dynamic_uploader,
|
||||
sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length),
|
||||
64, &cc_offset);
|
||||
iris_pack_state(GENX(COLOR_CALC_STATE), cc_map, cc) {
|
||||
cc.AlphaTestFormat = ALPHATEST_FLOAT32;
|
||||
cc.AlphaReferenceValueAsFLOAT32 = cso->alpha.ref_value;
|
||||
|
|
@ -1966,8 +1955,9 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
uint32_t *bt_map = NULL;
|
||||
|
||||
if (prog_data->binding_table.size_bytes != 0) {
|
||||
bt_map = iris_alloc_state(batch, prog_data->binding_table.size_bytes,
|
||||
64, &bt_offset);
|
||||
bt_map = stream_state(batch, ice->state.surface_uploader,
|
||||
prog_data->binding_table.size_bytes,
|
||||
64, &bt_offset);
|
||||
}
|
||||
|
||||
iris_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), ptr) {
|
||||
|
|
@ -1983,9 +1973,10 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
|
||||
struct iris_surface *surf = (void *) cso_fb->cbufs[i];
|
||||
struct iris_resource *res = (void *) surf->pipe.texture;
|
||||
|
||||
*bt_map++ = emit_patched_surface_state(batch, surf->surface_state,
|
||||
res, RELOC_WRITE);
|
||||
*bt_map++ =
|
||||
emit_state(batch, ice->state.surface_uploader,
|
||||
surf->surface_state,
|
||||
4 * GENX(RENDER_SURFACE_STATE_length), 64);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1996,7 +1987,6 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
// XXX: these are per-context??????????? pipe_sampler_view::context
|
||||
*bt_map++ =
|
||||
emit_patched_surface_state(batch, view->surface_state, res, 0);
|
||||
|
||||
}
|
||||
|
||||
// XXX: not implemented yet
|
||||
|
|
@ -2019,9 +2009,9 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
const int count = IRIS_MAX_TEXTURE_SAMPLERS;
|
||||
|
||||
uint32_t offset;
|
||||
uint32_t *map = iris_alloc_state(batch,
|
||||
count * 4 * GENX(SAMPLER_STATE_length),
|
||||
32, &offset);
|
||||
uint32_t *map = stream_state(batch, ice->state.dynamic_uploader,
|
||||
count * 4 * GENX(SAMPLER_STATE_length),
|
||||
32, &offset);
|
||||
|
||||
for (int i = 0; i < count; i++) {
|
||||
// XXX: when we have a correct count, these better be bound
|
||||
|
|
@ -2169,9 +2159,9 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
|
||||
if (dirty & IRIS_DIRTY_SCISSOR) {
|
||||
uint32_t scissor_offset =
|
||||
iris_emit_state(batch, ice->state.scissors,
|
||||
sizeof(struct pipe_scissor_state) *
|
||||
ice->state.num_scissors, 32);
|
||||
emit_state(batch, ice->state.dynamic_uploader, ice->state.scissors,
|
||||
sizeof(struct pipe_scissor_state) *
|
||||
ice->state.num_scissors, 32);
|
||||
|
||||
iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
|
||||
ptr.ScissorRectPointer = scissor_offset;
|
||||
|
|
@ -2231,9 +2221,8 @@ iris_upload_render_state(struct iris_context *ice,
|
|||
sizeof(uint32_t) * (1 + 4 * cso->num_buffers));
|
||||
|
||||
for (unsigned i = 0; i < cso->num_buffers; i++) {
|
||||
*addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
|
||||
cso->bos[i].bo, cso->bos[i].offset +
|
||||
*delta, cso->bos[i].reloc_flags);
|
||||
iris_use_pinned_bo(batch, cso->bos[i].bo);
|
||||
*addr = cso->bos[i].offset + *delta;
|
||||
addr = (void *) addr + 16;
|
||||
delta = (void *) delta + 16;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue