2016-09-26 20:10:11 +01:00
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "anv_private.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#include "common/gen_l3_config.h"
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/**
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* This file implements some lightweight memcpy/memset operations on the GPU
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* using a vertex buffer and streamout.
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*/
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/**
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* Returns the greatest common divisor of a and b that is a power of two.
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*/
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2017-07-07 05:18:03 +01:00
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static uint64_t
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2016-09-26 20:10:11 +01:00
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gcd_pow2_u64(uint64_t a, uint64_t b)
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{
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assert(a > 0 || b > 0);
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unsigned a_log2 = ffsll(a) - 1;
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unsigned b_log2 = ffsll(b) - 1;
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/* If either a or b is 0, then a_log2 or b_log2 will be UINT_MAX in which
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* case, the MIN2() will take the other one. If both are 0 then we will
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* hit the assert above.
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*/
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return 1 << MIN2(a_log2, b_log2);
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}
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2017-01-25 22:54:39 +00:00
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void
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genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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struct anv_bo *dst, uint32_t dst_offset,
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struct anv_bo *src, uint32_t src_offset,
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uint32_t size)
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{
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/* This memcpy operates in units of dwords. */
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assert(size % 4 == 0);
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assert(dst_offset % 4 == 0);
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assert(src_offset % 4 == 0);
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2018-02-17 01:35:15 +00:00
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#if GEN_GEN == 7
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/* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
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* and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
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* in-flight when they are issued even if the memory touched is not
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* currently active for rendering. The weird bit is that it is not the
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* MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
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* rendering hangs such that the next stalling command after the
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* MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
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*
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* It is unclear exactly why this hang occurs. Both MI commands come with
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* warnings about the 3D pipeline but that doesn't seem to fully explain
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* it. My (Jason's) best theory is that it has something to do with the
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* fact that we're using a GPU state register as our temporary and that
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* something with reading/writing it is causing problems.
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*
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* In order to work around this issue, we emit a PIPE_CONTROL with the
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* command streamer stall bit set.
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*/
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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#endif
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2017-01-25 22:54:39 +00:00
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for (uint32_t i = 0; i < size; i += 4) {
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const struct anv_address src_addr =
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(struct anv_address) { src, src_offset + i};
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const struct anv_address dst_addr =
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(struct anv_address) { dst, dst_offset + i};
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#if GEN_GEN >= 8
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_COPY_MEM_MEM), cp) {
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cp.DestinationMemoryAddress = dst_addr;
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cp.SourceMemoryAddress = src_addr;
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}
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#else
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/* IVB does not have a general purpose register for command streamer
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* commands. Therefore, we use an alternate temporary register.
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*/
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#define TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), load) {
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load.RegisterAddress = TEMP_REG;
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load.MemoryAddress = src_addr;
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}
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), store) {
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store.RegisterAddress = TEMP_REG;
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store.MemoryAddress = dst_addr;
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}
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#undef TEMP_REG
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#endif
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}
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return;
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}
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2016-09-26 20:10:11 +01:00
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void
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2017-05-11 17:37:33 +01:00
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genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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struct anv_bo *dst, uint32_t dst_offset,
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struct anv_bo *src, uint32_t src_offset,
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uint32_t size)
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2016-09-26 20:10:11 +01:00
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{
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if (size == 0)
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return;
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assert(dst_offset + size <= dst->size);
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assert(src_offset + size <= src->size);
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/* The maximum copy block size is 4 32-bit components at a time. */
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unsigned bs = 16;
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bs = gcd_pow2_u64(bs, src_offset);
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bs = gcd_pow2_u64(bs, dst_offset);
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bs = gcd_pow2_u64(bs, size);
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enum isl_format format;
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switch (bs) {
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case 4: format = ISL_FORMAT_R32_UINT; break;
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case 8: format = ISL_FORMAT_R32G32_UINT; break;
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case 16: format = ISL_FORMAT_R32G32B32A32_UINT; break;
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default:
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unreachable("Invalid size");
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}
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if (!cmd_buffer->state.current_l3_config) {
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const struct gen_l3_config *cfg =
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gen_get_default_l3_config(&cmd_buffer->device->info);
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genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
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}
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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genX(flush_pipeline_select_3d)(cmd_buffer);
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uint32_t *dw;
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dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
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GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,
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&(struct GENX(VERTEX_BUFFER_STATE)) {
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.VertexBufferIndex = 32, /* Reserved for this */
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.AddressModifyEnable = true,
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.BufferStartingAddress = { src, src_offset },
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.BufferPitch = bs,
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#if (GEN_GEN >= 8)
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.MemoryObjectControlState = GENX(MOCS),
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.BufferSize = size,
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#else
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.VertexBufferMemoryObjectControlState = GENX(MOCS),
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.EndAddress = { src, src_offset + size - 1 },
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#endif
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});
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dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
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GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1,
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&(struct GENX(VERTEX_ELEMENT_STATE)) {
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.VertexBufferIndex = 32,
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.Valid = true,
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2017-08-26 04:08:58 +01:00
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.SourceElementFormat = (enum GENX(SURFACE_FORMAT)) format,
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2016-09-26 20:10:11 +01:00
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.SourceElementOffset = 0,
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.Component0Control = (bs >= 4) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component1Control = (bs >= 8) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component2Control = (bs >= 12) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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});
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#if GEN_GEN >= 8
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs);
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#endif
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/* Disable all shader stages */
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_TE), te);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DS), DS);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_GS), gs);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PS), gs);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SBE), sbe) {
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sbe.VertexURBEntryReadOffset = 1;
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sbe.NumberofSFOutputAttributes = 1;
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sbe.VertexURBEntryReadLength = 1;
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#if GEN_GEN >= 8
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sbe.ForceVertexURBEntryReadLength = true;
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sbe.ForceVertexURBEntryReadOffset = true;
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#endif
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#if GEN_GEN >= 9
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for (unsigned i = 0; i < 32; i++)
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sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
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#endif
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}
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/* Emit URB setup. We tell it that the VS is active because we want it to
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* allocate space for the VS. Even though one isn't run, we need VUEs to
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* store the data that VF is going to pass to SOL.
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*/
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2016-11-15 19:43:07 +00:00
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const unsigned entry_size[4] = { DIV_ROUND_UP(32, 64), 1, 1, 1 };
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2016-09-26 20:10:11 +01:00
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genX(emit_urb_setup)(cmd_buffer->device, &cmd_buffer->batch,
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2016-11-15 19:43:07 +00:00
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cmd_buffer->state.current_l3_config,
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VK_SHADER_STAGE_VERTEX_BIT, entry_size);
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2016-09-26 20:10:11 +01:00
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
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sob.SOBufferIndex = 0;
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sob.SOBufferObjectControlState = GENX(MOCS);
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sob.SurfaceBaseAddress = (struct anv_address) { dst, dst_offset };
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#if GEN_GEN >= 8
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sob.SOBufferEnable = true;
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sob.SurfaceSize = size - 1;
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#else
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sob.SurfacePitch = bs;
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sob.SurfaceEndAddress = sob.SurfaceBaseAddress;
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sob.SurfaceEndAddress.offset += size;
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#endif
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#if GEN_GEN >= 8
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/* As SOL writes out data, it updates the SO_WRITE_OFFSET registers with
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* the end position of the stream. We need to reset this value to 0 at
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* the beginning of the run or else SOL will start at the offset from
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* the previous draw.
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*/
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sob.StreamOffsetWriteEnable = true;
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sob.StreamOffset = 0;
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#endif
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}
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#if GEN_GEN <= 7
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/* The hardware can do this for us on BDW+ (see above) */
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), load) {
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load.RegisterOffset = GENX(SO_WRITE_OFFSET0_num);
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load.DataDWord = 0;
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}
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#endif
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dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_SO_DECL_LIST),
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.StreamtoBufferSelects0 = (1 << 0),
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.NumEntries0 = 1);
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GENX(SO_DECL_ENTRY_pack)(&cmd_buffer->batch, dw + 3,
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&(struct GENX(SO_DECL_ENTRY)) {
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.Stream0Decl = {
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.OutputBufferSlot = 0,
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.RegisterIndex = 0,
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.ComponentMask = (1 << (bs / 4)) - 1,
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},
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});
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STREAMOUT), so) {
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so.SOFunctionEnable = true;
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so.RenderingDisable = true;
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so.Stream0VertexReadOffset = 0;
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so.Stream0VertexReadLength = DIV_ROUND_UP(32, 64);
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#if GEN_GEN >= 8
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so.Buffer0SurfacePitch = bs;
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#else
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so.SOBufferEnable0 = true;
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#endif
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}
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#if GEN_GEN >= 8
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
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topo.PrimitiveTopologyType = _3DPRIM_POINTLIST;
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}
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#endif
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2017-03-16 21:12:03 +00:00
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_STATISTICS), vf) {
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vf.StatisticsEnable = false;
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}
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2016-09-26 20:10:11 +01:00
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anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
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prim.VertexAccessType = SEQUENTIAL;
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prim.PrimitiveTopologyType = _3DPRIM_POINTLIST;
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prim.VertexCountPerInstance = size / bs;
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prim.StartVertexLocation = 0;
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prim.InstanceCount = 1;
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prim.StartInstanceLocation = 0;
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prim.BaseVertexLocation = 0;
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}
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2017-12-16 00:38:10 +00:00
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
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2016-09-26 20:10:11 +01:00
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}
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