2013-10-17 13:21:40 +01:00
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/**************************************************************************
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*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#include <unistd.h>
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#include "util/u_memory.h"
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#include "util/u_video.h"
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#include "vl/vl_defines.h"
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#include "vl/vl_video_buffer.h"
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#include "r600_pipe_common.h"
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#include "radeon_video.h"
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2013-10-17 13:21:40 +01:00
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#include "radeon_vce.h"
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2013-10-17 13:21:40 +01:00
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/* generate an stream handle */
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2017-09-13 01:26:26 +01:00
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unsigned si_vid_alloc_stream_handle()
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2013-10-17 13:21:40 +01:00
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{
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static unsigned counter = 0;
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unsigned stream_handle = 0;
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unsigned pid = getpid();
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int i;
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for (i = 0; i < 32; ++i)
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stream_handle |= ((pid >> i) & 1) << (31 - i);
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stream_handle ^= ++counter;
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return stream_handle;
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}
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/* create a buffer in the winsys */
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2017-09-13 01:26:26 +01:00
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bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
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unsigned size, unsigned usage)
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2013-10-17 13:21:40 +01:00
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{
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2014-09-11 08:29:28 +01:00
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memset(buffer, 0, sizeof(*buffer));
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buffer->usage = usage;
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2016-09-30 10:26:13 +01:00
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/* Hardware buffer placement restrictions require the kernel to be
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* able to move buffers around individually, so request a
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* non-sub-allocated buffer.
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*/
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2014-09-11 08:29:28 +01:00
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buffer->res = (struct r600_resource *)
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2016-10-24 22:26:39 +01:00
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pipe_buffer_create(screen, PIPE_BIND_SHARED,
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2016-09-30 10:26:13 +01:00
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usage, size);
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2014-01-21 18:49:06 +00:00
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2014-09-11 08:29:28 +01:00
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return buffer->res != NULL;
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2013-10-17 13:21:40 +01:00
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}
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/* destroy a buffer */
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2017-09-13 01:26:26 +01:00
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void si_vid_destroy_buffer(struct rvid_buffer *buffer)
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2013-10-17 13:21:40 +01:00
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{
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2016-06-21 20:13:00 +01:00
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r600_resource_reference(&buffer->res, NULL);
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2013-10-17 13:21:40 +01:00
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}
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/* reallocate a buffer, preserving its content */
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2017-09-13 01:26:26 +01:00
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bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
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struct rvid_buffer *new_buf, unsigned new_size)
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2013-10-17 13:21:40 +01:00
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{
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2014-09-11 08:29:28 +01:00
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struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
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struct radeon_winsys* ws = rscreen->ws;
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unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
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2013-10-17 13:21:40 +01:00
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struct rvid_buffer old_buf = *new_buf;
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void *src = NULL, *dst = NULL;
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2017-09-13 01:26:26 +01:00
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if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage))
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2013-10-17 13:21:40 +01:00
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goto error;
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2015-12-06 23:00:59 +00:00
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src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
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2013-10-17 13:21:40 +01:00
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if (!src)
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goto error;
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2015-12-06 23:00:59 +00:00
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dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
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2013-10-17 13:21:40 +01:00
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if (!dst)
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goto error;
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memcpy(dst, src, bytes);
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if (new_size > bytes) {
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new_size -= bytes;
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dst += bytes;
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memset(dst, 0, new_size);
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}
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2015-12-06 23:00:59 +00:00
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ws->buffer_unmap(new_buf->res->buf);
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ws->buffer_unmap(old_buf.res->buf);
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2017-09-13 01:26:26 +01:00
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si_vid_destroy_buffer(&old_buf);
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2013-10-17 13:21:40 +01:00
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return true;
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error:
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if (src)
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2015-12-06 23:00:59 +00:00
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ws->buffer_unmap(old_buf.res->buf);
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2017-09-13 01:26:26 +01:00
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si_vid_destroy_buffer(new_buf);
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2013-10-17 13:21:40 +01:00
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*new_buf = old_buf;
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return false;
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}
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/* clear the buffer with zeros */
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2017-09-13 01:26:26 +01:00
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void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
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2013-10-17 13:21:40 +01:00
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{
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2014-09-11 08:38:50 +01:00
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struct r600_common_context *rctx = (struct r600_common_context*)context;
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2013-10-17 13:21:40 +01:00
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2016-12-24 22:00:27 +00:00
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rctx->dma_clear_buffer(context, &buffer->res->b.b, 0,
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buffer->res->buf->size, 0);
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2014-09-11 08:38:50 +01:00
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context->flush(context, NULL, 0);
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2013-10-17 13:21:40 +01:00
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}
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/**
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* join surfaces into the same buffer with identical tiling params
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* sumup their sizes and replace the backend buffers with a single bo
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*/
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2017-09-13 01:26:26 +01:00
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void si_vid_join_surfaces(struct r600_common_context *rctx,
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struct pb_buffer** buffers[VL_NUM_COMPONENTS],
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struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
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2013-10-17 13:21:40 +01:00
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{
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2017-02-09 15:25:20 +00:00
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struct radeon_winsys* ws;
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2013-10-17 13:21:40 +01:00
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unsigned best_tiling, best_wh, off;
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unsigned size, alignment;
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struct pb_buffer *pb;
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unsigned i, j;
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2017-02-09 15:25:20 +00:00
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ws = rctx->ws;
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2013-10-17 13:21:40 +01:00
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for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
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unsigned wh;
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if (!surfaces[i])
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continue;
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2017-02-09 15:25:20 +00:00
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if (rctx->chip_class < GFX9) {
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/* choose the smallest bank w/h for now */
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wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
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if (wh < best_wh) {
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best_wh = wh;
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best_tiling = i;
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}
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2013-10-17 13:21:40 +01:00
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}
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}
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for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!surfaces[i])
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continue;
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/* adjust the texture layer offsets */
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2016-10-23 20:26:43 +01:00
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off = align(off, surfaces[i]->surf_alignment);
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2017-02-09 15:25:20 +00:00
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if (rctx->chip_class < GFX9) {
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/* copy the tiling parameters */
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surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
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surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
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surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
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surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
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for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
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surfaces[i]->u.legacy.level[j].offset += off;
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2017-10-25 14:46:17 +01:00
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} else {
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2017-02-09 15:25:20 +00:00
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surfaces[i]->u.gfx9.surf_offset += off;
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2017-10-25 14:46:17 +01:00
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for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
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surfaces[i]->u.gfx9.offset[j] += off;
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}
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2017-02-09 15:25:20 +00:00
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2016-10-23 20:26:43 +01:00
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off += surfaces[i]->surf_size;
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2013-10-17 13:21:40 +01:00
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}
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for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!buffers[i] || !*buffers[i])
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continue;
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size = align(size, (*buffers[i])->alignment);
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size += (*buffers[i])->size;
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alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
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}
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if (!size)
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return;
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/* TODO: 2D tiling workaround */
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alignment *= 2;
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2017-07-05 00:14:03 +01:00
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pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
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RADEON_FLAG_GTT_WC);
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2013-10-17 13:21:40 +01:00
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if (!pb)
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return;
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!buffers[i] || !*buffers[i])
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continue;
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pb_reference(buffers[i], pb);
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}
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pb_reference(&pb, NULL);
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}
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