2013-10-17 13:21:40 +01:00
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/**************************************************************************
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*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors:
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* Christian König <christian.koenig@amd.com>
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*
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*/
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#include <unistd.h>
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#include "util/u_memory.h"
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#include "util/u_video.h"
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#include "vl/vl_defines.h"
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#include "vl/vl_video_buffer.h"
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#include "r600_pipe_common.h"
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#include "radeon_video.h"
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2013-10-17 13:21:40 +01:00
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#include "radeon_vce.h"
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2013-10-17 13:21:40 +01:00
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2016-07-07 10:20:30 +01:00
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#define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
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2013-10-17 13:21:40 +01:00
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/* generate an stream handle */
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unsigned rvid_alloc_stream_handle()
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{
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static unsigned counter = 0;
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unsigned stream_handle = 0;
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unsigned pid = getpid();
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int i;
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for (i = 0; i < 32; ++i)
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stream_handle |= ((pid >> i) & 1) << (31 - i);
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stream_handle ^= ++counter;
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return stream_handle;
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}
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/* create a buffer in the winsys */
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2014-09-11 08:29:28 +01:00
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bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
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unsigned size, unsigned usage)
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2013-10-17 13:21:40 +01:00
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{
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2014-09-11 08:29:28 +01:00
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memset(buffer, 0, sizeof(*buffer));
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buffer->usage = usage;
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buffer->res = (struct r600_resource *)
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pipe_buffer_create(screen, PIPE_BIND_CUSTOM, usage, size);
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2014-01-21 18:49:06 +00:00
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2014-09-11 08:29:28 +01:00
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return buffer->res != NULL;
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2013-10-17 13:21:40 +01:00
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}
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/* destroy a buffer */
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void rvid_destroy_buffer(struct rvid_buffer *buffer)
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{
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2016-06-21 20:13:00 +01:00
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r600_resource_reference(&buffer->res, NULL);
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2013-10-17 13:21:40 +01:00
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}
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/* reallocate a buffer, preserving its content */
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2014-09-11 08:29:28 +01:00
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bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
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2013-10-17 13:21:40 +01:00
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struct rvid_buffer *new_buf, unsigned new_size)
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{
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2014-09-11 08:29:28 +01:00
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struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
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struct radeon_winsys* ws = rscreen->ws;
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unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
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2013-10-17 13:21:40 +01:00
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struct rvid_buffer old_buf = *new_buf;
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void *src = NULL, *dst = NULL;
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2014-09-11 08:29:28 +01:00
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if (!rvid_create_buffer(screen, new_buf, new_size, new_buf->usage))
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2013-10-17 13:21:40 +01:00
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goto error;
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2015-12-06 23:00:59 +00:00
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src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
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2013-10-17 13:21:40 +01:00
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if (!src)
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goto error;
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2015-12-06 23:00:59 +00:00
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dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
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2013-10-17 13:21:40 +01:00
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if (!dst)
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goto error;
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memcpy(dst, src, bytes);
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if (new_size > bytes) {
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new_size -= bytes;
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dst += bytes;
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memset(dst, 0, new_size);
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}
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2015-12-06 23:00:59 +00:00
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ws->buffer_unmap(new_buf->res->buf);
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ws->buffer_unmap(old_buf.res->buf);
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2013-10-17 13:21:40 +01:00
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rvid_destroy_buffer(&old_buf);
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return true;
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error:
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if (src)
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2015-12-06 23:00:59 +00:00
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ws->buffer_unmap(old_buf.res->buf);
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2013-10-17 13:21:40 +01:00
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rvid_destroy_buffer(new_buf);
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*new_buf = old_buf;
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return false;
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}
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/* clear the buffer with zeros */
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2014-09-11 08:38:50 +01:00
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void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
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2013-10-17 13:21:40 +01:00
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{
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2014-09-11 08:38:50 +01:00
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struct r600_common_context *rctx = (struct r600_common_context*)context;
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2013-10-17 13:21:40 +01:00
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2014-12-29 13:45:49 +00:00
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rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size,
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2016-04-22 09:26:28 +01:00
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0, R600_COHERENCY_NONE);
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2014-09-11 08:38:50 +01:00
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context->flush(context, NULL, 0);
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2013-10-17 13:21:40 +01:00
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}
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/**
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* join surfaces into the same buffer with identical tiling params
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* sumup their sizes and replace the backend buffers with a single bo
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*/
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2016-04-23 04:50:19 +01:00
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void rvid_join_surfaces(struct radeon_winsys* ws,
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2013-10-17 13:21:40 +01:00
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struct pb_buffer** buffers[VL_NUM_COMPONENTS],
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2015-04-16 21:53:04 +01:00
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struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
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2013-10-17 13:21:40 +01:00
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{
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unsigned best_tiling, best_wh, off;
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unsigned size, alignment;
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struct pb_buffer *pb;
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unsigned i, j;
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for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
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unsigned wh;
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if (!surfaces[i])
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continue;
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/* choose the smallest bank w/h for now */
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wh = surfaces[i]->bankw * surfaces[i]->bankh;
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if (wh < best_wh) {
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best_wh = wh;
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best_tiling = i;
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}
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}
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for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!surfaces[i])
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continue;
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/* copy the tiling parameters */
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surfaces[i]->bankw = surfaces[best_tiling]->bankw;
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surfaces[i]->bankh = surfaces[best_tiling]->bankh;
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surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
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surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
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/* adjust the texture layer offsets */
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off = align(off, surfaces[i]->bo_alignment);
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2016-05-17 14:25:44 +01:00
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for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j)
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2013-10-17 13:21:40 +01:00
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surfaces[i]->level[j].offset += off;
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off += surfaces[i]->bo_size;
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}
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for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!buffers[i] || !*buffers[i])
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continue;
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size = align(size, (*buffers[i])->alignment);
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size += (*buffers[i])->size;
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alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
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}
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if (!size)
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return;
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/* TODO: 2D tiling workaround */
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alignment *= 2;
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2016-04-23 04:58:38 +01:00
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pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0);
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2013-10-17 13:21:40 +01:00
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if (!pb)
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return;
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for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
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if (!buffers[i] || !*buffers[i])
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continue;
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pb_reference(buffers[i], pb);
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}
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pb_reference(&pb, NULL);
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}
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int rvid_get_video_param(struct pipe_screen *screen,
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enum pipe_video_profile profile,
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enum pipe_video_entrypoint entrypoint,
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enum pipe_video_cap param)
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{
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struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
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2015-10-22 17:24:42 +01:00
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enum pipe_video_format codec = u_reduce_video_profile(profile);
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2016-07-07 10:20:30 +01:00
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struct radeon_info info;
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rscreen->ws->query_info(rscreen->ws, &info);
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2013-10-17 13:21:40 +01:00
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2013-10-17 13:21:40 +01:00
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if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
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switch (param) {
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case PIPE_VIDEO_CAP_SUPPORTED:
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2015-10-22 17:24:42 +01:00
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return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
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2013-10-17 13:21:40 +01:00
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rvce_is_fw_version_supported(rscreen);
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2016-07-07 09:56:23 +01:00
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case PIPE_VIDEO_CAP_NPOT_TEXTURES:
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return 1;
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case PIPE_VIDEO_CAP_MAX_WIDTH:
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2015-03-09 20:24:48 +00:00
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return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
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2016-07-07 09:56:23 +01:00
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case PIPE_VIDEO_CAP_MAX_HEIGHT:
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2015-03-09 20:24:48 +00:00
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return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
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2016-07-07 09:56:23 +01:00
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case PIPE_VIDEO_CAP_PREFERED_FORMAT:
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return PIPE_FORMAT_NV12;
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case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
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return false;
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case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
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return false;
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case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
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return true;
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case PIPE_VIDEO_CAP_STACKED_FRAMES:
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2015-06-25 17:12:12 +01:00
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return (rscreen->family < CHIP_TONGA) ? 1 : 2;
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2016-07-07 09:56:23 +01:00
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default:
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return 0;
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2013-10-17 13:21:40 +01:00
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}
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}
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2013-10-17 13:21:40 +01:00
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switch (param) {
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case PIPE_VIDEO_CAP_SUPPORTED:
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2015-10-22 17:24:42 +01:00
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switch (codec) {
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2013-10-17 13:21:40 +01:00
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case PIPE_VIDEO_FORMAT_MPEG12:
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2016-02-05 08:25:59 +00:00
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return profile != PIPE_VIDEO_PROFILE_MPEG1;
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2013-10-17 13:21:40 +01:00
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case PIPE_VIDEO_FORMAT_MPEG4:
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2016-07-07 10:20:30 +01:00
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/* no support for MPEG4 on older hw */
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return rscreen->family >= CHIP_PALM;
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2013-10-17 13:21:40 +01:00
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case PIPE_VIDEO_FORMAT_MPEG4_AVC:
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2016-07-07 10:20:30 +01:00
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if ((rscreen->family == CHIP_POLARIS10 ||
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rscreen->family == CHIP_POLARIS11) &&
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info.uvd_fw_version < UVD_FW_1_66_16 ) {
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RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
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return false;
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}
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2015-10-22 17:24:42 +01:00
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return true;
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2013-10-17 13:21:40 +01:00
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case PIPE_VIDEO_FORMAT_VC1:
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2015-09-23 09:11:08 +01:00
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return true;
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2015-07-08 21:54:48 +01:00
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case PIPE_VIDEO_FORMAT_HEVC:
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/* Carrizo only supports HEVC Main */
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2015-12-22 01:06:26 +00:00
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if (rscreen->family >= CHIP_STONEY)
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return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
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profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
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else if (rscreen->family >= CHIP_CARRIZO)
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return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
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2013-10-17 13:21:40 +01:00
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default:
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return false;
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}
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case PIPE_VIDEO_CAP_NPOT_TEXTURES:
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return 1;
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case PIPE_VIDEO_CAP_MAX_WIDTH:
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2015-03-09 20:24:48 +00:00
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return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
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2013-10-17 13:21:40 +01:00
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case PIPE_VIDEO_CAP_MAX_HEIGHT:
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2016-03-07 09:47:29 +00:00
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return (rscreen->family < CHIP_TONGA) ? 1152 : 4096;
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2013-10-17 13:21:40 +01:00
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case PIPE_VIDEO_CAP_PREFERED_FORMAT:
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return PIPE_FORMAT_NV12;
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case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
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case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
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2015-10-22 17:24:42 +01:00
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if (rscreen->family < CHIP_PALM) {
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/* MPEG2 only with shaders and no support for
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interlacing on R6xx style UVD */
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return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
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rscreen->family > CHIP_RV770;
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} else {
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if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
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return false; //The firmware doesn't support interlaced HEVC.
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return true;
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}
|
2013-10-17 13:21:40 +01:00
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case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
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return true;
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case PIPE_VIDEO_CAP_MAX_LEVEL:
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switch (profile) {
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case PIPE_VIDEO_PROFILE_MPEG1:
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return 0;
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case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
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case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
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return 3;
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case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
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return 3;
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case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
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return 5;
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case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
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return 1;
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|
|
case PIPE_VIDEO_PROFILE_VC1_MAIN:
|
|
|
|
return 2;
|
|
|
|
case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
|
|
|
|
return 4;
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
|
2016-05-25 15:55:48 +01:00
|
|
|
return (rscreen->family < CHIP_TONGA) ? 41 : 52;
|
2015-07-08 21:54:48 +01:00
|
|
|
case PIPE_VIDEO_PROFILE_HEVC_MAIN:
|
2015-12-22 01:06:26 +00:00
|
|
|
case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
|
2015-07-08 21:54:48 +01:00
|
|
|
return 186;
|
2013-10-17 13:21:40 +01:00
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
boolean rvid_is_format_supported(struct pipe_screen *screen,
|
|
|
|
enum pipe_format format,
|
|
|
|
enum pipe_video_profile profile,
|
|
|
|
enum pipe_video_entrypoint entrypoint)
|
|
|
|
{
|
|
|
|
/* we can only handle this one with UVD */
|
|
|
|
if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
|
|
|
|
return format == PIPE_FORMAT_NV12;
|
|
|
|
|
|
|
|
return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
|
|
|
|
}
|