2015-11-18 20:25:11 +00:00
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "anv_private.h"
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2016-02-20 17:08:27 +00:00
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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2015-11-18 20:25:11 +00:00
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void
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genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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struct anv_bo *scratch_bo = NULL;
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cmd_buffer->state.scratch_size =
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anv_block_pool_size(&device->scratch_block_pool);
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if (cmd_buffer->state.scratch_size > 0)
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scratch_bo = &device->scratch_block_pool.bo;
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/* XXX: Do we need this on more than just BDW? */
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2016-02-20 17:08:27 +00:00
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#if (GEN_GEN >= 8)
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2015-11-18 20:25:11 +00:00
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/* Emit a render target cache flush.
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*
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* This isn't documented anywhere in the PRM. However, it seems to be
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* necessary prior to changing the surface state base adress. Without
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* this, we get GPU hangs when using multi-level command buffers which
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* clear depth, reset state base address, and then go render stuff.
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*/
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2016-01-21 22:14:01 +00:00
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
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2015-11-18 20:25:11 +00:00
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.RenderTargetCacheFlushEnable = true);
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#endif
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anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS),
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.GeneralStateBaseAddress = { scratch_bo, 0 },
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.GeneralStateMemoryObjectControlState = GENX(MOCS),
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.GeneralStateBaseAddressModifyEnable = true,
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.SurfaceStateBaseAddress = anv_cmd_buffer_surface_base_address(cmd_buffer),
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.SurfaceStateMemoryObjectControlState = GENX(MOCS),
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.SurfaceStateBaseAddressModifyEnable = true,
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.DynamicStateBaseAddress = { &device->dynamic_state_block_pool.bo, 0 },
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.DynamicStateMemoryObjectControlState = GENX(MOCS),
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.DynamicStateBaseAddressModifyEnable = true,
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.IndirectObjectBaseAddress = { NULL, 0 },
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.IndirectObjectMemoryObjectControlState = GENX(MOCS),
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.IndirectObjectBaseAddressModifyEnable = true,
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.InstructionBaseAddress = { &device->instruction_block_pool.bo, 0 },
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.InstructionMemoryObjectControlState = GENX(MOCS),
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.InstructionBaseAddressModifyEnable = true,
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2016-02-20 17:08:27 +00:00
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# if (GEN_GEN >= 8)
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2015-11-18 20:25:11 +00:00
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/* Broadwell requires that we specify a buffer size for a bunch of
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* these fields. However, since we will be growing the BO's live, we
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* just set them all to the maximum.
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*/
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.GeneralStateBufferSize = 0xfffff,
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.GeneralStateBufferSizeModifyEnable = true,
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.DynamicStateBufferSize = 0xfffff,
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.DynamicStateBufferSizeModifyEnable = true,
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.IndirectObjectBufferSize = 0xfffff,
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.IndirectObjectBufferSizeModifyEnable = true,
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.InstructionBufferSize = 0xfffff,
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.InstructionBuffersizeModifyEnable = true,
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# endif
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);
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/* After re-setting the surface state base address, we have to do some
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* cache flusing so that the sampler engine will pick up the new
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* SURFACE_STATE objects and binding tables. From the Broadwell PRM,
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* Shared Function > 3D Sampler > State > State Caching (page 96):
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*
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* Coherency with system memory in the state cache, like the texture
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* cache is handled partially by software. It is expected that the
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* command stream or shader will issue Cache Flush operation or
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* Cache_Flush sampler message to ensure that the L1 cache remains
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* coherent with system memory.
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*
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* [...]
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*
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* Whenever the value of the Dynamic_State_Base_Addr,
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* Surface_State_Base_Addr are altered, the L1 state cache must be
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* invalidated to ensure the new surface or sampler state is fetched
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* from system memory.
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*
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* The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
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* which, according the PIPE_CONTROL instruction documentation in the
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* Broadwell PRM:
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*
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* Setting this bit is independent of any other bit in this packet.
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* This bit controls the invalidation of the L1 and L2 state caches
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* at the top of the pipe i.e. at the parsing time.
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*
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* Unfortunately, experimentation seems to indicate that state cache
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* invalidation through a PIPE_CONTROL does nothing whatsoever in
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* regards to surface state and binding tables. In stead, it seems that
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* invalidating the texture cache is what is actually needed.
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*
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* XXX: As far as we have been able to determine through
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* experimentation, shows that flush the texture cache appears to be
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* sufficient. The theory here is that all of the sampling/rendering
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* units cache the binding table in the texture cache. However, we have
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* yet to be able to actually confirm this.
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*/
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
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.TextureCacheInvalidationEnable = true);
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}
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void genX(CmdPipelineBarrier)(
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2015-11-30 19:48:08 +00:00
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VkCommandBuffer commandBuffer,
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2015-11-18 20:25:11 +00:00
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VkPipelineStageFlags srcStageMask,
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VkPipelineStageFlags destStageMask,
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VkBool32 byRegion,
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2016-01-14 16:09:39 +00:00
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uint32_t memoryBarrierCount,
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const VkMemoryBarrier* pMemoryBarriers,
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uint32_t bufferMemoryBarrierCount,
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const VkBufferMemoryBarrier* pBufferMemoryBarriers,
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uint32_t imageMemoryBarrierCount,
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const VkImageMemoryBarrier* pImageMemoryBarriers)
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2015-11-18 20:25:11 +00:00
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{
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2015-11-30 19:48:08 +00:00
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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2015-11-18 20:25:11 +00:00
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uint32_t b, *dw;
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/* XXX: Right now, we're really dumb and just flush whatever categories
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* the app asks for. One of these days we may make this a bit better
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* but right now that's all the hardware allows for in most areas.
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*/
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2015-12-01 21:39:28 +00:00
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VkAccessFlags src_flags = 0;
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VkAccessFlags dst_flags = 0;
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2015-11-18 20:25:11 +00:00
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2016-01-14 16:09:39 +00:00
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for (uint32_t i = 0; i < memoryBarrierCount; i++) {
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src_flags |= pMemoryBarriers[i].srcAccessMask;
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dst_flags |= pMemoryBarriers[i].dstAccessMask;
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}
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for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
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src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
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dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
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}
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for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
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src_flags |= pImageMemoryBarriers[i].srcAccessMask;
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dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
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2015-11-18 20:25:11 +00:00
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}
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2016-02-17 23:09:40 +00:00
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/* Mask out the Source access flags we care about */
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const uint32_t src_mask =
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VK_ACCESS_SHADER_WRITE_BIT |
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VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT |
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VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT |
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VK_ACCESS_TRANSFER_WRITE_BIT;
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src_flags = src_flags & src_mask;
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/* Mask out the destination access flags we care about */
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const uint32_t dst_mask =
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VK_ACCESS_INDIRECT_COMMAND_READ_BIT |
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VK_ACCESS_INDEX_READ_BIT |
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VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT |
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VK_ACCESS_UNIFORM_READ_BIT |
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VK_ACCESS_SHADER_READ_BIT |
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VK_ACCESS_COLOR_ATTACHMENT_READ_BIT |
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VK_ACCESS_TRANSFER_READ_BIT;
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dst_flags = dst_flags & dst_mask;
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2015-12-03 19:05:52 +00:00
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/* The src flags represent how things were used previously. This is
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* what we use for doing flushes.
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*/
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2016-02-17 23:09:40 +00:00
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struct GENX(PIPE_CONTROL) flush_cmd = {
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GENX(PIPE_CONTROL_header),
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.PostSyncOperation = NoWrite,
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};
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2015-12-03 19:05:52 +00:00
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for_each_bit(b, src_flags) {
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2015-12-01 21:39:28 +00:00
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switch ((VkAccessFlagBits)(1 << b)) {
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case VK_ACCESS_SHADER_WRITE_BIT:
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2016-02-17 23:09:40 +00:00
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flush_cmd.DCFlushEnable = true;
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2015-11-18 20:25:11 +00:00
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break;
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2015-12-01 21:39:28 +00:00
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case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
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2016-02-17 23:09:40 +00:00
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flush_cmd.RenderTargetCacheFlushEnable = true;
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2015-11-18 20:25:11 +00:00
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break;
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2015-12-01 21:39:28 +00:00
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case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
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2016-02-17 23:09:40 +00:00
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flush_cmd.DepthCacheFlushEnable = true;
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2015-11-18 20:25:11 +00:00
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break;
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2015-12-01 21:39:28 +00:00
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case VK_ACCESS_TRANSFER_WRITE_BIT:
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2016-02-17 23:09:40 +00:00
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flush_cmd.RenderTargetCacheFlushEnable = true;
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flush_cmd.DepthCacheFlushEnable = true;
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2015-11-18 20:25:11 +00:00
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break;
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default:
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2016-02-17 23:09:40 +00:00
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unreachable("should've masked this out by now");
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2015-11-18 20:25:11 +00:00
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}
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}
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2016-02-17 23:09:40 +00:00
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/* If we end up doing two PIPE_CONTROLs, the first, flusing one also has to
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* stall and wait for the flushing to finish, so we don't re-dirty the
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* caches with in-flight rendering after the second PIPE_CONTROL
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* invalidates.
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*/
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if (dst_flags)
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flush_cmd.CommandStreamerStallEnable = true;
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if (src_flags && dst_flags) {
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dw = anv_batch_emit_dwords(&cmd_buffer->batch, GENX(PIPE_CONTROL_length));
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GENX(PIPE_CONTROL_pack)(&cmd_buffer->batch, dw, &flush_cmd);
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}
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/* The dst flags represent how things will be used in the future. This
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2015-12-03 19:05:52 +00:00
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* is what we use for doing cache invalidations.
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*/
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2016-02-17 23:09:40 +00:00
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struct GENX(PIPE_CONTROL) invalidate_cmd = {
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GENX(PIPE_CONTROL_header),
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.PostSyncOperation = NoWrite,
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};
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2015-12-03 19:05:52 +00:00
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for_each_bit(b, dst_flags) {
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2015-12-01 21:39:28 +00:00
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switch ((VkAccessFlagBits)(1 << b)) {
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case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
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case VK_ACCESS_INDEX_READ_BIT:
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case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
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2016-02-17 23:09:40 +00:00
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invalidate_cmd.VFCacheInvalidationEnable = true;
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2015-11-18 20:25:11 +00:00
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break;
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2015-12-01 21:39:28 +00:00
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case VK_ACCESS_UNIFORM_READ_BIT:
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2016-02-17 23:09:40 +00:00
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invalidate_cmd.ConstantCacheInvalidationEnable = true;
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2015-11-18 20:25:11 +00:00
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/* fallthrough */
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2015-12-01 21:39:28 +00:00
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case VK_ACCESS_SHADER_READ_BIT:
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2016-02-17 23:09:40 +00:00
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invalidate_cmd.TextureCacheInvalidationEnable = true;
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2015-11-18 20:25:11 +00:00
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break;
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2015-12-01 21:39:28 +00:00
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case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
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2016-02-17 23:09:40 +00:00
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invalidate_cmd.TextureCacheInvalidationEnable = true;
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2015-11-18 20:25:11 +00:00
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break;
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2015-12-01 21:39:28 +00:00
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case VK_ACCESS_TRANSFER_READ_BIT:
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2016-02-17 23:09:40 +00:00
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invalidate_cmd.TextureCacheInvalidationEnable = true;
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2015-12-01 21:39:28 +00:00
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break;
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default:
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2016-02-17 23:09:40 +00:00
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unreachable("should've masked this out by now");
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2015-11-18 20:25:11 +00:00
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}
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}
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2016-02-17 23:09:40 +00:00
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if (dst_flags) {
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dw = anv_batch_emit_dwords(&cmd_buffer->batch, GENX(PIPE_CONTROL_length));
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GENX(PIPE_CONTROL_pack)(&cmd_buffer->batch, dw, &invalidate_cmd);
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}
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2015-11-18 20:25:11 +00:00
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}
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2016-02-06 00:41:56 +00:00
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2016-03-09 01:10:05 +00:00
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static uint32_t
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cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
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{
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static const uint32_t push_constant_opcodes[] = {
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[MESA_SHADER_VERTEX] = 21,
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[MESA_SHADER_TESS_CTRL] = 25, /* HS */
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[MESA_SHADER_TESS_EVAL] = 26, /* DS */
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[MESA_SHADER_GEOMETRY] = 22,
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[MESA_SHADER_FRAGMENT] = 23,
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[MESA_SHADER_COMPUTE] = 0,
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};
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VkShaderStageFlags flushed = 0;
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anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
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if (stage == MESA_SHADER_COMPUTE)
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continue;
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struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
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if (state.offset == 0) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
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._3DCommandSubOpcode = push_constant_opcodes[stage]);
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} else {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
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._3DCommandSubOpcode = push_constant_opcodes[stage],
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.ConstantBody = {
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#if GEN_GEN >= 9
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.PointerToConstantBuffer2 = { &cmd_buffer->device->dynamic_state_block_pool.bo, state.offset },
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.ConstantBuffer2ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
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#else
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|
|
|
.PointerToConstantBuffer0 = { .offset = state.offset },
|
|
|
|
.ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
|
|
|
|
#endif
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
flushed |= mesa_to_vk_shader_stage(stage);
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd_buffer->state.push_constants_dirty &= ~VK_SHADER_STAGE_ALL_GRAPHICS;
|
|
|
|
|
|
|
|
return flushed;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
|
|
|
|
{
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
|
|
|
uint32_t *p;
|
|
|
|
|
|
|
|
uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
|
|
|
|
|
|
|
|
assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
|
|
|
|
|
2016-03-12 16:54:41 +00:00
|
|
|
#if GEN_GEN >= 8
|
|
|
|
/* FIXME (jason): Currently, the config_l3 function causes problems on
|
|
|
|
* Haswell and prior if you have a kernel older than 4.4. In order to
|
|
|
|
* work, it requires a couple of registers be white-listed in the
|
|
|
|
* command parser and they weren't added until 4.4. What we should do
|
|
|
|
* is check the command parser version and make it a no-op if your
|
|
|
|
* command parser is either off or too old. Compute won't work 100%,
|
|
|
|
* but at least 3-D will. In the mean time, I'm going to make this
|
|
|
|
* gen8+ only so that we can get Haswell working again.
|
|
|
|
*/
|
2016-03-09 01:10:05 +00:00
|
|
|
genX(cmd_buffer_config_l3)(cmd_buffer, false);
|
2016-03-12 16:54:41 +00:00
|
|
|
#endif
|
2016-03-09 01:10:05 +00:00
|
|
|
|
|
|
|
genX(flush_pipeline_select_3d)(cmd_buffer);
|
|
|
|
|
|
|
|
if (vb_emit) {
|
|
|
|
const uint32_t num_buffers = __builtin_popcount(vb_emit);
|
|
|
|
const uint32_t num_dwords = 1 + num_buffers * 4;
|
|
|
|
|
|
|
|
p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
|
|
|
|
GENX(3DSTATE_VERTEX_BUFFERS));
|
|
|
|
uint32_t vb, i = 0;
|
|
|
|
for_each_bit(vb, vb_emit) {
|
|
|
|
struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
|
|
|
|
uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
|
|
|
|
|
|
|
|
struct GENX(VERTEX_BUFFER_STATE) state = {
|
|
|
|
.VertexBufferIndex = vb,
|
|
|
|
|
|
|
|
#if GEN_GEN >= 8
|
|
|
|
.MemoryObjectControlState = GENX(MOCS),
|
|
|
|
#else
|
|
|
|
.BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
|
|
|
|
.InstanceDataStepRate = 1,
|
|
|
|
.VertexBufferMemoryObjectControlState = GENX(MOCS),
|
|
|
|
#endif
|
|
|
|
|
|
|
|
.AddressModifyEnable = true,
|
|
|
|
.BufferPitch = pipeline->binding_stride[vb],
|
|
|
|
.BufferStartingAddress = { buffer->bo, buffer->offset + offset },
|
|
|
|
|
|
|
|
#if GEN_GEN >= 8
|
|
|
|
.BufferSize = buffer->size - offset
|
|
|
|
#else
|
|
|
|
.EndAddress = { buffer->bo, buffer->offset + buffer->size - 1},
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd_buffer->state.vb_dirty &= ~vb_emit;
|
|
|
|
|
|
|
|
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
|
|
|
|
/* If somebody compiled a pipeline after starting a command buffer the
|
|
|
|
* scratch bo may have grown since we started this cmd buffer (and
|
|
|
|
* emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
|
|
|
|
* reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
|
|
|
|
if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
|
|
|
|
anv_cmd_buffer_emit_state_base_address(cmd_buffer);
|
|
|
|
|
|
|
|
anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
|
|
|
|
|
|
|
|
/* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
|
|
|
|
*
|
|
|
|
* "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
|
|
|
|
* the next 3DPRIMITIVE command after programming the
|
|
|
|
* 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
|
|
|
|
*
|
|
|
|
* Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
|
|
|
|
* pipeline setup, we need to dirty push constants.
|
|
|
|
*/
|
|
|
|
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if GEN_GEN <= 7
|
|
|
|
if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
|
|
|
|
cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
|
|
|
|
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
|
|
|
|
*
|
|
|
|
* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
|
|
|
|
* stall needs to be sent just prior to any 3DSTATE_VS,
|
|
|
|
* 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
|
|
|
|
* 3DSTATE_BINDING_TABLE_POINTER_VS,
|
|
|
|
* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
|
|
|
|
* PIPE_CONTROL needs to be sent before any combination of VS
|
|
|
|
* associated 3DSTATE."
|
|
|
|
*/
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
|
|
|
|
.DepthStallEnable = true,
|
|
|
|
.PostSyncOperation = WriteImmediateData,
|
|
|
|
.Address = { &cmd_buffer->device->workaround_bo, 0 });
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* We emit the binding tables and sampler tables first, then emit push
|
|
|
|
* constants and then finally emit binding table and sampler table
|
|
|
|
* pointers. It has to happen in this order, since emitting the binding
|
|
|
|
* tables may change the push constants (in case of storage images). After
|
|
|
|
* emitting push constants, on SKL+ we have to emit the corresponding
|
|
|
|
* 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
|
|
|
|
*/
|
|
|
|
uint32_t dirty = 0;
|
|
|
|
if (cmd_buffer->state.descriptors_dirty)
|
|
|
|
dirty = gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
|
|
|
|
|
|
|
|
if (cmd_buffer->state.push_constants_dirty) {
|
|
|
|
#if GEN_GEN >= 9
|
|
|
|
/* On Sky Lake and later, the binding table pointers commands are
|
|
|
|
* what actually flush the changes to push constant state so we need
|
|
|
|
* to dirty them so they get re-emitted below.
|
|
|
|
*/
|
|
|
|
dirty |= cmd_buffer_flush_push_constants(cmd_buffer);
|
|
|
|
#else
|
|
|
|
cmd_buffer_flush_push_constants(cmd_buffer);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dirty)
|
|
|
|
gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
|
|
|
|
|
|
|
|
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
|
|
|
|
gen8_cmd_buffer_emit_viewport(cmd_buffer);
|
|
|
|
|
|
|
|
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
|
|
|
|
gen7_cmd_buffer_emit_scissor(cmd_buffer);
|
|
|
|
|
|
|
|
genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
|
|
|
|
}
|
|
|
|
|
2016-02-06 00:41:56 +00:00
|
|
|
static void
|
|
|
|
emit_base_vertex_instance_bo(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
struct anv_bo *bo, uint32_t offset)
|
|
|
|
{
|
|
|
|
uint32_t *p = anv_batch_emitn(&cmd_buffer->batch, 5,
|
|
|
|
GENX(3DSTATE_VERTEX_BUFFERS));
|
|
|
|
|
|
|
|
GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, p + 1,
|
|
|
|
&(struct GENX(VERTEX_BUFFER_STATE)) {
|
|
|
|
.VertexBufferIndex = 32, /* Reserved for this */
|
|
|
|
.AddressModifyEnable = true,
|
|
|
|
.BufferPitch = 0,
|
2016-02-20 17:08:27 +00:00
|
|
|
#if (GEN_GEN >= 8)
|
2016-02-06 00:41:56 +00:00
|
|
|
.MemoryObjectControlState = GENX(MOCS),
|
|
|
|
.BufferStartingAddress = { bo, offset },
|
|
|
|
.BufferSize = 8
|
|
|
|
#else
|
|
|
|
.VertexBufferMemoryObjectControlState = GENX(MOCS),
|
|
|
|
.BufferStartingAddress = { bo, offset },
|
|
|
|
.EndAddress = { bo, offset + 8 },
|
|
|
|
#endif
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_base_vertex_instance(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
uint32_t base_vertex, uint32_t base_instance)
|
|
|
|
{
|
|
|
|
struct anv_state id_state =
|
|
|
|
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 8, 4);
|
|
|
|
|
|
|
|
((uint32_t *)id_state.map)[0] = base_vertex;
|
|
|
|
((uint32_t *)id_state.map)[1] = base_instance;
|
|
|
|
|
|
|
|
if (!cmd_buffer->device->info.has_llc)
|
|
|
|
anv_state_clflush(id_state);
|
|
|
|
|
|
|
|
emit_base_vertex_instance_bo(cmd_buffer,
|
|
|
|
&cmd_buffer->device->dynamic_state_block_pool.bo, id_state.offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdDraw)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
uint32_t vertexCount,
|
|
|
|
uint32_t instanceCount,
|
|
|
|
uint32_t firstVertex,
|
|
|
|
uint32_t firstInstance)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
2016-03-04 16:15:16 +00:00
|
|
|
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
|
2016-02-06 00:41:56 +00:00
|
|
|
|
|
|
|
genX(cmd_buffer_flush_state)(cmd_buffer);
|
|
|
|
|
2016-03-04 16:15:16 +00:00
|
|
|
if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
|
2016-02-06 00:41:56 +00:00
|
|
|
emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
|
|
|
|
.VertexAccessType = SEQUENTIAL,
|
|
|
|
.PrimitiveTopologyType = pipeline->topology,
|
|
|
|
.VertexCountPerInstance = vertexCount,
|
|
|
|
.StartVertexLocation = firstVertex,
|
|
|
|
.InstanceCount = instanceCount,
|
|
|
|
.StartInstanceLocation = firstInstance,
|
|
|
|
.BaseVertexLocation = 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdDrawIndexed)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
uint32_t indexCount,
|
|
|
|
uint32_t instanceCount,
|
|
|
|
uint32_t firstIndex,
|
|
|
|
int32_t vertexOffset,
|
|
|
|
uint32_t firstInstance)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
2016-03-04 16:15:16 +00:00
|
|
|
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
|
2016-02-06 00:41:56 +00:00
|
|
|
|
|
|
|
genX(cmd_buffer_flush_state)(cmd_buffer);
|
|
|
|
|
2016-03-04 16:15:16 +00:00
|
|
|
if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
|
2016-02-06 00:41:56 +00:00
|
|
|
emit_base_vertex_instance(cmd_buffer, vertexOffset, firstInstance);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
|
|
|
|
.VertexAccessType = RANDOM,
|
|
|
|
.PrimitiveTopologyType = pipeline->topology,
|
|
|
|
.VertexCountPerInstance = indexCount,
|
|
|
|
.StartVertexLocation = firstIndex,
|
|
|
|
.InstanceCount = instanceCount,
|
|
|
|
.StartInstanceLocation = firstInstance,
|
|
|
|
.BaseVertexLocation = vertexOffset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Auto-Draw / Indirect Registers */
|
|
|
|
#define GEN7_3DPRIM_END_OFFSET 0x2420
|
|
|
|
#define GEN7_3DPRIM_START_VERTEX 0x2430
|
|
|
|
#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
|
|
|
|
#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
|
|
|
|
#define GEN7_3DPRIM_START_INSTANCE 0x243C
|
|
|
|
#define GEN7_3DPRIM_BASE_VERTEX 0x2440
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_lrm(struct anv_batch *batch,
|
|
|
|
uint32_t reg, struct anv_bo *bo, uint32_t offset)
|
|
|
|
{
|
|
|
|
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
|
|
|
|
.RegisterAddress = reg,
|
|
|
|
.MemoryAddress = { bo, offset });
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
|
|
|
|
{
|
|
|
|
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
|
|
|
|
.RegisterOffset = reg,
|
|
|
|
.DataDWord = imm);
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdDrawIndirect)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
VkBuffer _buffer,
|
|
|
|
VkDeviceSize offset,
|
|
|
|
uint32_t drawCount,
|
|
|
|
uint32_t stride)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
2016-03-04 16:15:16 +00:00
|
|
|
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
|
2016-02-06 00:41:56 +00:00
|
|
|
struct anv_bo *bo = buffer->bo;
|
|
|
|
uint32_t bo_offset = buffer->offset + offset;
|
|
|
|
|
|
|
|
genX(cmd_buffer_flush_state)(cmd_buffer);
|
|
|
|
|
2016-03-04 16:15:16 +00:00
|
|
|
if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
|
2016-02-06 00:41:56 +00:00
|
|
|
emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 8);
|
|
|
|
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
|
|
|
|
emit_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
|
|
|
|
.IndirectParameterEnable = true,
|
|
|
|
.VertexAccessType = SEQUENTIAL,
|
|
|
|
.PrimitiveTopologyType = pipeline->topology);
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdDrawIndexedIndirect)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
VkBuffer _buffer,
|
|
|
|
VkDeviceSize offset,
|
|
|
|
uint32_t drawCount,
|
|
|
|
uint32_t stride)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
2016-03-04 16:15:16 +00:00
|
|
|
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
|
2016-02-06 00:41:56 +00:00
|
|
|
struct anv_bo *bo = buffer->bo;
|
|
|
|
uint32_t bo_offset = buffer->offset + offset;
|
|
|
|
|
|
|
|
genX(cmd_buffer_flush_state)(cmd_buffer);
|
|
|
|
|
|
|
|
/* TODO: We need to stomp base vertex to 0 somehow */
|
2016-03-04 16:15:16 +00:00
|
|
|
if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
|
2016-02-06 00:41:56 +00:00
|
|
|
emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 12);
|
|
|
|
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
|
|
|
|
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
|
|
|
|
.IndirectParameterEnable = true,
|
|
|
|
.VertexAccessType = RANDOM,
|
|
|
|
.PrimitiveTopologyType = pipeline->topology);
|
|
|
|
}
|
2016-02-06 06:36:53 +00:00
|
|
|
|
|
|
|
|
|
|
|
void genX(CmdDispatch)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
uint32_t x,
|
|
|
|
uint32_t y,
|
|
|
|
uint32_t z)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
|
2016-03-04 16:15:16 +00:00
|
|
|
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
|
2016-02-06 06:36:53 +00:00
|
|
|
|
|
|
|
if (prog_data->uses_num_work_groups) {
|
|
|
|
struct anv_state state =
|
|
|
|
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 12, 4);
|
|
|
|
uint32_t *sizes = state.map;
|
|
|
|
sizes[0] = x;
|
|
|
|
sizes[1] = y;
|
|
|
|
sizes[2] = z;
|
|
|
|
if (!cmd_buffer->device->info.has_llc)
|
|
|
|
anv_state_clflush(state);
|
|
|
|
cmd_buffer->state.num_workgroups_offset = state.offset;
|
|
|
|
cmd_buffer->state.num_workgroups_bo =
|
|
|
|
&cmd_buffer->device->dynamic_state_block_pool.bo;
|
|
|
|
}
|
|
|
|
|
|
|
|
genX(cmd_buffer_flush_compute_state)(cmd_buffer);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER),
|
|
|
|
.SIMDSize = prog_data->simd_size / 16,
|
|
|
|
.ThreadDepthCounterMaximum = 0,
|
|
|
|
.ThreadHeightCounterMaximum = 0,
|
|
|
|
.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1,
|
|
|
|
.ThreadGroupIDXDimension = x,
|
|
|
|
.ThreadGroupIDYDimension = y,
|
|
|
|
.ThreadGroupIDZDimension = z,
|
|
|
|
.RightExecutionMask = pipeline->cs_right_mask,
|
|
|
|
.BottomExecutionMask = 0xffffffff);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH));
|
|
|
|
}
|
|
|
|
|
|
|
|
#define GPGPU_DISPATCHDIMX 0x2500
|
|
|
|
#define GPGPU_DISPATCHDIMY 0x2504
|
|
|
|
#define GPGPU_DISPATCHDIMZ 0x2508
|
|
|
|
|
2016-03-02 09:11:29 +00:00
|
|
|
#define MI_PREDICATE_SRC0 0x2400
|
|
|
|
#define MI_PREDICATE_SRC1 0x2408
|
|
|
|
|
2016-02-06 06:36:53 +00:00
|
|
|
void genX(CmdDispatchIndirect)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
VkBuffer _buffer,
|
|
|
|
VkDeviceSize offset)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
|
2016-03-04 16:15:16 +00:00
|
|
|
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
|
2016-02-06 06:36:53 +00:00
|
|
|
struct anv_bo *bo = buffer->bo;
|
|
|
|
uint32_t bo_offset = buffer->offset + offset;
|
2016-03-02 09:09:16 +00:00
|
|
|
struct anv_batch *batch = &cmd_buffer->batch;
|
2016-02-06 06:36:53 +00:00
|
|
|
|
|
|
|
if (prog_data->uses_num_work_groups) {
|
|
|
|
cmd_buffer->state.num_workgroups_offset = bo_offset;
|
|
|
|
cmd_buffer->state.num_workgroups_bo = bo;
|
|
|
|
}
|
|
|
|
|
|
|
|
genX(cmd_buffer_flush_compute_state)(cmd_buffer);
|
|
|
|
|
2016-03-02 09:09:16 +00:00
|
|
|
emit_lrm(batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
|
|
|
|
emit_lrm(batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
|
|
|
|
emit_lrm(batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
|
2016-02-06 06:36:53 +00:00
|
|
|
|
2016-03-02 09:11:29 +00:00
|
|
|
#if GEN_GEN <= 7
|
|
|
|
/* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
|
|
|
|
emit_lri(batch, MI_PREDICATE_SRC0 + 4, 0);
|
|
|
|
emit_lri(batch, MI_PREDICATE_SRC1 + 0, 0);
|
|
|
|
emit_lri(batch, MI_PREDICATE_SRC1 + 4, 0);
|
|
|
|
|
|
|
|
/* Load compute_dispatch_indirect_x_size into SRC0 */
|
|
|
|
emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 0);
|
|
|
|
|
|
|
|
/* predicate = (compute_dispatch_indirect_x_size == 0); */
|
|
|
|
anv_batch_emit(batch, GENX(MI_PREDICATE),
|
|
|
|
.LoadOperation = LOAD_LOAD,
|
|
|
|
.CombineOperation = COMBINE_SET,
|
|
|
|
.CompareOperation = COMPARE_SRCS_EQUAL);
|
|
|
|
|
|
|
|
/* Load compute_dispatch_indirect_y_size into SRC0 */
|
|
|
|
emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 4);
|
|
|
|
|
|
|
|
/* predicate |= (compute_dispatch_indirect_y_size == 0); */
|
|
|
|
anv_batch_emit(batch, GENX(MI_PREDICATE),
|
|
|
|
.LoadOperation = LOAD_LOAD,
|
|
|
|
.CombineOperation = COMBINE_OR,
|
|
|
|
.CompareOperation = COMPARE_SRCS_EQUAL);
|
|
|
|
|
|
|
|
/* Load compute_dispatch_indirect_z_size into SRC0 */
|
|
|
|
emit_lrm(batch, MI_PREDICATE_SRC0, bo, bo_offset + 8);
|
|
|
|
|
|
|
|
/* predicate |= (compute_dispatch_indirect_z_size == 0); */
|
|
|
|
anv_batch_emit(batch, GENX(MI_PREDICATE),
|
|
|
|
.LoadOperation = LOAD_LOAD,
|
|
|
|
.CombineOperation = COMBINE_OR,
|
|
|
|
.CompareOperation = COMPARE_SRCS_EQUAL);
|
|
|
|
|
|
|
|
/* predicate = !predicate; */
|
|
|
|
#define COMPARE_FALSE 1
|
|
|
|
anv_batch_emit(batch, GENX(MI_PREDICATE),
|
|
|
|
.LoadOperation = LOAD_LOADINV,
|
|
|
|
.CombineOperation = COMBINE_OR,
|
|
|
|
.CompareOperation = COMPARE_FALSE);
|
|
|
|
#endif
|
|
|
|
|
2016-03-02 09:09:16 +00:00
|
|
|
anv_batch_emit(batch, GENX(GPGPU_WALKER),
|
2016-02-06 06:36:53 +00:00
|
|
|
.IndirectParameterEnable = true,
|
2016-03-02 09:11:29 +00:00
|
|
|
.PredicateEnable = GEN_GEN <= 7,
|
2016-02-06 06:36:53 +00:00
|
|
|
.SIMDSize = prog_data->simd_size / 16,
|
|
|
|
.ThreadDepthCounterMaximum = 0,
|
|
|
|
.ThreadHeightCounterMaximum = 0,
|
|
|
|
.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1,
|
|
|
|
.RightExecutionMask = pipeline->cs_right_mask,
|
|
|
|
.BottomExecutionMask = 0xffffffff);
|
|
|
|
|
2016-03-02 09:09:16 +00:00
|
|
|
anv_batch_emit(batch, GENX(MEDIA_STATE_FLUSH));
|
2016-02-06 06:36:53 +00:00
|
|
|
}
|
2016-02-15 06:45:41 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
|
|
|
|
{
|
|
|
|
if (cmd_buffer->state.current_pipeline != _3D) {
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
|
2016-02-20 17:08:27 +00:00
|
|
|
#if GEN_GEN >= 9
|
2016-02-15 06:45:41 +00:00
|
|
|
.MaskBits = 3,
|
|
|
|
#endif
|
|
|
|
.PipelineSelection = _3D);
|
|
|
|
cmd_buffer->state.current_pipeline = _3D;
|
|
|
|
}
|
|
|
|
}
|
2016-02-15 07:01:42 +00:00
|
|
|
|
2016-03-11 01:16:58 +00:00
|
|
|
void
|
|
|
|
genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer)
|
|
|
|
{
|
|
|
|
if (cmd_buffer->state.current_pipeline != GPGPU) {
|
|
|
|
#if GEN_GEN >= 8 && GEN_GEN < 10
|
|
|
|
/* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
|
|
|
|
*
|
|
|
|
* Software must clear the COLOR_CALC_STATE Valid field in
|
|
|
|
* 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
|
|
|
|
* with Pipeline Select set to GPGPU.
|
|
|
|
*
|
|
|
|
* The internal hardware docs recommend the same workaround for Gen9
|
|
|
|
* hardware too.
|
|
|
|
*/
|
|
|
|
anv_batch_emit(&cmd_buffer->batch,
|
|
|
|
GENX(3DSTATE_CC_STATE_POINTERS));
|
|
|
|
#endif
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
|
|
|
|
#if GEN_GEN >= 9
|
|
|
|
.MaskBits = 3,
|
|
|
|
#endif
|
|
|
|
.PipelineSelection = GPGPU);
|
|
|
|
cmd_buffer->state.current_pipeline = GPGPU;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-26 19:31:04 +00:00
|
|
|
struct anv_state
|
|
|
|
genX(cmd_buffer_alloc_null_surface_state)(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
struct anv_framebuffer *fb)
|
|
|
|
{
|
|
|
|
struct anv_state state =
|
|
|
|
anv_state_stream_alloc(&cmd_buffer->surface_state_stream, 64, 64);
|
|
|
|
|
|
|
|
struct GENX(RENDER_SURFACE_STATE) null_ss = {
|
|
|
|
.SurfaceType = SURFTYPE_NULL,
|
|
|
|
.SurfaceArray = fb->layers > 0,
|
|
|
|
.SurfaceFormat = ISL_FORMAT_R8G8B8A8_UNORM,
|
|
|
|
#if GEN_GEN >= 8
|
|
|
|
.TileMode = YMAJOR,
|
|
|
|
#else
|
|
|
|
.TiledSurface = true,
|
|
|
|
#endif
|
|
|
|
.Width = fb->width - 1,
|
|
|
|
.Height = fb->height - 1,
|
|
|
|
.Depth = fb->layers - 1,
|
|
|
|
.RenderTargetViewExtent = fb->layers - 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
GENX(RENDER_SURFACE_STATE_pack)(NULL, state.map, &null_ss);
|
|
|
|
|
|
|
|
if (!cmd_buffer->device->info.has_llc)
|
|
|
|
anv_state_clflush(state);
|
|
|
|
|
|
|
|
return state;
|
|
|
|
}
|
|
|
|
|
2016-02-15 07:01:42 +00:00
|
|
|
static void
|
|
|
|
cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
|
|
|
|
{
|
|
|
|
struct anv_device *device = cmd_buffer->device;
|
|
|
|
const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
|
|
const struct anv_image_view *iview =
|
|
|
|
anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
|
|
|
|
const struct anv_image *image = iview ? iview->image : NULL;
|
|
|
|
const struct anv_format *anv_format =
|
|
|
|
iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
|
|
|
|
const bool has_depth = iview && anv_format->has_depth;
|
|
|
|
const bool has_stencil = iview && anv_format->has_stencil;
|
|
|
|
|
|
|
|
/* FIXME: Implement the PMA stall W/A */
|
|
|
|
/* FIXME: Width and Height are wrong */
|
|
|
|
|
|
|
|
/* Emit 3DSTATE_DEPTH_BUFFER */
|
|
|
|
if (has_depth) {
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
|
|
|
|
.SurfaceType = SURFTYPE_2D,
|
|
|
|
.DepthWriteEnable = true,
|
|
|
|
.StencilWriteEnable = has_stencil,
|
|
|
|
.HierarchicalDepthBufferEnable = false,
|
|
|
|
.SurfaceFormat = isl_surf_get_depth_format(&device->isl_dev,
|
|
|
|
&image->depth_surface.isl),
|
|
|
|
.SurfacePitch = image->depth_surface.isl.row_pitch - 1,
|
|
|
|
.SurfaceBaseAddress = {
|
|
|
|
.bo = image->bo,
|
2016-03-01 17:17:16 +00:00
|
|
|
.offset = image->offset + image->depth_surface.offset,
|
2016-02-15 07:01:42 +00:00
|
|
|
},
|
|
|
|
.Height = fb->height - 1,
|
|
|
|
.Width = fb->width - 1,
|
|
|
|
.LOD = 0,
|
|
|
|
.Depth = 1 - 1,
|
|
|
|
.MinimumArrayElement = 0,
|
|
|
|
.DepthBufferObjectControlState = GENX(MOCS),
|
2016-02-20 17:08:27 +00:00
|
|
|
#if GEN_GEN >= 8
|
2016-02-15 07:01:42 +00:00
|
|
|
.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2,
|
|
|
|
#endif
|
|
|
|
.RenderTargetViewExtent = 1 - 1);
|
|
|
|
} else {
|
|
|
|
/* Even when no depth buffer is present, the hardware requires that
|
|
|
|
* 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
|
|
|
|
*
|
|
|
|
* If a null depth buffer is bound, the driver must instead bind depth as:
|
|
|
|
* 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
|
|
|
|
* 3DSTATE_DEPTH.Width = 1
|
|
|
|
* 3DSTATE_DEPTH.Height = 1
|
|
|
|
* 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
|
|
|
|
* 3DSTATE_DEPTH.SurfaceBaseAddress = 0
|
|
|
|
* 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
|
|
|
|
* 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
|
|
|
|
* 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
|
|
|
|
*
|
|
|
|
* The PRM is wrong, though. The width and height must be programmed to
|
|
|
|
* actual framebuffer's width and height, even when neither depth buffer
|
2016-03-05 17:13:44 +00:00
|
|
|
* nor stencil buffer is present. Also, D16_UNORM is not allowed to
|
|
|
|
* be combined with a stencil buffer so we use D32_FLOAT instead.
|
2016-02-15 07:01:42 +00:00
|
|
|
*/
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
|
|
|
|
.SurfaceType = SURFTYPE_2D,
|
2016-03-05 17:13:44 +00:00
|
|
|
.SurfaceFormat = D32_FLOAT,
|
2016-02-15 07:01:42 +00:00
|
|
|
.Width = fb->width - 1,
|
|
|
|
.Height = fb->height - 1,
|
|
|
|
.StencilWriteEnable = has_stencil);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Emit 3DSTATE_STENCIL_BUFFER */
|
|
|
|
if (has_stencil) {
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
|
2016-02-20 17:08:27 +00:00
|
|
|
#if GEN_GEN >= 8 || GEN_IS_HASWELL
|
2016-02-15 07:01:42 +00:00
|
|
|
.StencilBufferEnable = true,
|
|
|
|
#endif
|
|
|
|
.StencilBufferObjectControlState = GENX(MOCS),
|
|
|
|
|
|
|
|
/* Stencil buffers have strange pitch. The PRM says:
|
|
|
|
*
|
|
|
|
* The pitch must be set to 2x the value computed based on width,
|
|
|
|
* as the stencil buffer is stored with two rows interleaved.
|
|
|
|
*/
|
|
|
|
.SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
|
|
|
|
|
2016-02-20 17:08:27 +00:00
|
|
|
#if GEN_GEN >= 8
|
2016-02-15 07:01:42 +00:00
|
|
|
.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2,
|
|
|
|
#endif
|
|
|
|
.SurfaceBaseAddress = {
|
|
|
|
.bo = image->bo,
|
|
|
|
.offset = image->offset + image->stencil_surface.offset,
|
|
|
|
});
|
|
|
|
} else {
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable hierarchial depth buffers. */
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER));
|
|
|
|
|
|
|
|
/* Clear the clear params. */
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS));
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @see anv_cmd_buffer_set_subpass()
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
struct anv_subpass *subpass)
|
|
|
|
{
|
|
|
|
cmd_buffer->state.subpass = subpass;
|
|
|
|
|
|
|
|
cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
|
|
|
|
|
|
|
|
cmd_buffer_emit_depth_stencil(cmd_buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdBeginRenderPass)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
const VkRenderPassBeginInfo* pRenderPassBegin,
|
|
|
|
VkSubpassContents contents)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
|
|
|
|
ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
|
|
|
|
|
|
|
|
cmd_buffer->state.framebuffer = framebuffer;
|
|
|
|
cmd_buffer->state.pass = pass;
|
|
|
|
anv_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
|
|
|
|
|
|
|
|
genX(flush_pipeline_select_3d)(cmd_buffer);
|
|
|
|
|
|
|
|
const VkRect2D *render_area = &pRenderPassBegin->renderArea;
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DRAWING_RECTANGLE),
|
2016-03-04 00:21:09 +00:00
|
|
|
.ClippedDrawingRectangleYMin = MAX2(render_area->offset.y, 0),
|
|
|
|
.ClippedDrawingRectangleXMin = MAX2(render_area->offset.x, 0),
|
2016-02-15 07:01:42 +00:00
|
|
|
.ClippedDrawingRectangleYMax =
|
|
|
|
render_area->offset.y + render_area->extent.height - 1,
|
|
|
|
.ClippedDrawingRectangleXMax =
|
|
|
|
render_area->offset.x + render_area->extent.width - 1,
|
|
|
|
.DrawingRectangleOriginY = 0,
|
|
|
|
.DrawingRectangleOriginX = 0);
|
|
|
|
|
|
|
|
genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses);
|
|
|
|
anv_cmd_buffer_clear_subpass(cmd_buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdNextSubpass)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
VkSubpassContents contents)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
|
|
|
|
assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
|
|
|
|
|
|
|
|
anv_cmd_buffer_resolve_subpass(cmd_buffer);
|
|
|
|
genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
|
|
|
|
anv_cmd_buffer_clear_subpass(cmd_buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdEndRenderPass)(
|
|
|
|
VkCommandBuffer commandBuffer)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
|
|
|
|
anv_cmd_buffer_resolve_subpass(cmd_buffer);
|
|
|
|
}
|
2016-03-05 08:54:54 +00:00
|
|
|
|
|
|
|
static void
|
|
|
|
emit_ps_depth_count(struct anv_batch *batch,
|
|
|
|
struct anv_bo *bo, uint32_t offset)
|
|
|
|
{
|
|
|
|
anv_batch_emit(batch, GENX(PIPE_CONTROL),
|
|
|
|
.DestinationAddressType = DAT_PPGTT,
|
|
|
|
.PostSyncOperation = WritePSDepthCount,
|
|
|
|
.DepthStallEnable = true,
|
|
|
|
.Address = { bo, offset });
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_query_availability(struct anv_batch *batch,
|
|
|
|
struct anv_bo *bo, uint32_t offset)
|
|
|
|
{
|
|
|
|
anv_batch_emit(batch, GENX(PIPE_CONTROL),
|
|
|
|
.DestinationAddressType = DAT_PPGTT,
|
|
|
|
.PostSyncOperation = WriteImmediateData,
|
|
|
|
.Address = { bo, offset },
|
|
|
|
.ImmediateData = 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdBeginQuery)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
VkQueryPool queryPool,
|
|
|
|
uint32_t query,
|
|
|
|
VkQueryControlFlags flags)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
|
|
|
|
|
|
|
/* Workaround: When meta uses the pipeline with the VS disabled, it seems
|
|
|
|
* that the pipelining of the depth write breaks. What we see is that
|
|
|
|
* samples from the render pass clear leaks into the first query
|
|
|
|
* immediately after the clear. Doing a pipecontrol with a post-sync
|
|
|
|
* operation and DepthStallEnable seems to work around the issue.
|
|
|
|
*/
|
|
|
|
if (cmd_buffer->state.need_query_wa) {
|
|
|
|
cmd_buffer->state.need_query_wa = false;
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
|
|
|
|
.DepthCacheFlushEnable = true,
|
|
|
|
.DepthStallEnable = true);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (pool->type) {
|
|
|
|
case VK_QUERY_TYPE_OCCLUSION:
|
|
|
|
emit_ps_depth_count(&cmd_buffer->batch, &pool->bo,
|
|
|
|
query * sizeof(struct anv_query_pool_slot));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case VK_QUERY_TYPE_PIPELINE_STATISTICS:
|
|
|
|
default:
|
|
|
|
unreachable("");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdEndQuery)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
VkQueryPool queryPool,
|
|
|
|
uint32_t query)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
|
|
|
|
|
|
|
switch (pool->type) {
|
|
|
|
case VK_QUERY_TYPE_OCCLUSION:
|
|
|
|
emit_ps_depth_count(&cmd_buffer->batch, &pool->bo,
|
|
|
|
query * sizeof(struct anv_query_pool_slot) + 8);
|
|
|
|
|
|
|
|
emit_query_availability(&cmd_buffer->batch, &pool->bo,
|
|
|
|
query * sizeof(struct anv_query_pool_slot) + 16);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case VK_QUERY_TYPE_PIPELINE_STATISTICS:
|
|
|
|
default:
|
|
|
|
unreachable("");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#define TIMESTAMP 0x2358
|
|
|
|
|
|
|
|
void genX(CmdWriteTimestamp)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
VkPipelineStageFlagBits pipelineStage,
|
|
|
|
VkQueryPool queryPool,
|
|
|
|
uint32_t query)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
|
|
|
uint32_t offset = query * sizeof(struct anv_query_pool_slot);
|
|
|
|
|
|
|
|
assert(pool->type == VK_QUERY_TYPE_TIMESTAMP);
|
|
|
|
|
|
|
|
switch (pipelineStage) {
|
|
|
|
case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
|
|
|
|
.RegisterAddress = TIMESTAMP,
|
|
|
|
.MemoryAddress = { &pool->bo, offset });
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
|
|
|
|
.RegisterAddress = TIMESTAMP + 4,
|
|
|
|
.MemoryAddress = { &pool->bo, offset + 4 });
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
/* Everything else is bottom-of-pipe */
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
|
|
|
|
.DestinationAddressType = DAT_PPGTT,
|
|
|
|
.PostSyncOperation = WriteTimestamp,
|
|
|
|
.Address = { &pool->bo, offset });
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
emit_query_availability(&cmd_buffer->batch, &pool->bo, query + 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if GEN_GEN > 7 || GEN_IS_HASWELL
|
|
|
|
|
|
|
|
#define alu_opcode(v) __gen_uint((v), 20, 31)
|
|
|
|
#define alu_operand1(v) __gen_uint((v), 10, 19)
|
|
|
|
#define alu_operand2(v) __gen_uint((v), 0, 9)
|
|
|
|
#define alu(opcode, operand1, operand2) \
|
|
|
|
alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
|
|
|
|
|
|
|
|
#define OPCODE_NOOP 0x000
|
|
|
|
#define OPCODE_LOAD 0x080
|
|
|
|
#define OPCODE_LOADINV 0x480
|
|
|
|
#define OPCODE_LOAD0 0x081
|
|
|
|
#define OPCODE_LOAD1 0x481
|
|
|
|
#define OPCODE_ADD 0x100
|
|
|
|
#define OPCODE_SUB 0x101
|
|
|
|
#define OPCODE_AND 0x102
|
|
|
|
#define OPCODE_OR 0x103
|
|
|
|
#define OPCODE_XOR 0x104
|
|
|
|
#define OPCODE_STORE 0x180
|
|
|
|
#define OPCODE_STOREINV 0x580
|
|
|
|
|
|
|
|
#define OPERAND_R0 0x00
|
|
|
|
#define OPERAND_R1 0x01
|
|
|
|
#define OPERAND_R2 0x02
|
|
|
|
#define OPERAND_R3 0x03
|
|
|
|
#define OPERAND_R4 0x04
|
|
|
|
#define OPERAND_SRCA 0x20
|
|
|
|
#define OPERAND_SRCB 0x21
|
|
|
|
#define OPERAND_ACCU 0x31
|
|
|
|
#define OPERAND_ZF 0x32
|
|
|
|
#define OPERAND_CF 0x33
|
|
|
|
|
|
|
|
#define CS_GPR(n) (0x2600 + (n) * 8)
|
|
|
|
|
|
|
|
static void
|
|
|
|
emit_load_alu_reg_u64(struct anv_batch *batch, uint32_t reg,
|
|
|
|
struct anv_bo *bo, uint32_t offset)
|
|
|
|
{
|
|
|
|
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
|
|
|
|
.RegisterAddress = reg,
|
|
|
|
.MemoryAddress = { bo, offset });
|
|
|
|
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
|
|
|
|
.RegisterAddress = reg + 4,
|
|
|
|
.MemoryAddress = { bo, offset + 4 });
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
store_query_result(struct anv_batch *batch, uint32_t reg,
|
|
|
|
struct anv_bo *bo, uint32_t offset, VkQueryResultFlags flags)
|
|
|
|
{
|
|
|
|
anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM),
|
|
|
|
.RegisterAddress = reg,
|
|
|
|
.MemoryAddress = { bo, offset });
|
|
|
|
|
|
|
|
if (flags & VK_QUERY_RESULT_64_BIT)
|
|
|
|
anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM),
|
|
|
|
.RegisterAddress = reg + 4,
|
|
|
|
.MemoryAddress = { bo, offset + 4 });
|
|
|
|
}
|
|
|
|
|
|
|
|
void genX(CmdCopyQueryPoolResults)(
|
|
|
|
VkCommandBuffer commandBuffer,
|
|
|
|
VkQueryPool queryPool,
|
|
|
|
uint32_t firstQuery,
|
|
|
|
uint32_t queryCount,
|
|
|
|
VkBuffer destBuffer,
|
|
|
|
VkDeviceSize destOffset,
|
|
|
|
VkDeviceSize destStride,
|
|
|
|
VkQueryResultFlags flags)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
|
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
|
|
|
|
uint32_t slot_offset, dst_offset;
|
|
|
|
|
|
|
|
if (flags & VK_QUERY_RESULT_WAIT_BIT)
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
|
|
|
|
.CommandStreamerStallEnable = true,
|
|
|
|
.StallAtPixelScoreboard = true);
|
|
|
|
|
|
|
|
dst_offset = buffer->offset + destOffset;
|
|
|
|
for (uint32_t i = 0; i < queryCount; i++) {
|
|
|
|
|
|
|
|
slot_offset = (firstQuery + i) * sizeof(struct anv_query_pool_slot);
|
|
|
|
switch (pool->type) {
|
|
|
|
case VK_QUERY_TYPE_OCCLUSION:
|
|
|
|
emit_load_alu_reg_u64(&cmd_buffer->batch,
|
|
|
|
CS_GPR(0), &pool->bo, slot_offset);
|
|
|
|
emit_load_alu_reg_u64(&cmd_buffer->batch,
|
|
|
|
CS_GPR(1), &pool->bo, slot_offset + 8);
|
|
|
|
|
|
|
|
/* FIXME: We need to clamp the result for 32 bit. */
|
|
|
|
|
|
|
|
uint32_t *dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(MI_MATH));
|
|
|
|
dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R1);
|
|
|
|
dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
|
|
|
|
dw[3] = alu(OPCODE_SUB, 0, 0);
|
|
|
|
dw[4] = alu(OPCODE_STORE, OPERAND_R2, OPERAND_ACCU);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case VK_QUERY_TYPE_TIMESTAMP:
|
|
|
|
emit_load_alu_reg_u64(&cmd_buffer->batch,
|
|
|
|
CS_GPR(2), &pool->bo, slot_offset);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
unreachable("unhandled query type");
|
|
|
|
}
|
|
|
|
|
|
|
|
store_query_result(&cmd_buffer->batch,
|
|
|
|
CS_GPR(2), buffer->bo, dst_offset, flags);
|
|
|
|
|
|
|
|
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
|
|
|
|
emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0),
|
|
|
|
&pool->bo, slot_offset + 16);
|
|
|
|
if (flags & VK_QUERY_RESULT_64_BIT)
|
|
|
|
store_query_result(&cmd_buffer->batch,
|
|
|
|
CS_GPR(0), buffer->bo, dst_offset + 8, flags);
|
|
|
|
else
|
|
|
|
store_query_result(&cmd_buffer->batch,
|
|
|
|
CS_GPR(0), buffer->bo, dst_offset + 4, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
dst_offset += destStride;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|