2018-10-30 05:30:06 +00:00
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/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "tgsi/tgsi_from_mesa.h"
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#include "st_nir.h"
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2021-01-11 23:39:15 +00:00
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#include "st_program.h"
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2019-02-05 22:13:51 +00:00
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#include "compiler/nir/nir_builder.h"
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2020-06-15 14:14:58 +01:00
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#include "compiler/glsl/gl_nir.h"
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2022-01-04 01:51:56 +00:00
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#include "compiler/glsl/gl_nir_linker.h"
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2021-01-11 19:09:12 +00:00
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#include "tgsi/tgsi_parse.h"
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2018-10-30 05:30:06 +00:00
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struct pipe_shader_state *
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st_nir_finish_builtin_shader(struct st_context *st,
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2020-10-26 18:37:25 +00:00
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nir_shader *nir)
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2018-10-30 05:30:06 +00:00
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{
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2020-11-29 08:27:37 +00:00
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struct pipe_screen *screen = st->screen;
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2020-11-02 18:11:11 +00:00
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gl_shader_stage stage = nir->info.stage;
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2018-10-30 05:30:06 +00:00
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nir->info.separate_shader = true;
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2020-11-02 18:11:11 +00:00
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if (stage == MESA_SHADER_FRAGMENT)
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2018-10-30 05:30:06 +00:00
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nir->info.fs.untyped_color_outputs = true;
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NIR_PASS_V(nir, nir_lower_global_vars_to_local);
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NIR_PASS_V(nir, nir_split_var_copies);
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NIR_PASS_V(nir, nir_lower_var_copies);
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NIR_PASS_V(nir, nir_lower_system_values);
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2020-08-21 18:40:45 +01:00
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NIR_PASS_V(nir, nir_lower_compute_system_values, NULL);
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2018-10-30 05:30:06 +00:00
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2019-10-08 03:47:23 +01:00
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if (nir->options->lower_to_scalar) {
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2018-10-30 05:30:06 +00:00
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nir_variable_mode mask =
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2020-11-02 18:11:11 +00:00
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(stage > MESA_SHADER_VERTEX ? nir_var_shader_in : 0) |
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(stage < MESA_SHADER_FRAGMENT ? nir_var_shader_out : 0);
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2018-10-30 05:30:06 +00:00
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NIR_PASS_V(nir, nir_lower_io_to_scalar_early, mask);
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}
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2021-02-01 10:48:02 +00:00
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if (st->lower_rect_tex) {
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const struct nir_lower_tex_options opts = { .lower_rect = true, };
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NIR_PASS_V(nir, nir_lower_tex, &opts);
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}
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2018-10-30 05:30:06 +00:00
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nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
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2019-10-18 18:02:15 +01:00
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st_nir_assign_vs_in_locations(nir);
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2018-10-30 05:30:06 +00:00
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st_nir_assign_varying_locations(st, nir);
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nir: Gather texture bitmasks in gl_nir_lower_samplers_as_deref.
Eric and I would like a bitmask of which samplers are used, similar to
prog->SamplersUsed, but available in NIR. The linker uses SamplersUsed
for resource limit checking, but later optimizations may eliminate more
samplers. So instead of propagating it through, we gather a new one.
While there, we also gather the existing textures_used_by_txf bitmask.
Gathering these bitfields in nir_shader_gather_info is awkward at best.
The main reason is that it introduces an ordering dependency between the
two passes. If gathering runs before lower_samplers_as_deref, it can't
look at var->data.binding. If the driver doesn't use the full lowering
to texture_index/texture_array_size (like radeonsi), then the gathering
can't use those fields. Gathering might be run early /and/ late, first
to get varying info, and later to update it after variant lowering. At
this point, should gathering work on pre-lowered or post-lowered code?
Pre-lowered is also harder due to the presence of structure types.
Just doing the gathering when we do the lowering alleviates these
ordering problems. This fixes ordering issues in i965 and makes the
txf info gathering work for radeonsi (though they don't use it).
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-01-13 18:39:41 +00:00
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st_nir_lower_samplers(screen, nir, NULL, NULL);
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2020-01-06 19:47:03 +00:00
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st_nir_lower_uniforms(st, nir);
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2020-06-15 14:14:58 +01:00
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if (!screen->get_param(screen, PIPE_CAP_NIR_IMAGES_AS_DEREF))
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NIR_PASS_V(nir, gl_nir_lower_images, false);
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2018-10-30 05:30:06 +00:00
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2021-08-03 18:20:18 +01:00
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if (screen->finalize_nir) {
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char *msg = screen->finalize_nir(screen, nir);
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free(msg);
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} else {
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2022-01-04 01:51:56 +00:00
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gl_nir_opts(nir);
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2021-08-03 18:20:18 +01:00
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}
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2019-09-27 23:09:11 +01:00
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2018-10-30 05:30:06 +00:00
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struct pipe_shader_state state = {
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.type = PIPE_SHADER_IR_NIR,
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.ir.nir = nir,
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};
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2021-01-11 23:39:15 +00:00
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return st_create_nir_shader(st, &state);
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2018-10-30 05:30:06 +00:00
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}
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/**
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* Make a simple shader that copies inputs to corresponding outputs.
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*/
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struct pipe_shader_state *
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st_nir_make_passthrough_shader(struct st_context *st,
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const char *shader_name,
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gl_shader_stage stage,
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unsigned num_vars,
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unsigned *input_locations,
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unsigned *output_locations,
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unsigned *interpolation_modes,
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unsigned sysval_mask)
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{
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const struct glsl_type *vec4 = glsl_vec4_type();
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const nir_shader_compiler_options *options =
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2020-08-26 20:42:36 +01:00
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st_get_nir_compiler_options(st, stage);
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2018-10-30 05:30:06 +00:00
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2020-10-26 18:37:25 +00:00
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nir_builder b = nir_builder_init_simple_shader(stage, options,
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"%s", shader_name);
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2018-10-30 05:30:06 +00:00
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char var_name[15];
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for (unsigned i = 0; i < num_vars; i++) {
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nir_variable *in;
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if (sysval_mask & (1 << i)) {
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snprintf(var_name, sizeof(var_name), "sys_%u", input_locations[i]);
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in = nir_variable_create(b.shader, nir_var_system_value,
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glsl_int_type(), var_name);
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} else {
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snprintf(var_name, sizeof(var_name), "in_%u", input_locations[i]);
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in = nir_variable_create(b.shader, nir_var_shader_in, vec4, var_name);
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}
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in->data.location = input_locations[i];
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if (interpolation_modes)
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in->data.interpolation = interpolation_modes[i];
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snprintf(var_name, sizeof(var_name), "out_%u", output_locations[i]);
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nir_variable *out =
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nir_variable_create(b.shader, nir_var_shader_out, in->type, var_name);
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out->data.location = output_locations[i];
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out->data.interpolation = in->data.interpolation;
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nir_copy_var(&b, out, in);
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}
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2020-10-26 18:37:25 +00:00
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return st_nir_finish_builtin_shader(st, b.shader);
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2018-10-30 05:30:06 +00:00
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}
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2022-05-13 12:33:20 +01:00
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/**
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* Make a simple shader that reads color value from a constant buffer
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* and uses it to clear all color buffers.
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*/
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struct pipe_shader_state *
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st_nir_make_clearcolor_shader(struct st_context *st)
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{
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const nir_shader_compiler_options *options =
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st_get_nir_compiler_options(st, MESA_SHADER_FRAGMENT);
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nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, options,
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"clear color FS");
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b.shader->info.num_ubos = 1;
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b.shader->num_outputs = 1;
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b.shader->num_uniforms = 1;
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/* Read clear color from constant buffer */
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nir_ssa_def *clear_color = nir_load_uniform(&b, 4, 32, nir_imm_int(&b,0),
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.range = 16,
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.dest_type = nir_type_float32);
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nir_variable *color_out =
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nir_variable_create(b.shader, nir_var_shader_out, glsl_vec_type(4),
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"outcolor");
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color_out->data.location = FRAG_RESULT_COLOR;
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/* Write out the color */
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nir_store_var(&b, color_out, clear_color, 0xf);
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return st_nir_finish_builtin_shader(st, b.shader);
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}
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