vkd3d-shader: Implement DADD, DMUL, DDIV, DMAX, DMIN, DFMA and DMOV
Signed-off-by: Joshua Ashton <joshua@froggi.es>
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@ -1278,6 +1278,14 @@ static const struct vkd3d_sm4_opcode_info opcode_table[] =
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{VKD3D_SM5_OP_SAMPLE_D_CLAMP_FEEDBACK, VKD3DSIH_SAMPLE_GRAD_FEEDBACK, "fu", "fRSfff"},
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{VKD3D_SM5_OP_SAMPLE_C_CLAMP_FEEDBACK, VKD3DSIH_SAMPLE_C_FEEDBACK, "fu", "fRSff"},
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{VKD3D_SM5_OP_CHECK_ACCESS_FULLY_MAPPED, VKD3DSIH_CHECK_ACCESS_FULLY_MAPPED, "u", "u"},
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{VKD3D_SM5_OP_DADD, VKD3DSIH_DADD, "d", "dd"},
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{VKD3D_SM5_OP_DMAX, VKD3DSIH_DMAX, "d", "dd"},
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{VKD3D_SM5_OP_DMIN, VKD3DSIH_DMIN, "d", "dd"},
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{VKD3D_SM5_OP_DMUL, VKD3DSIH_DMUL, "d", "dd"},
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{VKD3D_SM5_OP_DMOV, VKD3DSIH_DMOV, "d", "d"},
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{VKD3D_SM5_OP_DDIV, VKD3DSIH_DDIV, "d", "dd"},
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{VKD3D_SM5_OP_DFMA, VKD3DSIH_DFMA, "d", "ddd"},
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};
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static const enum vkd3d_shader_register_type register_type_table[] =
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@ -6674,10 +6674,12 @@ static SpvOp vkd3d_dxbc_compiler_map_alu_instruction(const struct vkd3d_shader_i
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}
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alu_ops[] =
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{
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{VKD3DSIH_DADD, SpvOpFAdd},
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{VKD3DSIH_ADD, SpvOpFAdd},
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{VKD3DSIH_AND, SpvOpBitwiseAnd},
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{VKD3DSIH_BFREV, SpvOpBitReverse},
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{VKD3DSIH_COUNTBITS, SpvOpBitCount},
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{VKD3DSIH_DDIV, SpvOpFDiv},
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{VKD3DSIH_DIV, SpvOpFDiv},
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{VKD3DSIH_FTOI, SpvOpConvertFToS},
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{VKD3DSIH_FTOU, SpvOpConvertFToU},
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@ -6686,6 +6688,7 @@ static SpvOp vkd3d_dxbc_compiler_map_alu_instruction(const struct vkd3d_shader_i
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{VKD3DSIH_ISHL, SpvOpShiftLeftLogical},
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{VKD3DSIH_ISHR, SpvOpShiftRightArithmetic},
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{VKD3DSIH_ITOF, SpvOpConvertSToF},
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{VKD3DSIH_DMUL, SpvOpFMul},
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{VKD3DSIH_MUL, SpvOpFMul},
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{VKD3DSIH_NOT, SpvOpNot},
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{VKD3DSIH_OR, SpvOpBitwiseOr},
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@ -6754,8 +6757,11 @@ static enum GLSLstd450 vkd3d_dxbc_compiler_map_ext_glsl_instruction(
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{VKD3DSIH_IMAX, GLSLstd450SMax},
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{VKD3DSIH_IMIN, GLSLstd450SMin},
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{VKD3DSIH_LOG, GLSLstd450Log2},
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{VKD3DSIH_DFMA, GLSLstd450Fma},
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{VKD3DSIH_MAD, GLSLstd450Fma},
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{VKD3DSIH_DMAX, GLSLstd450NMax},
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{VKD3DSIH_MAX, GLSLstd450NMax},
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{VKD3DSIH_DMIN, GLSLstd450NMin},
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{VKD3DSIH_MIN, GLSLstd450NMin},
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{VKD3DSIH_ROUND_NE, GLSLstd450RoundEven},
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{VKD3DSIH_ROUND_NI, GLSLstd450Floor},
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@ -9456,6 +9462,7 @@ int vkd3d_dxbc_compiler_handle_instruction(struct vkd3d_dxbc_compiler *compiler,
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case VKD3DSIH_HS_JOIN_PHASE:
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vkd3d_dxbc_compiler_enter_shader_phase(compiler, instruction);
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break;
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case VKD3DSIH_DMOV:
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case VKD3DSIH_MOV:
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vkd3d_dxbc_compiler_emit_mov(compiler, instruction);
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break;
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@ -9465,10 +9472,12 @@ int vkd3d_dxbc_compiler_handle_instruction(struct vkd3d_dxbc_compiler *compiler,
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case VKD3DSIH_SWAPC:
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vkd3d_dxbc_compiler_emit_swapc(compiler, instruction);
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break;
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case VKD3DSIH_DADD:
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case VKD3DSIH_ADD:
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case VKD3DSIH_AND:
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case VKD3DSIH_BFREV:
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case VKD3DSIH_COUNTBITS:
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case VKD3DSIH_DDIV:
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case VKD3DSIH_DIV:
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case VKD3DSIH_FTOI:
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case VKD3DSIH_FTOU:
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@ -9477,6 +9486,7 @@ int vkd3d_dxbc_compiler_handle_instruction(struct vkd3d_dxbc_compiler *compiler,
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case VKD3DSIH_ISHL:
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case VKD3DSIH_ISHR:
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case VKD3DSIH_ITOF:
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case VKD3DSIH_DMUL:
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case VKD3DSIH_MUL:
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case VKD3DSIH_NOT:
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case VKD3DSIH_OR:
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@ -9493,8 +9503,11 @@ int vkd3d_dxbc_compiler_handle_instruction(struct vkd3d_dxbc_compiler *compiler,
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case VKD3DSIH_IMAX:
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case VKD3DSIH_IMIN:
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case VKD3DSIH_LOG:
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case VKD3DSIH_DFMA:
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case VKD3DSIH_MAD:
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case VKD3DSIH_DMAX:
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case VKD3DSIH_MAX:
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case VKD3DSIH_DMIN:
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case VKD3DSIH_MIN:
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case VKD3DSIH_ROUND_NE:
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case VKD3DSIH_ROUND_NI:
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@ -276,6 +276,14 @@ enum VKD3D_SHADER_INSTRUCTION_HANDLER
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VKD3DSIH_UTOF,
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VKD3DSIH_XOR,
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VKD3DSIH_DADD,
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VKD3DSIH_DMAX,
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VKD3DSIH_DMIN,
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VKD3DSIH_DMUL,
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VKD3DSIH_DMOV,
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VKD3DSIH_DDIV,
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VKD3DSIH_DFMA,
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VKD3DSIH_INVALID,
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};
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