vkd3d-shader: Implement 64-bit immediate constants
Signed-off-by: Joshua Ashton <joshua@froggi.es>
This commit is contained in:
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ab03abe419
commit
837ef2edc6
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@ -363,6 +363,7 @@ enum vkd3d_sm4_register_type
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VKD3D_SM4_RT_OUTPUT = 0x02,
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VKD3D_SM4_RT_OUTPUT = 0x02,
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VKD3D_SM4_RT_INDEXABLE_TEMP = 0x03,
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VKD3D_SM4_RT_INDEXABLE_TEMP = 0x03,
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VKD3D_SM4_RT_IMMCONST = 0x04,
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VKD3D_SM4_RT_IMMCONST = 0x04,
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VKD3D_SM4_RT_IMMCONST64 = 0x05,
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VKD3D_SM4_RT_SAMPLER = 0x06,
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VKD3D_SM4_RT_SAMPLER = 0x06,
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VKD3D_SM4_RT_RESOURCE = 0x07,
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VKD3D_SM4_RT_RESOURCE = 0x07,
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VKD3D_SM4_RT_CONSTBUFFER = 0x08,
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VKD3D_SM4_RT_CONSTBUFFER = 0x08,
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@ -454,6 +455,7 @@ enum vkd3d_sm4_immconst_type
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{
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{
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VKD3D_SM4_IMMCONST_SCALAR = 0x1,
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VKD3D_SM4_IMMCONST_SCALAR = 0x1,
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VKD3D_SM4_IMMCONST_VEC4 = 0x2,
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VKD3D_SM4_IMMCONST_VEC4 = 0x2,
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VKD3D_SM4_IMMCONST_DVEC2 = VKD3D_SM4_IMMCONST_VEC4,
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};
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};
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enum vkd3d_sm4_resource_type
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enum vkd3d_sm4_resource_type
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@ -1307,7 +1309,7 @@ static const enum vkd3d_shader_register_type register_type_table[] =
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/* VKD3D_SM4_RT_OUTPUT */ VKD3DSPR_OUTPUT,
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/* VKD3D_SM4_RT_OUTPUT */ VKD3DSPR_OUTPUT,
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/* VKD3D_SM4_RT_INDEXABLE_TEMP */ VKD3DSPR_IDXTEMP,
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/* VKD3D_SM4_RT_INDEXABLE_TEMP */ VKD3DSPR_IDXTEMP,
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/* VKD3D_SM4_RT_IMMCONST */ VKD3DSPR_IMMCONST,
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/* VKD3D_SM4_RT_IMMCONST */ VKD3DSPR_IMMCONST,
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/* UNKNOWN */ ~0u,
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/* VKD3D_SM4_RT_IMMCONST64 */ VKD3DSPR_IMMCONST64,
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/* VKD3D_SM4_RT_SAMPLER */ VKD3DSPR_SAMPLER,
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/* VKD3D_SM4_RT_SAMPLER */ VKD3DSPR_SAMPLER,
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/* VKD3D_SM4_RT_RESOURCE */ VKD3DSPR_RESOURCE,
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/* VKD3D_SM4_RT_RESOURCE */ VKD3DSPR_RESOURCE,
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/* VKD3D_SM4_RT_CONSTBUFFER */ VKD3DSPR_CONSTBUFFER,
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/* VKD3D_SM4_RT_CONSTBUFFER */ VKD3DSPR_CONSTBUFFER,
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@ -1710,6 +1712,40 @@ static bool shader_sm4_read_param(struct vkd3d_sm4_data *priv, const DWORD **ptr
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break;
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break;
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}
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}
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}
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}
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else if (register_type == VKD3D_SM4_RT_IMMCONST64)
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{
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enum vkd3d_sm4_immconst_type immconst_type =
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(token & VKD3D_SM4_IMMCONST_TYPE_MASK) >> VKD3D_SM4_IMMCONST_TYPE_SHIFT;
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switch (immconst_type)
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{
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case VKD3D_SM4_IMMCONST_SCALAR:
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param->immconst_type = VKD3D_IMMCONST_SCALAR;
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if (end - *ptr < VKD3D_DOUBLE_DWORD_SIZE)
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{
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WARN("Invalid ptr %p, end %p.\n", *ptr, end);
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return false;
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}
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memcpy(param->immconst_uint64, *ptr, VKD3D_DOUBLE_DWORD_SIZE * sizeof(DWORD));
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*ptr += VKD3D_DOUBLE_DWORD_SIZE;
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break;
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case VKD3D_SM4_IMMCONST_DVEC2:
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param->immconst_type = VKD3D_IMMCONST_VEC4;
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if (end - *ptr < VKD3D_DVEC2_DWORD_SIZE)
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{
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WARN("Invalid ptr %p, end %p.\n", *ptr, end);
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return false;
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}
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memcpy(param->immconst_uint64, *ptr, VKD3D_DVEC2_DWORD_SIZE * sizeof(DWORD));
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*ptr += VKD3D_DVEC2_DWORD_SIZE;
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break;
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default:
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FIXME("Unhandled immediate constant type %#x.\n", immconst_type);
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break;
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}
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}
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map_register(priv, param);
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map_register(priv, param);
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@ -2921,7 +2921,7 @@ static bool vkd3d_dxbc_compiler_find_register_info(const struct vkd3d_dxbc_compi
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struct vkd3d_symbol reg_symbol, *symbol;
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struct vkd3d_symbol reg_symbol, *symbol;
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struct rb_entry *entry;
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struct rb_entry *entry;
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assert(reg->type != VKD3DSPR_IMMCONST);
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assert(reg->type != VKD3DSPR_IMMCONST && reg->type != VKD3DSPR_IMMCONST64);
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if (reg->type == VKD3DSPR_TEMP)
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if (reg->type == VKD3DSPR_TEMP)
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{
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{
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@ -3161,6 +3161,33 @@ static uint32_t vkd3d_dxbc_compiler_emit_load_constant(struct vkd3d_dxbc_compile
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vkd3d_component_type_from_data_type(reg->data_type), component_count, values);
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vkd3d_component_type_from_data_type(reg->data_type), component_count, values);
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}
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}
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static uint32_t vkd3d_dxbc_compiler_emit_load_constant64(struct vkd3d_dxbc_compiler *compiler,
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const struct vkd3d_shader_register *reg, DWORD swizzle, DWORD write_mask)
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{
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unsigned int component_count = vkd3d_write_mask_component_count_typed(write_mask, VKD3D_TYPE_DOUBLE);
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uint64_t values[2] = {0};
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unsigned int i, j;
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assert(reg->type == VKD3DSPR_IMMCONST64);
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if (reg->immconst_type == VKD3D_IMMCONST_SCALAR)
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{
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for (i = 0; i < component_count; ++i)
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values[i] = reg->immconst_uint64[0];
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}
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else
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{
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for (i = 0, j = 0; i < VKD3D_DVEC2_SIZE; ++i)
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{
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if (write_mask & (VKD3DSP_WRITEMASK_0 << (i * 2)))
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values[j++] = reg->immconst_uint64[vkd3d_swizzle_get_component(swizzle, i * 2) / 2];
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}
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}
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return vkd3d_dxbc_compiler_get_constant(compiler,
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vkd3d_component_type_from_data_type(reg->data_type), component_count, (const uint32_t*)values);
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}
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static uint32_t vkd3d_dxbc_compiler_emit_load_scalar(struct vkd3d_dxbc_compiler *compiler,
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static uint32_t vkd3d_dxbc_compiler_emit_load_scalar(struct vkd3d_dxbc_compiler *compiler,
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const struct vkd3d_shader_register *reg, DWORD swizzle, DWORD write_mask,
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const struct vkd3d_shader_register *reg, DWORD swizzle, DWORD write_mask,
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const struct vkd3d_shader_register_info *reg_info)
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const struct vkd3d_shader_register_info *reg_info)
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@ -3171,7 +3198,7 @@ static uint32_t vkd3d_dxbc_compiler_emit_load_scalar(struct vkd3d_dxbc_compiler
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enum vkd3d_component_type component_type;
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enum vkd3d_component_type component_type;
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unsigned int skipped_component_mask;
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unsigned int skipped_component_mask;
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assert(reg->type != VKD3DSPR_IMMCONST);
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assert(reg->type != VKD3DSPR_IMMCONST && reg->type != VKD3DSPR_IMMCONST64);
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assert(vkd3d_write_mask_component_count(write_mask) == 1);
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assert(vkd3d_write_mask_component_count(write_mask) == 1);
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component_idx = vkd3d_write_mask_get_component_idx(write_mask);
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component_idx = vkd3d_write_mask_get_component_idx(write_mask);
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@ -3301,6 +3328,8 @@ static uint32_t vkd3d_dxbc_compiler_emit_load_reg(struct vkd3d_dxbc_compiler *co
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if (reg->type == VKD3DSPR_IMMCONST)
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if (reg->type == VKD3DSPR_IMMCONST)
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return vkd3d_dxbc_compiler_emit_load_constant(compiler, reg, swizzle, write_mask);
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return vkd3d_dxbc_compiler_emit_load_constant(compiler, reg, swizzle, write_mask);
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else if (reg->type == VKD3DSPR_IMMCONST64)
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return vkd3d_dxbc_compiler_emit_load_constant64(compiler, reg, swizzle, write_mask);
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component_count = vkd3d_write_mask_component_count(write_mask);
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component_count = vkd3d_write_mask_component_count(write_mask);
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component_type = vkd3d_component_type_from_data_type(reg->data_type);
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component_type = vkd3d_component_type_from_data_type(reg->data_type);
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@ -3509,7 +3538,7 @@ static void vkd3d_dxbc_compiler_emit_store_reg(struct vkd3d_dxbc_compiler *compi
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enum vkd3d_component_type component_type;
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enum vkd3d_component_type component_type;
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uint32_t type_id;
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uint32_t type_id;
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assert(reg->type != VKD3DSPR_IMMCONST);
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assert(reg->type != VKD3DSPR_IMMCONST && reg->type != VKD3DSPR_IMMCONST64);
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if (!vkd3d_dxbc_compiler_get_register_info(compiler, reg, ®_info))
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if (!vkd3d_dxbc_compiler_get_register_info(compiler, reg, ®_info))
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return;
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return;
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@ -667,6 +667,10 @@ static void shader_dump_register(struct vkd3d_string_buffer *buffer,
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shader_addline(buffer, "l");
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shader_addline(buffer, "l");
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break;
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break;
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case VKD3DSPR_IMMCONST64:
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shader_addline(buffer, "d");
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break;
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case VKD3DSPR_CONSTBUFFER:
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case VKD3DSPR_CONSTBUFFER:
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shader_addline(buffer, "cb");
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shader_addline(buffer, "cb");
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break;
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break;
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@ -833,6 +837,42 @@ static void shader_dump_register(struct vkd3d_string_buffer *buffer,
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}
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}
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shader_addline(buffer, ")");
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shader_addline(buffer, ")");
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}
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}
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else if (reg->type == VKD3DSPR_IMMCONST64)
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{
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shader_addline(buffer, "(");
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switch (reg->immconst_type)
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{
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case VKD3D_IMMCONST_SCALAR:
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switch (reg->data_type)
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{
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case VKD3D_DATA_DOUBLE:
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shader_addline(buffer, "%f", reg->immconst_double[0]);
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break;
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default:
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shader_addline(buffer, "<unhandled data type %#x>", reg->data_type);
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break;
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}
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break;
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case VKD3D_IMMCONST_DVEC2:
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switch (reg->data_type)
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{
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case VKD3D_DATA_DOUBLE:
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shader_addline(buffer, "%f, %f",
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reg->immconst_double[0], reg->immconst_double[1]);
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break;
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default:
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shader_addline(buffer, "<unhandled data type %#x>", reg->data_type);
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break;
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}
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break;
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default:
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shader_addline(buffer, "<unhandled immconst_type %#x>", reg->immconst_type);
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break;
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}
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shader_addline(buffer, ")");
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}
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else if (reg->type != VKD3DSPR_NULL)
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else if (reg->type != VKD3DSPR_NULL)
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{
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{
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if (offset != ~0u)
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if (offset != ~0u)
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@ -58,6 +58,10 @@
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#define VKD3D_VEC4_SIZE 4
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#define VKD3D_VEC4_SIZE 4
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#define VKD3D_DVEC2_SIZE 2
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#define VKD3D_DOUBLE_DWORD_SIZE 2
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#define VKD3D_DVEC2_DWORD_SIZE (VKD3D_DOUBLE_DWORD_SIZE * VKD3D_DVEC2_SIZE)
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enum VKD3D_SHADER_INSTRUCTION_HANDLER
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enum VKD3D_SHADER_INSTRUCTION_HANDLER
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{
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{
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VKD3DSIH_ADD,
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VKD3DSIH_ADD,
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@ -308,6 +312,7 @@ enum vkd3d_shader_register_type
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VKD3DSPR_DEPTHOUT,
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VKD3DSPR_DEPTHOUT,
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VKD3DSPR_SAMPLER,
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VKD3DSPR_SAMPLER,
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VKD3DSPR_IMMCONST,
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VKD3DSPR_IMMCONST,
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VKD3DSPR_IMMCONST64,
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VKD3DSPR_CONSTBUFFER,
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VKD3DSPR_CONSTBUFFER,
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VKD3DSPR_IMMCONSTBUFFER,
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VKD3DSPR_IMMCONSTBUFFER,
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VKD3DSPR_PRIMID,
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VKD3DSPR_PRIMID,
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@ -374,6 +379,7 @@ enum vkd3d_immconst_type
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{
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{
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VKD3D_IMMCONST_SCALAR,
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VKD3D_IMMCONST_SCALAR,
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VKD3D_IMMCONST_VEC4,
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VKD3D_IMMCONST_VEC4,
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VKD3D_IMMCONST_DVEC2 = VKD3D_IMMCONST_VEC4,
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};
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};
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enum vkd3d_shader_register_modifier
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enum vkd3d_shader_register_modifier
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@ -535,6 +541,8 @@ struct vkd3d_shader_register
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{
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{
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uint32_t immconst_uint[VKD3D_VEC4_SIZE];
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uint32_t immconst_uint[VKD3D_VEC4_SIZE];
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float immconst_float[VKD3D_VEC4_SIZE];
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float immconst_float[VKD3D_VEC4_SIZE];
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double immconst_double[VKD3D_DVEC2_SIZE];
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uint64_t immconst_uint64[VKD3D_DVEC2_SIZE];
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unsigned fp_body_idx;
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unsigned fp_body_idx;
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};
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};
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};
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};
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