From c7d0d328d569c15c01c5830af838faac8a8b3c62 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Mon, 22 Aug 2022 22:36:49 -0500 Subject: [PATCH] radv: Set the window scissor to the render area, not framebuffer With dynamic rendering, the concept of framebuffer dimensions goes away so this won't make sense. Even with render passes, the render area is guaranteed to be inside the framebuffer so we may as well clip to the potentially smaller render area. This commit also moves window scissor setup to CmdBeginRenderPass2() time. This should be fine, even for meta ops, as the only meta ops which happen inside a render pass need the same render area as the render pass itself. Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index db1086978ba47..d18df39cb2160 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2642,7 +2642,6 @@ static void radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) { int i; - struct vk_framebuffer *framebuffer = cmd_buffer->state.framebuffer; const struct radv_subpass *subpass = cmd_buffer->state.subpass; bool disable_constant_encode_ac01 = false; unsigned color_invalid = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11 @@ -2762,8 +2761,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) S_028040_NUM_SAMPLES(num_samples)); radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */ } - radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, - S_028208_BR_X(framebuffer->width) | S_028208_BR_Y(framebuffer->height)); if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX8) { bool disable_constant_encode = @@ -6232,6 +6229,15 @@ radv_CmdBeginRenderPass2(VkCommandBuffer commandBuffer, if (result != VK_SUCCESS) return; + radeon_set_context_reg(cmd_buffer->cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, + S_028204_TL_X(cmd_buffer->state.render_area.offset.x) | + S_028204_TL_Y(cmd_buffer->state.render_area.offset.y)); + radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, + S_028208_BR_X(cmd_buffer->state.render_area.offset.x + + cmd_buffer->state.render_area.extent.width) | + S_028208_BR_Y(cmd_buffer->state.render_area.offset.y + + cmd_buffer->state.render_area.extent.height)); + radv_cmd_buffer_begin_subpass(cmd_buffer, 0); }