gpu_id: 201
cmd: deqp-gles2/185: fence=1250
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122d000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122d008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122d014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122d020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122d02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122d034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122d040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122d050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122d05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122d068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122d078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122d084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122d090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122d09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122d0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122d0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122d0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122d0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122d0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122d100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122d11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122d12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122d15c:			2.000000 0.750000 0.375000 0.250000
0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122d190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
0122d19c:		0000: c0012d00 00040000 00000040
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 }
0122d1a8:		0000: c0012d00 00040001 0110d009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
0122d1b4:		0000: c0022d00 0004000e 80000000 00800040
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 9
			:0,0,9,0
0122d1d0:		0000: 0000057e 00000009
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d003 00100000 0112d003 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
0122e088:			0000: c0022d00 00040081 00000000 00800040
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 32.000000
				PA_CL_VPORT_XOFFSET: 32.000000
				PA_CL_VPORT_YSCALE: 64.000000
				PA_CL_VPORT_YOFFSET: 64.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=0111d000 (flags=820), size=64x128, pitch=64, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 00824800 0111d820 000fe03f 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 5
				:0,0,9,5
0122e24c:			0000: 0000057f 00000005
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[0] register values
!+	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
!+	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000009			CP_SCRATCH_REG6: 9
			:0,0,9,5
!+	00000005			CP_SCRATCH_REG7: 5
			:0,0,9,5
!+	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
!+	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
!+	00000002			TP0_CHICKEN: 0x2
!+	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000040			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
!+	0110d009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x110d000 }
!+	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00800040			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00800040			PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
!+	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
!+	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	42000000			PA_CL_VPORT_XSCALE: 32.000000
!+	42000000			PA_CL_VPORT_XOFFSET: 32.000000
!+	42800000			PA_CL_VPORT_YSCALE: 64.000000
!+	42800000			PA_CL_VPORT_YOFFSET: 64.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
!+	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
!+	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
!+	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
!+	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
!+	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
!+	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
!+	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
!+	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
!+	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
!+	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
!+	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
!+	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
!+	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
!+	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
!+	0000ffff			PA_SC_AA_MASK: 0xffff
!+	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
!+	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
!+	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
!+	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 6
				:0,0,9,6
0122e268:			0000: 0000057f 00000006
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122d1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1251
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122f000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122f008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122f014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122f020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122f02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122f034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122f040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122f050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122f05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122f068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122f078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122f084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122f090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122f09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122f0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122f0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122f0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122f0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122f0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122f100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122f11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122f12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122f15c:			2.000000 0.750000 0.375000 0.250000
0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122f190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122f19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 }
0122f1a8:		0000: c0012d00 00040001 01240009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
0122f1b4:		0000: c0022d00 0004000e 80000000 00400020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 15
			:0,0,15,6
0122f1d0:		0000: 0000057e 0000000f
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d083 00100000 0112d083 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
0122e088:			0000: c0022d00 00040081 00000000 00400020
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 16.000000
				PA_CL_VPORT_XOFFSET: 16.000000
				PA_CL_VPORT_YSCALE: 32.000000
				PA_CL_VPORT_YOFFSET: 32.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=01250000 (flags=820), size=32x64, pitch=32, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 00424800 01250820 0007e01f 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 11
				:0,0,15,11
0122e24c:			0000: 0000057f 0000000b
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[1] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	0000000f			CP_SCRATCH_REG6: 15
			:0,0,15,11
!+	0000000b			CP_SCRATCH_REG7: 11
			:0,0,15,11
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	01240009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1240000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00400020			PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00400020			PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	41800000			PA_CL_VPORT_XSCALE: 16.000000
!+	41800000			PA_CL_VPORT_XOFFSET: 16.000000
!+	42000000			PA_CL_VPORT_YSCALE: 32.000000
!+	42000000			PA_CL_VPORT_YOFFSET: 32.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 12
				:0,0,15,12
0122e268:			0000: 0000057f 0000000c
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122f1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1252
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122d000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122d008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122d014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122d020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122d02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122d034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122d040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122d050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122d05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122d068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122d078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122d084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122d090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122d09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122d0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122d0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122d0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122d0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122d0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122d100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122d11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122d12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122d15c:			2.000000 0.750000 0.375000 0.250000
0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122d190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122d19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 }
0122d1a8:		0000: c0012d00 00040001 01244009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
0122d1b4:		0000: c0022d00 0004000e 80000000 00200010
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 21
			:0,0,21,12
0122d1d0:		0000: 0000057e 00000015
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d103 00100000 0112d103 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
0122e088:			0000: c0022d00 00040081 00000000 00200010
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 8.000000
				PA_CL_VPORT_XOFFSET: 8.000000
				PA_CL_VPORT_YSCALE: 16.000000
				PA_CL_VPORT_YOFFSET: 16.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=01254000 (flags=820), size=16x32, pitch=32, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 00424800 01254820 0003e00f 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 17
				:0,0,21,17
0122e24c:			0000: 0000057f 00000011
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[2] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000015			CP_SCRATCH_REG6: 21
			:0,0,21,17
!+	00000011			CP_SCRATCH_REG7: 17
			:0,0,21,17
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 +	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	01244009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1244000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00200010			PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00200010			PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	41000000			PA_CL_VPORT_XSCALE: 8.000000
!+	41000000			PA_CL_VPORT_XOFFSET: 8.000000
!+	41800000			PA_CL_VPORT_YSCALE: 16.000000
!+	41800000			PA_CL_VPORT_YOFFSET: 16.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 18
				:0,0,21,18
0122e268:			0000: 0000057f 00000012
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122d1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1253
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122f000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122f008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122f014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122f020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122f02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122f034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122f040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122f050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122f05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122f068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122f078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122f084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122f090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122f09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122f0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122f0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122f0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122f0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122f0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122f100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122f11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122f12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122f15c:			2.000000 0.750000 0.375000 0.250000
0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122f190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122f19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 }
0122f1a8:		0000: c0012d00 00040001 01246009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
0122f1b4:		0000: c0022d00 0004000e 80000000 00100008
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 27
			:0,0,27,18
0122f1d0:		0000: 0000057e 0000001b
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d183 00100000 0112d183 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
0122e088:			0000: c0022d00 00040081 00000000 00100008
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 4.000000
				PA_CL_VPORT_XOFFSET: 4.000000
				PA_CL_VPORT_YSCALE: 8.000000
				PA_CL_VPORT_YOFFSET: 8.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=01254000 (flags=820), size=8x16, pitch=32, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 00424800 01254820 0001e007 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 23
				:0,0,27,23
0122e24c:			0000: 0000057f 00000017
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[3] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	0000001b			CP_SCRATCH_REG6: 27
			:0,0,27,23
!+	00000017			CP_SCRATCH_REG7: 23
			:0,0,27,23
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 +	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	01246009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1246000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00100008			PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00100008			PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	40800000			PA_CL_VPORT_XSCALE: 4.000000
!+	40800000			PA_CL_VPORT_XOFFSET: 4.000000
!+	41000000			PA_CL_VPORT_YSCALE: 8.000000
!+	41000000			PA_CL_VPORT_YOFFSET: 8.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 24
				:0,0,27,24
0122e268:			0000: 0000057f 00000018
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122f1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1254
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122d000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122d008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122d014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122d020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122d02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122d034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122d040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122d050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122d05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122d068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122d078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122d084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122d090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122d09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122d0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122d0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122d0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122d0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122d0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122d100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122d11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122d12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122d15c:			2.000000 0.750000 0.375000 0.250000
0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122d190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122d19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 }
0122d1a8:		0000: c0012d00 00040001 01248009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
0122d1b4:		0000: c0022d00 0004000e 80000000 00080004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 33
			:0,0,33,24
0122d1d0:		0000: 0000057e 00000021
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d203 00100000 0112d203 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
0122e088:			0000: c0022d00 00040081 00000000 00080004
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 2.000000
				PA_CL_VPORT_XOFFSET: 2.000000
				PA_CL_VPORT_YSCALE: 4.000000
				PA_CL_VPORT_YOFFSET: 4.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=01254000 (flags=820), size=4x8, pitch=32, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 00424800 01254820 0000e003 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 29
				:0,0,33,29
0122e24c:			0000: 0000057f 0000001d
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[4] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000021			CP_SCRATCH_REG6: 33
			:0,0,33,29
!+	0000001d			CP_SCRATCH_REG7: 29
			:0,0,33,29
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 +	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	01248009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1248000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00080004			PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00080004			PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	40000000			PA_CL_VPORT_XSCALE: 2.000000
!+	40000000			PA_CL_VPORT_XOFFSET: 2.000000
!+	40800000			PA_CL_VPORT_YSCALE: 4.000000
!+	40800000			PA_CL_VPORT_YOFFSET: 4.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 30
				:0,0,33,30
0122e268:			0000: 0000057f 0000001e
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122d1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1255
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122f000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122f008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122f014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122f020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122f02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122f034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122f040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122f050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122f05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122f068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122f078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122f084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122f090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122f09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122f0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122f0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122f0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122f0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122f0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122f100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122f11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122f12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122f15c:			2.000000 0.750000 0.375000 0.250000
0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122f190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122f19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 }
0122f1a8:		0000: c0012d00 00040001 0124a009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 }
0122f1b4:		0000: c0022d00 0004000e 80000000 00040002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 39
			:0,0,39,30
0122f1d0:		0000: 0000057e 00000027
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d283 00100000 0112d283 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 }
0122e088:			0000: c0022d00 00040081 00000000 00040002
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 1.000000
				PA_CL_VPORT_XOFFSET: 1.000000
				PA_CL_VPORT_YSCALE: 2.000000
				PA_CL_VPORT_YOFFSET: 2.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 3f800000 3f800000 40000000 40000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				1.000000 2.000000 0.000000 0.000000 1.000000 2.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 3f800000 40000000 00000000 00000000 3f800000 40000000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=01254000 (flags=820), size=2x4, pitch=32, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 00424800 01254820 00006001 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 35
				:0,0,39,35
0122e24c:			0000: 0000057f 00000023
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[5] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000027			CP_SCRATCH_REG6: 39
			:0,0,39,35
!+	00000023			CP_SCRATCH_REG7: 35
			:0,0,39,35
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 +	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	0124a009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124a000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00040002			PA_SC_SCREEN_SCISSOR_BR: { X = 2 | Y = 4 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00040002			PA_SC_WINDOW_SCISSOR_BR: { X = 2 | Y = 4 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	3f800000			PA_CL_VPORT_XSCALE: 1.000000
!+	3f800000			PA_CL_VPORT_XOFFSET: 1.000000
!+	40000000			PA_CL_VPORT_YSCALE: 2.000000
!+	40000000			PA_CL_VPORT_YOFFSET: 2.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 36
				:0,0,39,36
0122e268:			0000: 0000057f 00000024
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122f1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1256
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122d000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122d008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122d014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122d020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122d02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122d034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122d040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122d050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122d05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122d068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122d078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122d084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122d090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122d09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122d0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122d0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122d0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122d0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122d0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122d100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122d11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122d12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122d15c:			2.000000 0.750000 0.375000 0.250000
0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122d190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122d19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 }
0122d1a8:		0000: c0012d00 00040001 0124c009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 }
0122d1b4:		0000: c0022d00 0004000e 80000000 00020001
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 45
			:0,0,45,36
0122d1d0:		0000: 0000057e 0000002d
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d303 00100000 0112d303 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 }
0122e088:			0000: c0022d00 00040081 00000000 00020001
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 0.500000
				PA_CL_VPORT_XOFFSET: 0.500000
				PA_CL_VPORT_YSCALE: 1.000000
				PA_CL_VPORT_YOFFSET: 1.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 3f000000 3f000000 3f800000 3f800000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				0.500000 1.000000 0.000000 0.000000 0.500000 1.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 3f000000 3f800000 00000000 00000000 3f000000 3f800000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=01254000 (flags=820), size=1x2, pitch=32, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 00424800 01254820 00002000 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 41
				:0,0,45,41
0122e24c:			0000: 0000057f 00000029
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[6] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	0000002d			CP_SCRATCH_REG6: 45
			:0,0,45,41
!+	00000029			CP_SCRATCH_REG7: 41
			:0,0,45,41
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 +	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	0124c009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124c000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00020001			PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 2 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00020001			PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 2 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	3f000000			PA_CL_VPORT_XSCALE: 0.500000
!+	3f000000			PA_CL_VPORT_XOFFSET: 0.500000
!+	3f800000			PA_CL_VPORT_YSCALE: 1.000000
!+	3f800000			PA_CL_VPORT_YOFFSET: 1.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 42
				:0,0,45,42
0122e268:			0000: 0000057f 0000002a
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122d1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1257
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122f000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122f008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122f014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122f020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122f02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122f034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122f040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122f050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122f05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122f068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122f078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122f084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122f090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122f09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122f0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122f0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122f0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122f0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122f0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122f100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122f11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122f12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122f15c:			2.000000 0.750000 0.375000 0.250000
0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122f190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122f19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 }
0122f1a8:		0000: c0012d00 00040001 0124e009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 }
0122f1b4:		0000: c0022d00 0004000e 80000000 00010001
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 51
			:0,0,51,42
0122f1d0:		0000: 0000057e 00000033
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d383 00100000 0112d383 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 }
0122e088:			0000: c0022d00 00040081 00000000 00010001
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 0.500000
				PA_CL_VPORT_XOFFSET: 0.500000
				PA_CL_VPORT_YSCALE: 0.500000
				PA_CL_VPORT_YOFFSET: 0.500000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 3f000000 3f000000 3f000000 3f000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				0.500000 0.500000 0.000000 0.000000 0.500000 0.500000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 3f000000 3f000000 00000000 00000000 3f000000 3f000000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=01254000 (flags=820), size=1x1, pitch=32, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 00424800 01254820 00000000 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 47
				:0,0,51,47
0122e24c:			0000: 0000057f 0000002f
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[7] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000033			CP_SCRATCH_REG6: 51
			:0,0,51,47
!+	0000002f			CP_SCRATCH_REG7: 47
			:0,0,51,47
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
 +	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	0124e009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x124e000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00010001			PA_SC_SCREEN_SCISSOR_BR: { X = 1 | Y = 1 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00010001			PA_SC_WINDOW_SCISSOR_BR: { X = 1 | Y = 1 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
 +	3f000000			PA_CL_VPORT_XSCALE: 0.500000
 +	3f000000			PA_CL_VPORT_XOFFSET: 0.500000
!+	3f000000			PA_CL_VPORT_YSCALE: 0.500000
!+	3f000000			PA_CL_VPORT_YOFFSET: 0.500000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 48
				:0,0,51,48
0122e268:			0000: 0000057f 00000030
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122f1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1258
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122d000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122d008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122d014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122d020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122d02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122d034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122d040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122d050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122d05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122d068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122d078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122d084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122d090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122d09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122d0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122d0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122d0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122d0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122d0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122d100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122d11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122d12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122d15c:			2.000000 0.750000 0.375000 0.250000
0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122d190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
0122d19c:		0000: c0012d00 00040000 00000040
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 }
0122d1a8:		0000: c0012d00 00040001 01230009
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
0122d1b4:		0000: c0022d00 0004000e 80000000 00800040
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 57
			:0,0,57,48
0122d1d0:		0000: 0000057e 00000039
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d403 00100000 0112d403 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
0122e088:			0000: c0022d00 00040081 00000000 00800040
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 32.000000
				PA_CL_VPORT_XOFFSET: 32.000000
				PA_CL_VPORT_YSCALE: 64.000000
				PA_CL_VPORT_YOFFSET: 64.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: xyzw
				addr=0110d000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 80824800 0110d820 000fe03f 00000d11 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 53
				:0,0,57,53
0122e24c:			0000: 0000057f 00000035
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[8] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000039			CP_SCRATCH_REG6: 57
			:0,0,57,53
!+	00000035			CP_SCRATCH_REG7: 53
			:0,0,57,53
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000040			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
!+	01230009			RB_COLOR_INFO: { FORMAT = COLORX_16_16_16_16_FLOAT | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x1230000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00800040			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00800040			PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	42000000			PA_CL_VPORT_XSCALE: 32.000000
!+	42000000			PA_CL_VPORT_XOFFSET: 32.000000
!+	42800000			PA_CL_VPORT_YSCALE: 64.000000
!+	42800000			PA_CL_VPORT_YOFFSET: 64.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
 +	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
 +	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 +	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 54
				:0,0,57,54
0122e268:			0000: 0000057f 00000036
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122d1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1259
############################################################
cmdstream: 340 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0110a000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0110a008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0110a014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0110a020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0110a02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0110a034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0110a040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110a048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0110a050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0110a05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0110a068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0110a078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0110a084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0110a090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0110a09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0110a0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110a0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0110a0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0110a0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0110a0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110a0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0110a0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110a100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110a108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0110a11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110a124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0110a12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0110a13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0110a15c:			2.000000 0.750000 0.375000 0.250000
0110a134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0110a154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110a16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0110a178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0110a190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (5 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
0110a19c:		0000: c0032d00 00040000 00000080 00000205 00010001
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
0110a1b0:		0000: c0012d00 00040207 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
0110a1bc:		0000: c0012d00 00040203 00000000
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110a1d0:			3.069580 0.000000 8441856.000000 8454144.000000
0110a1c8:		0000: c0042d00 0000000c 40447400 00000000 4b00d000 4b010000
t3		opcode: CP_SET_CONSTANT (2d) (10 dwords)
0110a1e8:			0.125490 0.125490 0.500000 0.000000 0.000980 0.000980 0.000000 0.000000
0110a1e0:		0000: c0082d00 0000018c 3e008081 3e008081 3f000000 00000000 3a808081 3a808081
*
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 }
0110a208:		0000: c0012d00 00040316 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 67
			:0,0,67,54
0110a214:		0000: 0000057e 00000043
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110c000
		ibsize:000000c5
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0110c000:			0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (102 dwords)
			vertex shader, start=0000, size=0063
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    100b 0003 1000            	EXEC ADDR(0xb) CNT(0x1)
					0b: 19480000 00262688 00000010	   (S)FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
					    400c 0002 1000            	EXEC ADDR(0xc) CNT(0x4)
					0c: 00010001 00036c00 82000000	   (S)ALU:	MAXv	R1.x___ = R0.wyzw, C0.xxxx
					0d: 4c110302 0000006c 60400201	      ALU:	ADDv	R2.x___ = C0, R2
					                          		    	RECIP_IEEE	R3.x___ = R1.xxxx
					0e: 000f0004 00006c00 c1000300	      ALU:	MULv	R4 = R0, R3.xxxx
					0f: 000f0005 00000000 4b420441	      ALU:	MULADDv	R5 = C1, C2, R4
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1010 0000 1000            	EXEC ADDR(0x10) CNT(0x1)
					10: 000f803e 00000000 c2000000	      ALU:	MAXv	export62 = R0, R0	; gl_Position
					    0000 0000 c600            	ALLOC MEMORY SIZE(0x0)
					    2011 0000 2000            	EXEC_END ADDR(0x11) CNT(0x2)
					11: 000f8020 20136c00 4b010203	      ALU:	MULADDv	export32 = C3, C1.wyww, R2.xxxx
					12: 000f8021 00000000 4b440543	      ALU:	MULADDv	export33 = C3, C4, R5
					    0000 0000 c600            	ALLOC MEMORY SIZE(0x0)
					    2013 0000 1000            	EXEC ADDR(0x13) CNT(0x2)
					13: 000f8020 20136c00 4b010204	      ALU:	MULADDv	export32 = C4, C1.wyww, R2.xxxx
					14: 000f8021 00000000 4b460545	      ALU:	MULADDv	export33 = C5, C6, R5
					    0000 0000 c600            	ALLOC MEMORY SIZE(0x0)
					    2015 0000 1000            	EXEC ADDR(0x15) CNT(0x2)
					15: 000f8020 20136c00 4b010205	      ALU:	MULADDv	export32 = C5, C1.wyww, R2.xxxx
					16: 000f8021 00000000 4b480547	      ALU:	MULADDv	export33 = C7, C8, R5
					    0000 0000 c600            	ALLOC MEMORY SIZE(0x0)
					    2017 0000 1000            	EXEC ADDR(0x17) CNT(0x2)
					17: 000f8020 20136c00 4b010206	      ALU:	MULADDv	export32 = C6, C1.wyww, R2.xxxx
					18: 000f8021 00000000 4b4a0549	      ALU:	MULADDv	export33 = C9, C10, R5
					    0000 0000 c600            	ALLOC MEMORY SIZE(0x0)
					    2019 0000 1000            	EXEC ADDR(0x19) CNT(0x2)
					19: 000f8020 20136c00 4b010207	      ALU:	MULADDv	export32 = C7, C1.wyww, R2.xxxx
					1a: 000f8021 00000000 4b4c054b	      ALU:	MULADDv	export33 = C11, C12, R5
					    0000 0000 c600            	ALLOC MEMORY SIZE(0x0)
					    201b 0000 1000            	EXEC ADDR(0x1b) CNT(0x2)
					1b: 000f8020 20136c00 4b010208	      ALU:	MULADDv	export32 = C8, C1.wyww, R2.xxxx
					1c: 000f8021 00000000 4b4e054d	      ALU:	MULADDv	export33 = C13, C14, R5
					    0000 0000 c600            	ALLOC MEMORY SIZE(0x0)
					    201d 0000 1000            	EXEC ADDR(0x1d) CNT(0x2)
					1d: 000f8020 20136c00 4b010209	      ALU:	MULADDv	export32 = C9, C1.wyww, R2.xxxx
					1e: 000f8021 00000000 4b50054f	      ALU:	MULADDv	export33 = C15, C16, R5
					    0000 0000 c600            	ALLOC MEMORY SIZE(0x0)
					    201f 0000 2000            	EXEC_END ADDR(0x1f) CNT(0x2)
					1f: 000f8020 20136c00 4b01020a	      ALU:	MULADDv	export32 = C10, C1.wyww, R2.xxxx
					20: 000f8021 00000000 4b520551	      ALU:	MULADDv	export33 = C17, C18, R5
					    0000 0000 0000            	NOP
0110c018:			0000: c0642b00 00000000 00000063 00000000 100bc400 10000003 0002400c 00001000
0110c038:			0020: c2000000 00001010 00001000 c6000000 00002011 00002000 c6000000 00002013
0110c058:			0040: 00001000 c6000000 00002015 00001000 c6000000 00002017 00001000 c6000000
0110c078:			0060: 00002019 00001000 c6000000 0000201b 00001000 c6000000 0000201d 00001000
0110c098:			0080: c6000000 0000201f 00002000 00000000 19480000 00262688 00000010 00010001
0110c0b8:			00a0: 00036c00 82000000 4c110302 0000006c 60400201 000f0004 00006c00 c1000300
0110c0d8:			00c0: 000f0005 00000000 4b420441 000f803e 00000000 c2000000 000f8020 20136c00
0110c0f8:			00e0: 4b010203 000f8021 00000000 4b440543 000f8020 20136c00 4b010204 000f8021
0110c118:			0100: 00000000 4b460545 000f8020 20136c00 4b010205 000f8021 00000000 4b480547
0110c138:			0120: 000f8020 20136c00 4b010206 000f8021 00000000 4b4a0549 000f8020 20136c00
0110c158:			0140: 4b010207 000f8021 00000000 4b4c054b 000f8020 20136c00 4b010208 000f8021
0110c178:			0160: 00000000 4b4e054d 000f8020 20136c00 4b010209 000f8021 00000000 4b50054f
0110c198:			0180: 000f8020 20136c00 4b01020a 000f8021 00000000 4b520551
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0110c1b0:			0000: c0012d00 00040181 00000006
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX }
0110c1bc:			0000: c0012d00 00040180 90030005
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110c1d0:				0.000000 0.000000 0.000000 0.000000
0110c1c8:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0110c1e8:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
0110c1e0:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
0110c200:			0020: 3f000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0110c208:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110c214:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE }
0110c220:			0000: c0012d00 00040205 40000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0110c22c:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0110c238:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110c240:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0110c254:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110c278:				0.000000 0.000000 0.000000 0.000000
0110c270:			0000: c0042d00 00000180 00000000 00000000 00000000 00000000
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 61
				:0,0,67,61
0110c288:			0000: 0000057f 0000003d
t3			opcode: CP_DRAW_INDX (22) (5 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
				{ NUM_INDICES = 18011360 }
				{ INDX_BASE = 0xc }
			draw:          0
			prim_type:     DI_PT_TRILIST (4)
			source_select: DI_SRC_SEL_DMA (0)
			num_indices:   18011360
			draw[9] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000043			CP_SCRATCH_REG6: 67
			:0,0,67,61
!+	0000003d			CP_SCRATCH_REG7: 61
			:0,0,67,61
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000080			RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
!+	00000205			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
!+	00010001			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
!+	000000ff			RB_BLEND_ALPHA: 0xff
!+	90030005			SQ_PROGRAM_CNTL: { VS_REGS = 5 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 | GEN_INDEX_VTX }
!+	00000006			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000000			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
!+	40000000			PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_POINTS | BACK_PTYPE = PC_DRAW_POINTS | FACE_KILL_ENABLE }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000000			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 0 | ROW = 0 | GUARD_BAND_MASK = 0 }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
!+	00000000			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 0 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0110c290:			0000: c0032200 00000000 00060004 0112d4e0 0000000c
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 62
				:0,0,67,62
0110c2a4:			0000: 0000057f 0000003e
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0110c2ac:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2b4:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2bc:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2c4:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2cc:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2d4:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2dc:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2e4:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2ec:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2f4:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c2fc:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c304:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110c30c:			0000: c0004600 00000006
0110a21c:		0000: c0013700 0110c000 000000c5
t2		nop
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0110a234:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
0110a240:		0000: c0012d00 00040001 00000205
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
0110a24c:		0000: c0022d00 0004000e 00000000 00800080
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
0110a25c:		0000: c0012d00 00040001 00000205
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110a268:		0000: c0012d00 00040080 00000000
t3		opcode: CP_MEM_WRITE (3d) (3 dwords)
			{ ADDR_LO = 0x100903c }
			{ ADDR_HI = 0x800080 }
		gpuaddr:0100903c
0110a27c:			0.000000
0110a274:		0000: c0013d00 0100903c 00800080
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 }
0110a280:		0000: c0012d00 0004031c 00000000
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110a294:			0.000000 0.000000 0.000000 0.000000
0110a28c:		0000: c0042d00 00000580 00000000 00000000 00000000 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
0110a2a4:		0000: c0012d00 00040207 00000009
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
0110a2b0:		0000: c0012d00 00040203 00000009
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110a2bc:		0000: c0004b00 0111d000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 69
			:0,0,69,62
0110a2c4:		0000: 0000057e 00000045
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110b000
		ibsize:00000198
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
0110b000:			0000: c0022d00 00040081 00000000 3fff3fff
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_CL_VPORT_XSCALE: 4096.000000
				PA_CL_VPORT_XOFFSET: 4096.000000
				PA_CL_VPORT_YSCALE: 4096.000000
				PA_CL_VPORT_YOFFSET: 4096.000000
0110b010:			0000: c0042d00 0004010f 45800000 45800000 45800000 45800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
			set shader const 009c
0110b028:			0000: c0022d00 0001009c 01009003 00000024
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0110b038:			0000: c0012d00 00040102 00000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			vertex shader, start=0000, size=000c
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 19a80000 00392a88 0000000c	   (S)FETCH:	VERTEX	R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f803e 00000000 c2000000	   (S)ALU:	MAXv	export62 = R0, R0	; gl_Position
0110b044:			0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
0110b064:			0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
			fragment shader, start=0000, size=0006
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1001 0002 2000            	EXEC_END ADDR(0x1) CNT(0x1)
					01: 000f8000 00000000 02000000	   (S)ALU:	MAXv	export0 = C0, C0	; gl_FragColor
0110b080:			0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
0110b0a0:			0020: 02000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0110b0a4:			0000: c0012d00 00040181 00000006
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0110b0b0:			0000: c0012d00 00040180 10038002
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0110b0bc:			0000: 00000e00 00000001
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0110b0c4:			0000: c0012d00 00040200 0000877f
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0110b0d0:			0000: c0012d00 00040202 00000c27
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
0110b0dc:			0000: c0022d00 00040204 00000000 00088240
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
0110b0ec:			0000: c0012d00 00040301 00000003
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0110b0f8:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110b104:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0110b110:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
0110b11c:			0000: c0012d00 0004000f 00400020
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
				RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 }
0110b128:			0000: c0032d00 00040000 00008020 00000005 00008001
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110b144:				0.501961 0.250980 0.125490 1.000000
0110b13c:			0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.996586
0110b154:			0000: c0022d00 00040113 00000000 3f7f2041
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
				RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
0110b164:			0000: c0022d00 0004010c ffff0080 ffff0080
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 1
				:0,0,69,1
0110b174:			0000: 0000057f 00000001
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
			draw:          0
			prim_type:     DI_PT_RECTLIST (8)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[10] register values
!+	00000045			CP_SCRATCH_REG6: 69
			:0,0,69,1
!+	00000001			CP_SCRATCH_REG7: 1
			:0,0,69,1
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
!+	00008020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
!+	00000005			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
!+	00008001			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 32768 }
!+	00000000			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00400020			PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	3fff3fff			PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
!+	ffff0080			RB_STENCILREFMASK_BF: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
!+	ffff0080			RB_STENCILREFMASK: { STENCILREF = 0x80 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
!+	45800000			PA_CL_VPORT_XSCALE: 4096.000000
!+	45800000			PA_CL_VPORT_XOFFSET: 4096.000000
!+	45800000			PA_CL_VPORT_YSCALE: 4096.000000
!+	45800000			PA_CL_VPORT_YOFFSET: 4096.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
!+	3f7f2041			PA_CL_VPORT_ZOFFSET: 0.996586
!+	10038002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000006			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
!+	0000877f			RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00000c27			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
!+	00000009			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00088240			PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
!+	00000009			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 1 | GUARD_BAND_MASK = 0 }
!+	00000003			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
!+	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000000			RB_COPY_DEST_OFFSET: { X = 0 | Y = 0 }
0110b17c:			0000: c0012200 00000000 00030088
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 2
				:0,0,69,2
0110b188:			0000: 0000057f 00000002
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0110b190:			0000: c0012d00 00040301 00000000
t3			opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords)
0110b19c:			0000: c0022e00 01009000 0004000f 00000001
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
				RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
0110b1ac:			0000: c0032d00 00040000 00000080 00000205 00010001
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
0110b1c0:			0000: c0022d00 00040081 00000000 3fff3fff
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_CL_VPORT_XSCALE: 4096.000000
				PA_CL_VPORT_XOFFSET: 4096.000000
				PA_CL_VPORT_YSCALE: 4096.000000
				PA_CL_VPORT_YOFFSET: 4096.000000
0110b1d0:			0000: c0042d00 0004010f 45800000 45800000 45800000 45800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
			set shader const 009c
0110b1e8:			0000: c0022d00 0001009c 01009003 00000024
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0110b1f8:			0000: c0012d00 00040102 00000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			vertex shader, start=0000, size=000c
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 19a80000 00392a88 0000000c	   (S)FETCH:	VERTEX	R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f803e 00000000 c2000000	   (S)ALU:	MAXv	export62 = R0, R0	; gl_Position
0110b204:			0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
0110b224:			0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
			fragment shader, start=0000, size=0006
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1001 0002 2000            	EXEC_END ADDR(0x1) CNT(0x1)
					01: 000f8000 00000000 02000000	   (S)ALU:	MAXv	export0 = C0, C0	; gl_FragColor
0110b240:			0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
0110b260:			0020: 02000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0110b264:			0000: c0012d00 00040181 00000006
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0110b270:			0000: c0012d00 00040180 10038002
t0			write TC_CNTL_STATUS (0e00)
NEEDS WFI: TC_CNTL_STATUS (e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0110b27c:			0000: 00000e00 00000001
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0110b284:			0000: c0012d00 00040200 0000877f
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0110b290:			0000: c0012d00 00040202 00000c27
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
0110b29c:			0000: c0022d00 00040204 00000000 00088240
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
0110b2ac:			0000: c0012d00 00040301 00000003
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0110b2b8:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110b2c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0110b2d0:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 }
0110b2dc:			0000: c0012d00 0004000f 00800020
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
				RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
0110b2e8:			0000: c0032d00 00040000 00008020 00000005 00010001
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110b304:				0.501961 0.250980 0.125490 1.000000
0110b2fc:			0000: c0042d00 00000480 3f008081 3e808081 3e008081 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 1.000000
0110b314:			0000: c0022d00 00040113 00000000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
0110b324:			0000: c0022d00 0004010c ffff0000 ffff0000
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 3
				:0,0,69,3
0110b334:			0000: 0000057f 00000003
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
			draw:          1
			prim_type:     DI_PT_RECTLIST (8)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[11] register values
!+	00000003			CP_SCRATCH_REG7: 3
			:0,0,69,3
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00008020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 2 }
 +	00000005			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
!+	00010001			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
!+	00800020			PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 128 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
 +	3fff3fff			PA_SC_WINDOW_SCISSOR_BR: { X = 16383 | Y = 16383 }
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
!+	ffff0000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
!+	ffff0000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 }
 +	45800000			PA_CL_VPORT_XSCALE: 4096.000000
 +	45800000			PA_CL_VPORT_XOFFSET: 4096.000000
 +	45800000			PA_CL_VPORT_YSCALE: 4096.000000
 +	45800000			PA_CL_VPORT_YOFFSET: 4096.000000
 +	00000000			PA_CL_VPORT_ZSCALE: 0.000000
!+	3f800000			PA_CL_VPORT_ZOFFSET: 1.000000
 +	10038002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000006			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
 +	0000877f			RB_DEPTHCONTROL: { STENCIL_ENABLE | Z_ENABLE | Z_WRITE_ENABLE | EARLY_Z_ENABLE | ZFUNC = FUNC_ALWAYS | STENCILFUNC = FUNC_ALWAYS | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_REPLACE | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
 +	00000c27			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_ALWAYS | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
 +	00088240			PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | MSAA_ENABLE | PROVOKING_VTX_LAST }
 +	00000003			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 3 | MAX_SAMPLE_DIST = 0 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
0110b33c:			0000: c0012200 00000000 00030088
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 4
				:0,0,69,4
0110b348:			0000: 0000057f 00000004
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0110b350:			0000: c0012d00 00040301 00000000
t3			opcode: CP_LOAD_CONSTANT_CONTEXT (2e) (4 dwords)
0110b35c:			0000: c0022e00 01009000 0004000f 00000001
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
				RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
0110b36c:			0000: c0032d00 00040000 00000080 00000205 00010001
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0110b380:			0000: c0042d00 00010078 0112d483 00100000 0112d4c3 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0110b398:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0110b3a4:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0110b3b0:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0110b3c4:			0000: c0022d00 00040204 00000000 00090240
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0110b3d4:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0110b3ec:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
0110b408:			0000: c0022d00 00040081 00000000 01000100
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 128.000000
				PA_CL_VPORT_XOFFSET: 128.000000
				PA_CL_VPORT_YSCALE: -128.000000
				PA_CL_VPORT_YOFFSET: 128.000000
				PA_CL_VPORT_ZSCALE: 0.500000
				PA_CL_VPORT_ZOFFSET: 0.500000
0110b418:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0110b440:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
0110b438:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
0110b458:			0020: 3f000000 00000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
					04: 13480000 40252fc8 00000008	      FETCH:	VERTEX	R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 00038000 00000000 c2000000	      ALU:	MAXv	export0.xy__ = R0, R0
					    0000 0000 0000            	NOP
0110b460:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0110b480:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
0110b4a0:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0110b4c0:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0110b4e0:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0110b4fc:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0110b508:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110b51c:				0.000000 0.000000 0.000000 0.000000
0110b514:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0110b52c:			0000: c0012d00 00040202 00001c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0110b538:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110b544:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0110b550:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
				filter min/mag: point/point
				swizzle: xyzw
				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
				mipaddr=01240000 (flags=200)
0110b568:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0110b588:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
NEEDS WFI: TC_CNTL_STATUS (e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0110b594:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110b59c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0110b5b0:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 59
				:0,0,69,59
0110b5cc:			0000: 0000057f 0000003b
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0110b5d4:			0000: c0053400 00000000 0006c004 00000000 00000006 0112d4e0 0000000c
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 60
				:0,0,69,60
0110b5f0:			0000: 0000057f 0000003c
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0110b5f8:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b600:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b608:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b610:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b618:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b620:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b628:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b630:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b638:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b640:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b648:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b650:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b658:			0000: c0004600 00000006
0110a2cc:		0000: c0013700 0110b000 00000198
t2		nop
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 71
			:0,0,71,60
0110a2e4:		0000: 0000057e 00000047
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0125e000
		ibsize:00000064
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
			set shader const 009c
0125e000:			0000: c0022d00 0001009c 01009003 00000024
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0125e010:			0000: c0012d00 00040080 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0125e01c:			0000: c0012d00 00040102 00000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			vertex shader, start=0000, size=000c
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 19a80000 00392a88 0000000c	   (S)FETCH:	VERTEX	R0.xyz1 = R0.x FMT_32_32_32_FLOAT UNSIGNED STRIDE(12) CONST(26, 0)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f803e 00000000 c2000000	   (S)ALU:	MAXv	export62 = R0, R0	; gl_Position
0125e028:			0000: c00d2b00 00000000 0000000c 00000000 1002c400 10000003 00000000 1003c200
0125e048:			0020: 20000002 19a80000 00392a88 0000000c 000f803e 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (9 dwords)
			fragment shader, start=0000, size=0006
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1001 0002 2000            	EXEC_END ADDR(0x1) CNT(0x1)
					01: 000f8000 00000000 02000000	   (S)ALU:	MAXv	export0 = C0, C0	; gl_FragColor
0125e064:			0000: c0072b00 00000001 00000006 00000000 1001c400 20000002 000f8000 00000000
0125e084:			0020: 02000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0125e088:			0000: c0012d00 00040181 00000006
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0125e094:			0000: c0012d00 00040180 10038002
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0125e0a0:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0125e0ac:			0000: c0012d00 00040200 00000008
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
0125e0b8:			0000: c0012d00 00040205 00080240
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
0125e0c4:			0000: c0022d00 00040081 00000000 01000100
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
0125e0d4:			0000: c0012d00 00040204 00000000
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_CL_VPORT_XSCALE: 64.000000
				PA_CL_VPORT_XOFFSET: 64.000000
				PA_CL_VPORT_YSCALE: 64.000000
				PA_CL_VPORT_YOFFSET: 64.000000
0125e0e0:			0000: c0042d00 0004010f 42800000 42800000 42800000 42800000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY }
0125e0f8:			0000: c0012d00 00040208 00000006
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 }
0125e104:			0000: c0012d00 00040001 00010005
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
				RB_COPY_DEST_BASE: 0x10ca000
				RB_COPY_DEST_PITCH: 256
				RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0125e110:			0000: c0042d00 00040318 00000000 010ca000 00000008 0003c058
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 63
				:0,0,71,63
0125e128:			0000: 0000057f 0000003f
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
			draw:          0
			prim_type:     DI_PT_RECTLIST (8)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[12] register values
!+	00000047			CP_SCRATCH_REG6: 71
			:0,0,71,63
!+	0000003f			CP_SCRATCH_REG7: 63
			:0,0,71,63
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
!+	00000080			RB_SURFACE_INFO: { SURFACE_PITCH = 128 | MSAA_SAMPLES = 0 }
!+	00010005			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0x10000 }
 +	00010001			RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_24_8 | DEPTH_BASE = 65536 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	01000100			PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
!+	00000000			RB_BLEND_ALPHA: 0
!+	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
!+	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	42800000			PA_CL_VPORT_XSCALE: 64.000000
!+	42800000			PA_CL_VPORT_XOFFSET: 64.000000
!+	42800000			PA_CL_VPORT_YSCALE: 64.000000
!+	42800000			PA_CL_VPORT_YOFFSET: 64.000000
!+	3f000000			PA_CL_VPORT_ZSCALE: 0.500000
!+	3f000000			PA_CL_VPORT_ZOFFSET: 0.500000
 +	10038002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 128 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000006			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
!+	00000008			RB_DEPTHCONTROL: { EARLY_Z_ENABLE | ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00001c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00080240			PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST }
!+	00000006			RB_MODECONTROL: { EDRAM_MODE = EDRAM_COPY }
!+	00080008			PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
!+	00080008			PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
!+	00000008			PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
!+	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000000			RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
!+	010ca000			RB_COPY_DEST_BASE: 0x10ca000
!+	00000008			RB_COPY_DEST_PITCH: 256
!+	0003c058			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | LINEAR | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0125e130:			0000: c0012200 00000000 00030088
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 64
				:0,0,71,64
0125e13c:			0000: 0000057f 00000040
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
0125e144:			0000: c0012d00 00040001 00000005
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
				RB_COPY_DEST_BASE: 0x108a000
				RB_COPY_DEST_PITCH: 256
				RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0125e150:			0000: c0042d00 00040318 00000000 0108a000 00000008 0003c050
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 65
				:0,0,71,65
0125e168:			0000: 0000057f 00000041
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x30000 }
			draw:          1
			prim_type:     DI_PT_RECTLIST (8)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[13] register values
!+	00000041			CP_SCRATCH_REG7: 65
			:0,0,71,65
!+	00000005			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 0 | BASE = 0 }
 +	00000000			RB_COPY_CONTROL: { COPY_SAMPLE_SELECT = SAMPLE_0 | CLEAR_MASK = 0 }
!+	0108a000			RB_COPY_DEST_BASE: 0x108a000
 +	00000008			RB_COPY_DEST_PITCH: 256
!+	0003c050			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_8_8_8_8 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0125e170:			0000: c0012200 00000000 00030088
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 66
				:0,0,71,66
0125e17c:			0000: 0000057f 00000042
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0125e184:			0000: c0012d00 00040208 00000004
0110a2ec:		0000: c0013700 0125e000 00000064
t2		nop
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
0110a304:		0000: c0012d00 00040001 00000205
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
0110a310:		0000: c0022d00 0004000e 00000000 00800080
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
0110a320:		0000: c0012d00 00040001 00000205
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = -128 | Y = 0 }
0110a32c:		0000: c0012d00 00040080 00007f80
t3		opcode: CP_MEM_WRITE (3d) (3 dwords)
			{ ADDR_LO = 0x100903c }
			{ ADDR_HI = 0x800080 }
		gpuaddr:0100903c
0110a340:			0.000000
0110a338:		0000: c0013d00 0100903c 00800080
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_OFFSET: { X = 128 | Y = 0 }
0110a344:		0000: c0012d00 0004031c 00000080
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110a358:			128.000000 0.000000 0.000000 0.000000
0110a350:		0000: c0042d00 00000580 43000000 00000000 00000000 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 }
0110a368:		0000: c0012d00 00040207 0000000a
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 1 | GUARD_BAND_MASK = 0 }
0110a374:		0000: c0012d00 00040203 0000000a
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110a380:		0000: c0004b00 0111d000
t0		write CP_SCRATCH_REG6 (057e)
NEEDS WFI: CP_SCRATCH_REG6 (57e)
			CP_SCRATCH_REG6: 73
			:0,0,73,66
0110a388:		0000: 0000057e 00000049
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110b000
		ibsize:00000198
0110a390:		0000: c0013700 0110b000 00000198
t2		nop
t0		write CP_SCRATCH_REG6 (057e)
NEEDS WFI: CP_SCRATCH_REG6 (57e)
			CP_SCRATCH_REG6: 75
			:0,0,75,66
0110a3a8:		0000: 0000057e 0000004b
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0125e000
		ibsize:00000064
0110a3b0:		0000: c0013700 0125e000 00000064
t2		nop
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
0110a3c8:		0000: c0012d00 00040001 00000205
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
0110a3d4:		0000: c0022d00 0004000e 00000000 00800080
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
0110a3e4:		0000: c0012d00 00040001 00000205
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = -128 }
0110a3f0:		0000: c0012d00 00040080 7f800000
t3		opcode: CP_MEM_WRITE (3d) (3 dwords)
			{ ADDR_LO = 0x100903c }
			{ ADDR_HI = 0x800080 }
		gpuaddr:0100903c
0110a404:			0.000000
0110a3fc:		0000: c0013d00 0100903c 00800080
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_OFFSET: { X = 0 | Y = 128 }
0110a408:		0000: c0012d00 0004031c 00100000
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110a41c:			0.000000 128.000000 0.000000 0.000000
0110a414:		0000: c0042d00 00000580 00000000 43000000 00000000 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 }
0110a42c:		0000: c0012d00 00040207 00000011
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 1 | ROW = 2 | GUARD_BAND_MASK = 0 }
0110a438:		0000: c0012d00 00040203 00000011
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110a444:		0000: c0004b00 0111d000
t0		write CP_SCRATCH_REG6 (057e)
NEEDS WFI: CP_SCRATCH_REG6 (57e)
			CP_SCRATCH_REG6: 77
			:0,0,77,66
0110a44c:		0000: 0000057e 0000004d
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110b000
		ibsize:00000198
0110a454:		0000: c0013700 0110b000 00000198
t2		nop
t0		write CP_SCRATCH_REG6 (057e)
NEEDS WFI: CP_SCRATCH_REG6 (57e)
			CP_SCRATCH_REG6: 79
			:0,0,79,66
0110a46c:		0000: 0000057e 0000004f
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0125e000
		ibsize:00000064
0110a474:		0000: c0013700 0125e000 00000064
t2		nop
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
0110a48c:		0000: c0012d00 00040001 00000205
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 128 | Y = 128 }
0110a498:		0000: c0022d00 0004000e 00000000 00800080
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0 }
0110a4a8:		0000: c0012d00 00040001 00000205
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = -128 | Y = -128 }
0110a4b4:		0000: c0012d00 00040080 7f807f80
t3		opcode: CP_MEM_WRITE (3d) (3 dwords)
			{ ADDR_LO = 0x100903c }
			{ ADDR_HI = 0x800080 }
		gpuaddr:0100903c
0110a4c8:			0.000000
0110a4c0:		0000: c0013d00 0100903c 00800080
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 }
0110a4cc:		0000: c0012d00 0004031c 00100080
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110a4e0:			128.000000 128.000000 0.000000 0.000000
0110a4d8:		0000: c0042d00 00000580 43000000 43000000 00000000 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
0110a4f0:		0000: c0012d00 00040207 00000012
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
0110a4fc:		0000: c0012d00 00040203 00000012
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110a508:		0000: c0004b00 0111d000
t0		write CP_SCRATCH_REG6 (057e)
NEEDS WFI: CP_SCRATCH_REG6 (57e)
			CP_SCRATCH_REG6: 81
			:0,0,81,66
0110a510:		0000: 0000057e 00000051
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110b000
		ibsize:00000198
0110a518:		0000: c0013700 0110b000 00000198
t2		nop
t0		write CP_SCRATCH_REG6 (057e)
NEEDS WFI: CP_SCRATCH_REG6 (57e)
			CP_SCRATCH_REG6: 83
			:0,0,83,66
0110a530:		0000: 0000057e 00000053
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0125e000
		ibsize:00000064
0110a538:		0000: c0013700 0125e000 00000064
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1260
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
NEEDS WFI: RB_BC_CONTROL (f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122f000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122f008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122f014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122f020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
NEEDS WFI: CP_PERFMON_CNTL (444)
			CP_PERFMON_CNTL: 0
0122f02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
NEEDS WFI: RBBM_PM_OVERRIDE1 (39c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
NEEDS WFI: RBBM_PM_OVERRIDE2 (39d)
			RBBM_PM_OVERRIDE2: 0xfff
0122f034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
NEEDS WFI: TP0_CHICKEN (e1e)
			TP0_CHICKEN: 0x2
0122f040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122f050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122f05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122f068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122f078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122f084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122f090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122f09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122f0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122f0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122f0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122f0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122f0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122f100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
NEEDS WFI: SQ_INST_STORE_MANAGMENT (d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122f11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122f12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122f15c:			2.000000 0.750000 0.375000 0.250000
0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122f190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
0122f19c:		0000: c0012d00 00040000 00000040
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 }
0122f1a8:		0000: c0012d00 00040001 01256245
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
0122f1b4:		0000: c0022d00 0004000e 80000000 00800040
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
NEEDS WFI: CP_SCRATCH_REG6 (57e)
			CP_SCRATCH_REG6: 89
			:0,0,89,66
0122f1d0:		0000: 0000057e 00000059
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d4ef 00100000 0112d4ef 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
0122e088:			0000: c0022d00 00040081 00000000 00800040
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 32.000000
				PA_CL_VPORT_XOFFSET: 32.000000
				PA_CL_VPORT_YSCALE: 64.000000
				PA_CL_VPORT_YOFFSET: 64.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 42000000 42000000 42800000 42800000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				32.000000 64.000000 0.000000 0.000000 32.000000 64.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 42000000 42800000 00000000 00000000 42000000 42800000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: zyxw
				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
NEEDS WFI: TC_CNTL_STATUS (e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 85
				:0,0,89,85
0122e24c:			0000: 0000057f 00000055
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[14] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000059			CP_SCRATCH_REG6: 89
			:0,0,89,85
!+	00000055			CP_SCRATCH_REG7: 85
			:0,0,89,85
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000040			RB_SURFACE_INFO: { SURFACE_PITCH = 64 | MSAA_SAMPLES = 0 }
!+	01256245			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1256000 }
!+	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00800040			PA_SC_SCREEN_SCISSOR_BR: { X = 64 | Y = 128 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00800040			PA_SC_WINDOW_SCISSOR_BR: { X = 64 | Y = 128 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	42000000			PA_CL_VPORT_XSCALE: 32.000000
!+	42000000			PA_CL_VPORT_XOFFSET: 32.000000
 +	42800000			PA_CL_VPORT_YSCALE: 64.000000
 +	42800000			PA_CL_VPORT_YOFFSET: 64.000000
!+	00000000			PA_CL_VPORT_ZSCALE: 0.000000
!+	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
!+	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
!+	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
!+	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
!+	00000012			VGT_CURRENT_BIN_ID_MAX: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
!+	00000012			VGT_CURRENT_BIN_ID_MIN: { COLUMN = 2 | ROW = 2 | GUARD_BAND_MASK = 0 }
!+	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
!+	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
!+	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
!+	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
!+	00100080			RB_COPY_DEST_OFFSET: { X = 128 | Y = 128 }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 86
				:0,0,89,86
0122e268:			0000: 0000057f 00000056
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122f1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1261
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0110c000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0110c008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0110c014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0110c020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0110c02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0110c034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0110c040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110c048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0110c050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0110c05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0110c068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0110c078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0110c084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0110c090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0110c09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0110c0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110c0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0110c0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0110c0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0110c0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110c0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0110c0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110c100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110c108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0110c11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110c124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0110c12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0110c13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0110c15c:			2.000000 0.750000 0.375000 0.250000
0110c134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0110c154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110c16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0110c178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0110c190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
0110c19c:		0000: c0012d00 00040000 00000100
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
0110c1a8:		0000: c0012d00 00040001 0108a205
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
0110c1b4:		0000: c0022d00 0004000e 80000000 01000100
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110c1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 95
			:0,0,95,86
0110c1d0:		0000: 0000057e 0000005f
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110b000
		ibsize:000000b8
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0110b000:			0000: c0042d00 00010078 0112d56f 00100000 0112d5af 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0110b018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0110b024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0110b030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0110b044:			0000: c0022d00 00040204 00000000 00090240
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0110b054:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0110b06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
0110b088:			0000: c0022d00 00040081 00000000 01000100
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 128.000000
				PA_CL_VPORT_XOFFSET: 128.000000
				PA_CL_VPORT_YSCALE: -128.000000
				PA_CL_VPORT_YOFFSET: 128.000000
				PA_CL_VPORT_ZSCALE: 0.500000
				PA_CL_VPORT_ZOFFSET: 0.500000
0110b098:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0110b0c0:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
0110b0b8:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
0110b0d8:			0020: 3f000000 00000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
					04: 13480000 40252fc8 00000008	      FETCH:	VERTEX	R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 00038000 00000000 c2000000	      ALU:	MAXv	export0.xy__ = R0, R0
					    0000 0000 0000            	NOP
0110b0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0110b100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
0110b120:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0110b140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0110b160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0110b17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0110b188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110b19c:				0.000000 0.000000 0.000000 0.000000
0110b194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0110b1ac:			0000: c0012d00 00040202 00001c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0110b1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110b1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0110b1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
				filter min/mag: point/point
				swizzle: xyzw
				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
				mipaddr=01240000 (flags=200)
0110b1e8:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0110b208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0110b214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110b21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0110b230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 91
				:0,0,95,91
0110b24c:			0000: 0000057f 0000005b
t3			opcode: CP_NOP (10) (2 dwords)
0110b254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (5 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
				{ NUM_INDICES = 18011596 }
				{ INDX_BASE = 0xc }
			draw:          0
			prim_type:     DI_PT_TRILIST (4)
			source_select: DI_SRC_SEL_DMA (0)
			num_indices:   18011596
			draw[15] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	0000005f			CP_SCRATCH_REG6: 95
			:0,0,95,91
!+	0000005b			CP_SCRATCH_REG7: 91
			:0,0,95,91
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000100			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
!+	0108a205			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	01000100			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	01000100			PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	43000000			PA_CL_VPORT_XSCALE: 128.000000
!+	43000000			PA_CL_VPORT_XOFFSET: 128.000000
!+	c3000000			PA_CL_VPORT_YSCALE: -128.000000
!+	43000000			PA_CL_VPORT_YOFFSET: 128.000000
!+	3f000000			PA_CL_VPORT_ZSCALE: 0.500000
!+	3f000000			PA_CL_VPORT_ZOFFSET: 0.500000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00001c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090240			PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00080008			PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
!+	00080008			PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
!+	00000008			PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0110b25c:			0000: c0032200 00000000 00060004 0112d5cc 0000000c
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 92
				:0,0,95,92
0110b270:			0000: 0000057f 0000005c
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0110b278:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2d0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2d8:			0000: c0004600 00000006
0110c1d8:		0000: c0013700 0110b000 000000b8
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1262
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122d000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122d008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122d014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122d020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122d02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122d034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122d040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122d050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122d05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122d068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122d078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122d084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122d090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122d09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122d0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122d0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122d0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122d0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122d0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122d100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122d11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122d12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122d15c:			2.000000 0.750000 0.375000 0.250000
0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122d190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122d19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 }
0122d1a8:		0000: c0012d00 00040001 01254245
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
0122d1b4:		0000: c0022d00 0004000e 80000000 00400020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 101
			:0,0,101,92
0122d1d0:		0000: 0000057e 00000065
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d5db 00100000 0112d5db 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
0122e088:			0000: c0022d00 00040081 00000000 00400020
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 16.000000
				PA_CL_VPORT_XOFFSET: 16.000000
				PA_CL_VPORT_YSCALE: 32.000000
				PA_CL_VPORT_YOFFSET: 32.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 41800000 41800000 42000000 42000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				16.000000 32.000000 0.000000 0.000000 16.000000 32.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 41800000 42000000 00000000 00000000 41800000 42000000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: zyxw
				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 97
				:0,0,101,97
0122e24c:			0000: 0000057f 00000061
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[16] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000065			CP_SCRATCH_REG6: 101
			:0,0,101,97
!+	00000061			CP_SCRATCH_REG7: 97
			:0,0,101,97
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	01254245			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1254000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00400020			PA_SC_SCREEN_SCISSOR_BR: { X = 32 | Y = 64 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00400020			PA_SC_WINDOW_SCISSOR_BR: { X = 32 | Y = 64 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	41800000			PA_CL_VPORT_XSCALE: 16.000000
!+	41800000			PA_CL_VPORT_XOFFSET: 16.000000
!+	42000000			PA_CL_VPORT_YSCALE: 32.000000
!+	42000000			PA_CL_VPORT_YOFFSET: 32.000000
!+	00000000			PA_CL_VPORT_ZSCALE: 0.000000
!+	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
!+	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
!+	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 98
				:0,0,101,98
0122e268:			0000: 0000057f 00000062
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122d1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1263
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0110a000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0110a008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0110a014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0110a020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0110a02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0110a034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0110a040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110a048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0110a050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0110a05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0110a068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0110a078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0110a084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0110a090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0110a09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0110a0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110a0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0110a0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0110a0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0110a0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110a0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0110a0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110a100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110a108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0110a11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110a124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0110a12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0110a13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0110a15c:			2.000000 0.750000 0.375000 0.250000
0110a134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0110a154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110a16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0110a178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0110a190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
0110a19c:		0000: c0012d00 00040000 00000100
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
0110a1a8:		0000: c0012d00 00040001 0108a205
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
0110a1b4:		0000: c0022d00 0004000e 80000000 01000100
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110a1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 107
			:0,0,107,98
0110a1d0:		0000: 0000057e 0000006b
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110b000
		ibsize:000000b8
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0110b000:			0000: c0042d00 00010078 0112d65b 00100000 0112d69b 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0110b018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0110b024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0110b030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0110b044:			0000: c0022d00 00040204 00000000 00090240
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0110b054:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0110b06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
0110b088:			0000: c0022d00 00040081 00000000 01000100
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 128.000000
				PA_CL_VPORT_XOFFSET: 128.000000
				PA_CL_VPORT_YSCALE: -128.000000
				PA_CL_VPORT_YOFFSET: 128.000000
				PA_CL_VPORT_ZSCALE: 0.500000
				PA_CL_VPORT_ZOFFSET: 0.500000
0110b098:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0110b0c0:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
0110b0b8:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
0110b0d8:			0020: 3f000000 00000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
					04: 13480000 40252fc8 00000008	      FETCH:	VERTEX	R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 00038000 00000000 c2000000	      ALU:	MAXv	export0.xy__ = R0, R0
					    0000 0000 0000            	NOP
0110b0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0110b100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
0110b120:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0110b140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0110b160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0110b17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0110b188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110b19c:				0.000000 0.000000 0.000000 0.000000
0110b194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0110b1ac:			0000: c0012d00 00040202 00001c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0110b1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110b1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0110b1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
				filter min/mag: point/point
				swizzle: xyzw
				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
				mipaddr=01240000 (flags=200)
0110b1e8:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0110b208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0110b214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110b21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0110b230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 103
				:0,0,107,103
0110b24c:			0000: 0000057f 00000067
t3			opcode: CP_NOP (10) (2 dwords)
0110b254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (5 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
				{ NUM_INDICES = 18011832 }
				{ INDX_BASE = 0xc }
			draw:          0
			prim_type:     DI_PT_TRILIST (4)
			source_select: DI_SRC_SEL_DMA (0)
			num_indices:   18011832
			draw[17] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	0000006b			CP_SCRATCH_REG6: 107
			:0,0,107,103
!+	00000067			CP_SCRATCH_REG7: 103
			:0,0,107,103
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000100			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
!+	0108a205			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	01000100			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	01000100			PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	43000000			PA_CL_VPORT_XSCALE: 128.000000
!+	43000000			PA_CL_VPORT_XOFFSET: 128.000000
!+	c3000000			PA_CL_VPORT_YSCALE: -128.000000
!+	43000000			PA_CL_VPORT_YOFFSET: 128.000000
!+	3f000000			PA_CL_VPORT_ZSCALE: 0.500000
!+	3f000000			PA_CL_VPORT_ZOFFSET: 0.500000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00001c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090240			PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00080008			PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
!+	00080008			PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
!+	00000008			PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0110b25c:			0000: c0032200 00000000 00060004 0112d6b8 0000000c
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 104
				:0,0,107,104
0110b270:			0000: 0000057f 00000068
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0110b278:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2d0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2d8:			0000: c0004600 00000006
0110a1d8:		0000: c0013700 0110b000 000000b8
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1264
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122f000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122f008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122f014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122f020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122f02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122f034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122f040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122f050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122f05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122f068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122f078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122f084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122f090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122f09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122f0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122f0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122f0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122f0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122f0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122f100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122f11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122f12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122f15c:			2.000000 0.750000 0.375000 0.250000
0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122f190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122f19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
0122f1a8:		0000: c0012d00 00040001 01266245
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
0122f1b4:		0000: c0022d00 0004000e 80000000 00200010
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 113
			:0,0,113,104
0122f1d0:		0000: 0000057e 00000071
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d6c7 00100000 0112d6c7 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
0122e088:			0000: c0022d00 00040081 00000000 00200010
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 8.000000
				PA_CL_VPORT_XOFFSET: 8.000000
				PA_CL_VPORT_YSCALE: 16.000000
				PA_CL_VPORT_YOFFSET: 16.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 41000000 41000000 41800000 41800000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				8.000000 16.000000 0.000000 0.000000 8.000000 16.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 41000000 41800000 00000000 00000000 41000000 41800000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: zyxw
				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 109
				:0,0,113,109
0122e24c:			0000: 0000057f 0000006d
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[18] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000071			CP_SCRATCH_REG6: 113
			:0,0,113,109
!+	0000006d			CP_SCRATCH_REG7: 109
			:0,0,113,109
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	01266245			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00200010			PA_SC_SCREEN_SCISSOR_BR: { X = 16 | Y = 32 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00200010			PA_SC_WINDOW_SCISSOR_BR: { X = 16 | Y = 32 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	41000000			PA_CL_VPORT_XSCALE: 8.000000
!+	41000000			PA_CL_VPORT_XOFFSET: 8.000000
!+	41800000			PA_CL_VPORT_YSCALE: 16.000000
!+	41800000			PA_CL_VPORT_YOFFSET: 16.000000
!+	00000000			PA_CL_VPORT_ZSCALE: 0.000000
!+	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
!+	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
!+	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 110
				:0,0,113,110
0122e268:			0000: 0000057f 0000006e
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122f1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1265
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0110c000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0110c008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0110c014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0110c020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0110c02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0110c034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0110c040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110c048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0110c050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0110c05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0110c068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0110c078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0110c084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0110c090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0110c09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0110c0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110c0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0110c0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0110c0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0110c0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110c0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0110c0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110c100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110c108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0110c11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110c124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0110c12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0110c13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0110c15c:			2.000000 0.750000 0.375000 0.250000
0110c134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0110c154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110c16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0110c178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0110c190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
0110c19c:		0000: c0012d00 00040000 00000100
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
0110c1a8:		0000: c0012d00 00040001 0108a205
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
0110c1b4:		0000: c0022d00 0004000e 80000000 01000100
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110c1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 119
			:0,0,119,110
0110c1d0:		0000: 0000057e 00000077
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110b000
		ibsize:000000b8
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0110b000:			0000: c0042d00 00010078 0112d747 00100000 0112d787 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0110b018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0110b024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0110b030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0110b044:			0000: c0022d00 00040204 00000000 00090240
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0110b054:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0110b06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
0110b088:			0000: c0022d00 00040081 00000000 01000100
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 128.000000
				PA_CL_VPORT_XOFFSET: 128.000000
				PA_CL_VPORT_YSCALE: -128.000000
				PA_CL_VPORT_YOFFSET: 128.000000
				PA_CL_VPORT_ZSCALE: 0.500000
				PA_CL_VPORT_ZOFFSET: 0.500000
0110b098:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0110b0c0:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
0110b0b8:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
0110b0d8:			0020: 3f000000 00000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
					04: 13480000 40252fc8 00000008	      FETCH:	VERTEX	R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 00038000 00000000 c2000000	      ALU:	MAXv	export0.xy__ = R0, R0
					    0000 0000 0000            	NOP
0110b0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0110b100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
0110b120:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0110b140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0110b160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0110b17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0110b188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110b19c:				0.000000 0.000000 0.000000 0.000000
0110b194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0110b1ac:			0000: c0012d00 00040202 00001c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0110b1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110b1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0110b1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
				filter min/mag: point/point
				swizzle: xyzw
				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
				mipaddr=01240000 (flags=200)
0110b1e8:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0110b208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0110b214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110b21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0110b230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 115
				:0,0,119,115
0110b24c:			0000: 0000057f 00000073
t3			opcode: CP_NOP (10) (2 dwords)
0110b254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (5 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
				{ NUM_INDICES = 18012068 }
				{ INDX_BASE = 0xc }
			draw:          0
			prim_type:     DI_PT_TRILIST (4)
			source_select: DI_SRC_SEL_DMA (0)
			num_indices:   18012068
			draw[19] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000077			CP_SCRATCH_REG6: 119
			:0,0,119,115
!+	00000073			CP_SCRATCH_REG7: 115
			:0,0,119,115
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000100			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
!+	0108a205			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	01000100			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	01000100			PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	43000000			PA_CL_VPORT_XSCALE: 128.000000
!+	43000000			PA_CL_VPORT_XOFFSET: 128.000000
!+	c3000000			PA_CL_VPORT_YSCALE: -128.000000
!+	43000000			PA_CL_VPORT_YOFFSET: 128.000000
!+	3f000000			PA_CL_VPORT_ZSCALE: 0.500000
!+	3f000000			PA_CL_VPORT_ZOFFSET: 0.500000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00001c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090240			PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00080008			PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
!+	00080008			PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
!+	00000008			PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0110b25c:			0000: c0032200 00000000 00060004 0112d7a4 0000000c
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 116
				:0,0,119,116
0110b270:			0000: 0000057f 00000074
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0110b278:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2d0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2d8:			0000: c0004600 00000006
0110c1d8:		0000: c0013700 0110b000 000000b8
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1266
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122d000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122d008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122d014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122d020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122d02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122d034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122d040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122d050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122d05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122d068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122d078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122d084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122d090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122d09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122d0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122d0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122d0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122d0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122d0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122d100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122d108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122d11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122d124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122d12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122d13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122d15c:			2.000000 0.750000 0.375000 0.250000
0122d134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122d154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122d16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122d178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122d190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122d19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
0122d1a8:		0000: c0012d00 00040001 01266245
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
0122d1b4:		0000: c0022d00 0004000e 80000000 00100008
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122d1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 125
			:0,0,125,116
0122d1d0:		0000: 0000057e 0000007d
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d7b3 00100000 0112d7b3 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
0122e088:			0000: c0022d00 00040081 00000000 00100008
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 4.000000
				PA_CL_VPORT_XOFFSET: 4.000000
				PA_CL_VPORT_YSCALE: 8.000000
				PA_CL_VPORT_YOFFSET: 8.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 40800000 40800000 41000000 41000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				4.000000 8.000000 0.000000 0.000000 4.000000 8.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 40800000 41000000 00000000 00000000 40800000 41000000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: zyxw
				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 121
				:0,0,125,121
0122e24c:			0000: 0000057f 00000079
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[20] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	0000007d			CP_SCRATCH_REG6: 125
			:0,0,125,121
!+	00000079			CP_SCRATCH_REG7: 121
			:0,0,125,121
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	01266245			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00100008			PA_SC_SCREEN_SCISSOR_BR: { X = 8 | Y = 16 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00100008			PA_SC_WINDOW_SCISSOR_BR: { X = 8 | Y = 16 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	40800000			PA_CL_VPORT_XSCALE: 4.000000
!+	40800000			PA_CL_VPORT_XOFFSET: 4.000000
!+	41000000			PA_CL_VPORT_YSCALE: 8.000000
!+	41000000			PA_CL_VPORT_YOFFSET: 8.000000
!+	00000000			PA_CL_VPORT_ZSCALE: 0.000000
!+	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
!+	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
!+	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 122
				:0,0,125,122
0122e268:			0000: 0000057f 0000007a
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122d1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1267
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0110a000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0110a008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0110a014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0110a020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0110a02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0110a034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0110a040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110a048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0110a050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0110a05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0110a068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0110a078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0110a084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0110a090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0110a09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0110a0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110a0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0110a0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0110a0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0110a0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110a0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0110a0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0110a100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110a108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0110a11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0110a124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0110a12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0110a13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0110a15c:			2.000000 0.750000 0.375000 0.250000
0110a134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0110a154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110a16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0110a178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0110a190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
0110a19c:		0000: c0012d00 00040000 00000100
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
0110a1a8:		0000: c0012d00 00040001 0108a205
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
0110a1b4:		0000: c0022d00 0004000e 80000000 01000100
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0110a1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 131
			:0,0,131,122
0110a1d0:		0000: 0000057e 00000083
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0110b000
		ibsize:000000b8
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0110b000:			0000: c0042d00 00010078 0112d833 00100000 0112d873 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0110b018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0110b024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0110b030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0110b044:			0000: c0022d00 00040204 00000000 00090240
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
				PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0110b054:			0000: c0042d00 00040280 00080008 00080008 00000008 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0110b06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
0110b088:			0000: c0022d00 00040081 00000000 01000100
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 128.000000
				PA_CL_VPORT_XOFFSET: 128.000000
				PA_CL_VPORT_YSCALE: -128.000000
				PA_CL_VPORT_YOFFSET: 128.000000
				PA_CL_VPORT_ZSCALE: 0.500000
				PA_CL_VPORT_ZOFFSET: 0.500000
0110b098:			0000: c0062d00 0004010f 43000000 43000000 c3000000 43000000 3f000000 3f000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0110b0c0:				128.000000 128.000000 0.500000 0.000000 128.000000 -128.000000 0.500000 0.000000
0110b0b8:			0000: c0082d00 00000184 43000000 43000000 3f000000 00000000 43000000 c3000000
0110b0d8:			0020: 3f000000 00000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000010	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(16) CONST(20, 0)
					04: 13480000 40252fc8 00000008	      FETCH:	VERTEX	R0.xy__ = R0.x FMT_32_32_FLOAT UNSIGNED STRIDE(8) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 00038000 00000000 c2000000	      ALU:	MAXv	export0.xy__ = R0, R0
					    0000 0000 0000            	NOP
0110b0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0110b100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000010 13480000
0110b120:			0040: 40252fc8 00000008 000f803e 00000000 c2010100 00038000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0110b140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0110b160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0110b17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0110b188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0110b19c:				0.000000 0.000000 0.000000 0.000000
0110b194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0110b1ac:			0000: c0012d00 00040202 00001c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0110b1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0110b1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0110b1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/wrap
				filter min/mag: point/point
				swizzle: xyzw
				addr=01230000 (flags=820), size=64x128, pitch=16448, format=FMT_1_REVERSE
				mipaddr=01240000 (flags=200)
0110b1e8:			0000: c0062d00 00010000 80804800 01230820 000fe03f 00000d11 000001c0 01240200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0110b208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0110b214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0110b21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0110b230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 127
				:0,0,131,127
0110b24c:			0000: 0000057f 0000007f
t3			opcode: CP_NOP (10) (2 dwords)
0110b254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (5 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x60000 }
				{ NUM_INDICES = 18012304 }
				{ INDX_BASE = 0xc }
			draw:          0
			prim_type:     DI_PT_TRILIST (4)
			source_select: DI_SRC_SEL_DMA (0)
			num_indices:   18012304
			draw[21] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000083			CP_SCRATCH_REG6: 131
			:0,0,131,127
!+	0000007f			CP_SCRATCH_REG7: 127
			:0,0,131,127
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000100			RB_SURFACE_INFO: { SURFACE_PITCH = 256 | MSAA_SAMPLES = 0 }
!+	0108a205			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | ENDIAN = 0 | SWAP = 1 | BASE = 0x108a000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	01000100			PA_SC_SCREEN_SCISSOR_BR: { X = 256 | Y = 256 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	01000100			PA_SC_WINDOW_SCISSOR_BR: { X = 256 | Y = 256 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	43000000			PA_CL_VPORT_XSCALE: 128.000000
!+	43000000			PA_CL_VPORT_XOFFSET: 128.000000
!+	c3000000			PA_CL_VPORT_YSCALE: -128.000000
!+	43000000			PA_CL_VPORT_YOFFSET: 128.000000
!+	3f000000			PA_CL_VPORT_ZSCALE: 0.500000
!+	3f000000			PA_CL_VPORT_ZOFFSET: 0.500000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00001c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_ALWAYS | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090240			PA_SU_SC_MODE_CNTL: { POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00080008			PA_SU_POINT_SIZE: { HEIGHT = 0.500000 | WIDTH = 0.500000 }
!+	00080008			PA_SU_POINT_MINMAX: { MIN = 0.500000 | MAX = 0.500000 }
!+	00000008			PA_SU_LINE_CNTL: { WIDTH = 0.500000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0110b25c:			0000: c0032200 00000000 00060004 0112d890 0000000c
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 128
				:0,0,131,128
0110b270:			0000: 0000057f 00000080
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0110b278:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2d0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0110b2d8:			0000: c0004600 00000006
0110a1d8:		0000: c0013700 0110b000 000000b8
t2		nop
############################################################
vertices: 0
cmd: deqp-gles2/185: fence=1268
############################################################
cmdstream: 124 dwords
t0		write RB_BC_CONTROL (0f01)
			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
0122f000:		0000: 00000f01 1c004046
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
0122f008:		0000: c0012d00 00040293 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
0122f014:		0000: c0012d00 00040316 00000002
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
0122f020:		0000: c0012d00 00040317 00000002
t0		write CP_PERFMON_CNTL (0444)
			CP_PERFMON_CNTL: 0
0122f02c:		0000: 00000444 00000000
t0		write RBBM_PM_OVERRIDE1 (039c)
			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
			RBBM_PM_OVERRIDE2: 0xfff
0122f034:		0000: 0001039c ffffffff 00000fff
t0		write TP0_CHICKEN (0e1e)
			TP0_CHICKEN: 0x2
0122f040:		0000: 00000e1e 00000002
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f048:		0000: c0003b00 00007fff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
0122f050:		0000: c0012d00 00040307 00100020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
0122f05c:		0000: c0012d00 00040308 000e0120
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			VGT_MAX_VTX_INDX: 0xffffffff
			VGT_MIN_VTX_INDX: 0
0122f068:		0000: c0022d00 00040100 ffffffff 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			VGT_INDX_OFFSET: 0
0122f078:		0000: c0012d00 00040102 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_CONTEXT_MISC: { SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 0 }
0122f084:		0000: c0012d00 00040181 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
0122f090:		0000: c0012d00 00040182 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
0122f09c:		0000: c0012d00 00040301 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
0122f0a8:		0000: c0012d00 00040300 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f0b4:		0000: c0012d00 00040080 00000000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
0122f0c0:		0000: c0012d00 00040208 00000004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SAMPLE_POS: 0x88888888
0122f0cc:		0000: c0012d00 0004020a 88888888
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_DEST_MASK: 0xffffffff
0122f0d8:		0000: c0012d00 00040326 ffffffff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f0e4:		0000: c0012d00 0004031b 0003c000
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
0122f0f0:		0000: c0022d00 00040183 00000000 00000000
t3		opcode: CP_SET_DRAW_INIT_FLAGS (4b) (2 dwords)
0122f100:		0000: c0004b00 00000000
t3		opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122f108:		0000: c0035200 000005d0 00000000 5f601000 00000001
t0		write SQ_INST_STORE_MANAGMENT (0d02)
			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
0122f11c:		0000: 00000d02 00000180
t3		opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
0122f124:		0000: c0003b00 00000300
t3		opcode: CP_SET_SHADER_BASES (4a) (2 dwords)
0122f12c:		0000: c0004a00 80000180
t3		opcode: CP_SET_CONSTANT (2d) (14 dwords)
0122f13c:			0.000000 0.000000 0.000000 0.000000 20000.000000 1.000000 0.500000 0.000000
0122f15c:			2.000000 0.750000 0.375000 0.250000
0122f134:		0000: c00c2d00 00000000 00000000 00000000 00000000 00000000 469c4000 3f800000
0122f154:		0020: 3f000000 00000000 40000000 3f400000 3ec00000 3e800000
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122f16c:		0000: c0012d00 00040104 0000000f
t3		opcode: CP_SET_CONSTANT (2d) (6 dwords)
			RB_BLEND_RED: 0
			RB_BLEND_GREEN: 0
			RB_BLEND_BLUE: 0
			RB_BLEND_ALPHA: 0xff
0122f178:		0000: c0042d00 00040105 00000000 00000000 00000000 000000ff
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
0122f190:		0000: c0012d00 00040206 0000043f
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
0122f19c:		0000: c0012d00 00040000 00000020
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
0122f1a8:		0000: c0012d00 00040001 01266245
t3		opcode: CP_SET_CONSTANT (2d) (4 dwords)
			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
			PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
0122f1b4:		0000: c0022d00 0004000e 80000000 00080004
t3		opcode: CP_SET_CONSTANT (2d) (3 dwords)
			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
0122f1c4:		0000: c0012d00 00040080 00000000
t0		write CP_SCRATCH_REG6 (057e)
			CP_SCRATCH_REG6: 137
			:0,0,137,128
0122f1d0:		0000: 0000057e 00000089
t3		opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
		ibaddr:0122e000
		ibsize:000000b6
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
			set shader const 0078
0122e000:			0000: c0042d00 00010078 0112d89f 00100000 0112d89f 00100000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				PA_SC_AA_MASK: 0xffff
0122e018:			0000: c0012d00 00040312 0000ffff
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
0122e024:			0000: c0012d00 00040200 00000000
t3			opcode: CP_SET_CONSTANT (2d) (5 dwords)
				RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
				RB_ALPHA_REF: 0
0122e030:			0000: c0032d00 0004010c 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
				PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
0122e044:			0000: c0022d00 00040204 00000000 00090244
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
				PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
				PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
				PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
0122e054:			0000: c0042d00 00040280 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (7 dwords)
				PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
				PA_CL_GB_VERT_CLIP_ADJ: 1.000000
				PA_CL_GB_VERT_DISC_ADJ: 1.000000
				PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
				PA_CL_GB_HORZ_DISC_ADJ: 1.000000
0122e06c:			0000: c0052d00 00040302 00000001 3f800000 3f800000 3f800000 3f800000
t3			opcode: CP_SET_CONSTANT (2d) (4 dwords)
				PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
				PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
0122e088:			0000: c0022d00 00040081 00000000 00080004
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
				PA_CL_VPORT_XSCALE: 2.000000
				PA_CL_VPORT_XOFFSET: 2.000000
				PA_CL_VPORT_YSCALE: 4.000000
				PA_CL_VPORT_YOFFSET: 4.000000
				PA_CL_VPORT_ZSCALE: 0.000000
				PA_CL_VPORT_ZOFFSET: 0.000000
0122e098:			0000: c0062d00 0004010f 40000000 40000000 40800000 40800000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (10 dwords)
0122e0c0:				2.000000 4.000000 0.000000 0.000000 2.000000 4.000000 0.000000 0.000000
0122e0b8:			0000: c0082d00 00000184 40000000 40800000 00000000 00000000 40000000 40800000
*
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (24 dwords)
			vertex shader, start=0000, size=0015
					    2003 0007 1000            	EXEC ADDR(0x3) CNT(0x2)
					03: 19481000 00262688 00000020	   (S)FETCH:	VERTEX	R1.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) CONST(20, 0)
					04: 13480000 40262688 00001020	      FETCH:	VERTEX	R0.xyzw = R0.x FMT_32_32_32_32_FLOAT UNSIGNED STRIDE(32) OFFSET(16) CONST(20, 1)
					    0000 0000 c200            	ALLOC POSITION SIZE(0x0)
					    1005 0002 1000            	EXEC ADDR(0x5) CNT(0x1)
					05: 000f803e 00000000 c2010100	   (S)ALU:	MAXv	export62 = R1, R1	; gl_Position
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1006 0000 2000            	EXEC_END ADDR(0x6) CNT(0x1)
					06: 000f8000 00000000 c2000000	      ALU:	MAXv	export0 = R0, R0
					    0000 0000 0000            	NOP
0122e0e0:			0000: c0162b00 00000000 00000015 00072003 00001000 c2000000 00021005 00001000
0122e100:			0020: c4000000 00001006 00002000 00000000 19481000 00262688 00000020 13480000
0122e120:			0040: 40262688 00001020 000f803e 00000000 c2010100 000f8000 00000000 c2000000
t3			opcode: CP_IM_LOAD_IMMEDIATE (2b) (15 dwords)
			fragment shader, start=0000, size=000c
					    1002 0003 1000            	EXEC ADDR(0x2) CNT(0x1)
					02: 90000001 1ffff688 00000002	   (S)FETCH:	SAMPLE	R0.xyzw = R0.xyz CONST(0) LOCATION(CENTER)
					    0000 0000 c400            	ALLOC PARAM/PIXEL SIZE(0x0)
					    1003 0002 2000            	EXEC_END ADDR(0x3) CNT(0x1)
					03: 000f8000 00000000 c2000000	   (S)ALU:	MAXv	export0 = R0, R0	; gl_FragColor
					    0000 0000 0000            	NOP
0122e140:			0000: c00d2b00 00000001 0000000c 00031002 00001000 c4000000 00021003 00002000
0122e160:			0020: 00000000 90000001 1ffff688 00000002 000f8000 00000000 c2000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
0122e17c:			0000: c0012d00 00040181 00000106
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
0122e188:			0000: c0012d00 00040180 10030002
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
0122e19c:				0.000000 0.000000 0.000000 0.000000
0122e194:			0000: c0042d00 00000080 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
0122e1ac:			0000: c0012d00 00040202 00000c20
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
0122e1b8:			0000: c0012d00 00040201 00000000
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
0122e1c4:			0000: c0012d00 00040104 0000000f
t3			opcode: CP_SET_CONSTANT (2d) (6 dwords)
				RB_BLEND_RED: 0
				RB_BLEND_GREEN: 0
				RB_BLEND_BLUE: 0
				RB_BLEND_ALPHA: 0
0122e1d0:			0000: c0042d00 00040105 00000000 00000000 00000000 00000000
t3			opcode: CP_SET_CONSTANT (2d) (8 dwords)
			set texture const 0000
				clamp x/y/z: clamp-last-texel/clamp-last-texel/clamp-last-texel
				filter min/mag: point/point
				swizzle: zyxw
				addr=0108a000 (flags=806), size=256x256, pitch=16640, format=FMT_8_8_8_8
				mipaddr=00000000 (flags=200)
0122e1e8:			0000: c0062d00 00010000 82024800 0108a806 001fe0ff 00000c14 00000000 00000200
t3			opcode: CP_SET_CONSTANT (2d) (3 dwords)
				VGT_INDX_OFFSET: 0
0122e208:			0000: c0012d00 00040102 00000000
t0			write TC_CNTL_STATUS (0e00)
				TC_CNTL_STATUS: { L2_INVALIDATE }
0122e214:			0000: 00000e00 00000001
t3			opcode: CP_WAIT_REG_EQ (52) (5 dwords)
0122e21c:			0000: c0035200 000005d0 00000000 00001000 00000001
t3			opcode: CP_DRAW_INDX_BIN (34) (7 dwords)
0122e230:			0000: c0053400 00000000 0003c004 00000000 00000003 01009040 00000006
t0			write CP_SCRATCH_REG7 (057f)
				CP_SCRATCH_REG7: 133
				:0,0,137,133
0122e24c:			0000: 0000057f 00000085
t3			opcode: CP_NOP (10) (2 dwords)
0122e254:			0000: c0001000 00000000
t3			opcode: CP_DRAW_INDX (22) (3 dwords)
				{ VIZ_QUERY = 0 }
				{ PRIM_TYPE = DI_PT_TRIFAN | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | NUM_INSTANCES = 0 | 0x40000 }
			draw:          0
			prim_type:     DI_PT_TRIFAN (5)
			source_select: DI_SRC_SEL_AUTO_INDEX (2)
			num_indices:   1407
			draw[22] register values
 +	ffffffff			RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
 +	00000fff			RBBM_PM_OVERRIDE2: 0xfff
 +	00000000			CP_PERFMON_CNTL: 0
!+	00000089			CP_SCRATCH_REG6: 137
			:0,0,137,133
!+	00000085			CP_SCRATCH_REG7: 133
			:0,0,137,133
 +	00000180			SQ_INST_STORE_MANAGMENT: { INST_BASE_PIX = 384 | INST_BASE_VTX = 0 }
 +	00000001			TC_CNTL_STATUS: { L2_INVALIDATE }
 +	00000002			TP0_CHICKEN: 0x2
 +	1c004046			RB_BC_CONTROL: { ACCUM_TIMEOUT_SELECT = 3 | DISABLE_LZ_NULL_ZCMD_DROP | AZ_THROTTLE_COUNT = 0 | ENABLE_CRC_UPDATE | ACCUM_ALLOC_MASK = 0 | ACCUM_DATA_FIFO_LIMIT = 8 | MEM_EXPORT_TIMEOUT_SELECT = 3 }
!+	00000020			RB_SURFACE_INFO: { SURFACE_PITCH = 32 | MSAA_SAMPLES = 0 }
!+	01266245			RB_COLOR_INFO: { FORMAT = COLORX_8_8_8_8 | ROUND_MODE = 0 | LINEAR | ENDIAN = 0 | SWAP = 1 | BASE = 0x1266000 }
 +	80000000			PA_SC_SCREEN_SCISSOR_TL: { WINDOW_OFFSET_DISABLE | X = 0 | Y = 0 }
!+	00080004			PA_SC_SCREEN_SCISSOR_BR: { X = 4 | Y = 8 }
 +	00000000			PA_SC_WINDOW_OFFSET: { X = 0 | Y = 0 }
 +	00000000			PA_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+	00080004			PA_SC_WINDOW_SCISSOR_BR: { X = 4 | Y = 8 }
 +	ffffffff			VGT_MAX_VTX_INDX: 0xffffffff
 +	00000000			VGT_MIN_VTX_INDX: 0
 +	00000000			VGT_INDX_OFFSET: 0
 +	0000000f			RB_COLOR_MASK: { WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	00000000			RB_BLEND_RED: 0
 +	00000000			RB_BLEND_GREEN: 0
 +	00000000			RB_BLEND_BLUE: 0
 +	00000000			RB_BLEND_ALPHA: 0
 +	00000000			RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
 +	00000000			RB_ALPHA_REF: 0
!+	40000000			PA_CL_VPORT_XSCALE: 2.000000
!+	40000000			PA_CL_VPORT_XOFFSET: 2.000000
!+	40800000			PA_CL_VPORT_YSCALE: 4.000000
!+	40800000			PA_CL_VPORT_YOFFSET: 4.000000
!+	00000000			PA_CL_VPORT_ZSCALE: 0.000000
!+	00000000			PA_CL_VPORT_ZOFFSET: 0.000000
 +	10030002			SQ_PROGRAM_CNTL: { VS_REGS = 2 | PS_REGS = 0 | VS_RESOURCE | PS_RESOURCE | VS_EXPORT_COUNT = 0 | VS_EXPORT_MODE = POSITION_1_VECTOR | PS_EXPORT_MODE = 2 }
 +	00000106			SQ_CONTEXT_MISC: { SC_OUTPUT_SCREEN_XY | SC_SAMPLE_CNTL = CENTERS_ONLY | PARAM_GEN_POS = 1 }
 +	ffffffff			SQ_INTERPOLATOR_CNTL: { PARAM_SHADE = 65535 | SAMPLING_PATTERN = 65535 }
 +	00000000			SQ_WRAPPING_0: { PARAM_WRAP_0 = 0 | PARAM_WRAP_1 = 0 | PARAM_WRAP_2 = 0 | PARAM_WRAP_3 = 0 | PARAM_WRAP_4 = 0 | PARAM_WRAP_5 = 0 | PARAM_WRAP_6 = 0 | PARAM_WRAP_7 = 0 }
 +	00000000			SQ_WRAPPING_1: { PARAM_WRAP_8 = 0 | PARAM_WRAP_9 = 0 | PARAM_WRAP_10 = 0 | PARAM_WRAP_11 = 0 | PARAM_WRAP_12 = 0 | PARAM_WRAP_13 = 0 | PARAM_WRAP_14 = 0 | PARAM_WRAP_15 = 0 }
 +	00000000			RB_DEPTHCONTROL: { ZFUNC = FUNC_NEVER | STENCILFUNC = FUNC_NEVER | STENCILFAIL = STENCIL_KEEP | STENCILZPASS = STENCIL_KEEP | STENCILZFAIL = STENCIL_KEEP | STENCILFUNC_BF = FUNC_NEVER | STENCILFAIL_BF = STENCIL_KEEP | STENCILZPASS_BF = STENCIL_KEEP | STENCILZFAIL_BF = STENCIL_KEEP }
 +	00000000			RB_BLEND_CONTROL: { COLOR_SRCBLEND = FACTOR_ZERO | COLOR_COMB_FCN = BLEND2_DST_PLUS_SRC | COLOR_DESTBLEND = FACTOR_ZERO | ALPHA_SRCBLEND = FACTOR_ZERO | ALPHA_COMB_FCN = BLEND2_DST_PLUS_SRC | ALPHA_DESTBLEND = FACTOR_ZERO }
!+	00000c20			RB_COLORCONTROL: { ALPHA_FUNC = FUNC_NEVER | BLEND_DISABLE | ROP_CODE = 12 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | ALPHA_TO_MASK_OFFSET0 = 0 | ALPHA_TO_MASK_OFFSET1 = 0 | ALPHA_TO_MASK_OFFSET2 = 0 | ALPHA_TO_MASK_OFFSET3 = 0 }
 +	00000000			PA_CL_CLIP_CNTL: { DX_CLIP_SPACE_DEF = DXCLIP_OPENGL }
!+	00090244			PA_SU_SC_MODE_CNTL: { FACE | POLYMODE = POLY_DISABLED | FRONT_PTYPE = PC_DRAW_TRIANGLES | BACK_PTYPE = PC_DRAW_TRIANGLES | VTX_WINDOW_OFFSET_ENABLE | PROVOKING_VTX_LAST }
 +	0000043f			PA_CL_VTE_CNTL: { VPORT_X_SCALE_ENA | VPORT_X_OFFSET_ENA | VPORT_Y_SCALE_ENA | VPORT_Y_OFFSET_ENA | VPORT_Z_SCALE_ENA | VPORT_Z_OFFSET_ENA | VTX_W0_FMT }
 +	00000004			RB_MODECONTROL: { EDRAM_MODE = COLOR_DEPTH }
 +	88888888			RB_SAMPLE_POS: 0x88888888
!+	00000000			PA_SU_POINT_SIZE: { HEIGHT = 0.000000 | WIDTH = 0.000000 }
!+	00000000			PA_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
!+	00000000			PA_SU_LINE_CNTL: { WIDTH = 0.000000 }
 +	00000000			PA_SC_LINE_STIPPLE: { LINE_PATTERN = 0 | REPEAT_COUNT = 0 | PATTERN_BIT_ORDER = LITTLE | AUTO_RESET_CNTL = NEVER }
 +	00000020			PA_SC_VIZ_QUERY: { VIZ_QUERY_ID = 16 }
 +	00000000			PA_SC_LINE_CNTL: { BRES_CNTL = 0 }
 +	00000000			PA_SC_AA_CONFIG: { MSAA_NUM_SAMPLES = 0 | MAX_SAMPLE_DIST = 0 }
 +	00000001			PA_SU_VTX_CNTL: { PIX_CENTER = PIXCENTER_OGL | ROUND_MODE = TRUNCATE | QUANT_MODE = ONE_SIXTEENTH }
 +	3f800000			PA_CL_GB_VERT_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_VERT_DISC_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_CLIP_ADJ: 1.000000
 +	3f800000			PA_CL_GB_HORZ_DISC_ADJ: 1.000000
 +	00100020			SQ_VS_CONST: { BASE = 32 | SIZE = 256 }
 +	000e0120			SQ_PS_CONST: { BASE = 288 | SIZE = 224 }
 +	0000ffff			PA_SC_AA_MASK: 0xffff
 +	00000002			VGT_VERTEX_REUSE_BLOCK_CNTL: { VTX_REUSE_DEPTH = 2 }
 +	00000002			VGT_OUT_DEALLOC_CNTL: { DEALLOC_DIST = 2 }
 +	0003c000			RB_COPY_DEST_INFO: { DEST_ENDIAN = ENDIAN_NONE | FORMAT = COLORX_4_4_4_4 | SWAP = 0 | DITHER_MODE = DITHER_DISABLE | DITHER_TYPE = DITHER_PIXEL | WRITE_RED | WRITE_GREEN | WRITE_BLUE | WRITE_ALPHA }
 +	ffffffff			RB_COLOR_DEST_MASK: 0xffffffff
0122e25c:			0000: c0012200 00000000 00040085
t0			write CP_SCRATCH_REG7 (057f)
NEEDS WFI: CP_SCRATCH_REG7 (57f)
				CP_SCRATCH_REG7: 134
				:0,0,137,134
0122e268:			0000: 0000057f 00000086
t3			opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
0122e270:			0000: c0002600 00000000
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e278:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e280:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e288:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e290:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e298:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2a8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2b8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c0:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2c8:			0000: c0004600 00000006
t3			opcode: CP_EVENT_WRITE (46) (2 dwords)
				{ EVENT = CACHE_FLUSH }
			event CACHE_FLUSH
0122e2d0:			0000: c0004600 00000006
0122f1d8:		0000: c0013700 0122e000 000000b6
t2		nop
############################################################
vertices: 0
