187 lines
7.2 KiB
C
187 lines
7.2 KiB
C
/**************************************************************************
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*
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* Copyright 2006 VMware, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keithw@vmware.com>
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* Michel Dänzer <daenzer@vmware.com>
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*/
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#include "intel_mipmap_tree.h"
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#include "intel_tex_layout.h"
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#include "intel_context.h"
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#include "main/image.h"
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#include "main/macros.h"
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static unsigned int
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intel_horizontal_texture_alignment_unit(struct intel_context *intel,
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mesa_format format)
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{
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/**
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* From the "Alignment Unit Size" section of various specs, namely:
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* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
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* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
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* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
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* - BSpec (for Ivybridge and slight variations in separate stencil)
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*
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* +----------------------------------------------------------------------+
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* | | alignment unit width ("i") |
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* | Surface Property |-----------------------------|
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* | | 915 | 965 | ILK | SNB | IVB |
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* +----------------------------------------------------------------------+
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* | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
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* | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
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* | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
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* | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
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* | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
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* | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
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* | All Others | 4 | 4 | 4 | 4 | 4 |
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* +----------------------------------------------------------------------+
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*
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* On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
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* "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
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*/
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if (_mesa_is_format_compressed(format)) {
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/* The hardware alignment requirements for compressed textures
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* happen to match the block boundaries.
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*/
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unsigned int i, j;
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_mesa_get_format_block_size(format, &i, &j);
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return i;
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}
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return 4;
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}
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static unsigned int
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intel_vertical_texture_alignment_unit(struct intel_context *intel,
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mesa_format format)
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{
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/**
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* From the "Alignment Unit Size" section of various specs, namely:
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* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
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* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
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* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
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* - BSpec (for Ivybridge and slight variations in separate stencil)
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*
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* +----------------------------------------------------------------------+
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* | | alignment unit height ("j") |
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* | Surface Property |-----------------------------|
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* | | 915 | 965 | ILK | SNB | IVB |
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* +----------------------------------------------------------------------+
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* | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
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* | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
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* | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
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* | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
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* | All Others | 2 | 2 | 2 | 2 | 2 |
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* +----------------------------------------------------------------------+
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*
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* On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
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* "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
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*/
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if (_mesa_is_format_compressed(format))
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return 4;
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return 2;
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}
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void
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intel_get_texture_alignment_unit(struct intel_context *intel,
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mesa_format format,
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unsigned int *w, unsigned int *h)
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{
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*w = intel_horizontal_texture_alignment_unit(intel, format);
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*h = intel_vertical_texture_alignment_unit(intel, format);
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}
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void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
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{
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GLuint level;
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GLuint x = 0;
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GLuint y = 0;
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GLuint width = mt->physical_width0;
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GLuint height = mt->physical_height0;
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GLuint depth = mt->physical_depth0; /* number of array layers. */
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mt->total_width = mt->physical_width0;
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if (mt->compressed) {
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mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
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}
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/* May need to adjust width to accommodate the placement of
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* the 2nd mipmap. This occurs when the alignment
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* constraints of mipmap placement push the right edge of the
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* 2nd mipmap out past the width of its parent.
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*/
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if (mt->first_level != mt->last_level) {
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GLuint mip1_width;
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if (mt->compressed) {
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mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
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ALIGN(minify(mt->physical_width0, 2), mt->align_w);
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} else {
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mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
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minify(mt->physical_width0, 2);
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}
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if (mip1_width > mt->total_width) {
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mt->total_width = mip1_width;
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}
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}
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mt->total_height = 0;
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for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
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GLuint img_height;
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intel_miptree_set_level_info(mt, level, x, y, width,
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height, depth);
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img_height = ALIGN(height, mt->align_h);
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if (mt->compressed)
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img_height /= mt->align_h;
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/* Because the images are packed better, the final offset
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* might not be the maximal one:
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*/
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mt->total_height = MAX2(mt->total_height, y + img_height);
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/* Layout_below: step right after second mipmap.
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*/
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if (level == mt->first_level + 1) {
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x += ALIGN(width, mt->align_w);
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}
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else {
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y += img_height;
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}
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width = minify(width, 1);
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height = minify(height, 1);
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}
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}
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