193 lines
5.7 KiB
C
193 lines
5.7 KiB
C
/**************************************************************************
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*
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* Copyright 2003 VMware, Inc.
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* Copyright 2009 Intel Corporation.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#include "main/glheader.h"
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#include "main/mtypes.h"
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#include "main/condrender.h"
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#include "swrast/swrast.h"
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#include "drivers/common/meta.h"
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#include "intel_context.h"
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#include "intel_blit.h"
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#include "intel_clear.h"
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#include "intel_fbo.h"
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#include "intel_regions.h"
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#define FILE_DEBUG_FLAG DEBUG_BLIT
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static const char *buffer_names[] = {
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[BUFFER_FRONT_LEFT] = "front",
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[BUFFER_BACK_LEFT] = "back",
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[BUFFER_FRONT_RIGHT] = "front right",
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[BUFFER_BACK_RIGHT] = "back right",
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[BUFFER_DEPTH] = "depth",
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[BUFFER_STENCIL] = "stencil",
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[BUFFER_ACCUM] = "accum",
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[BUFFER_COLOR0] = "color0",
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[BUFFER_COLOR1] = "color1",
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[BUFFER_COLOR2] = "color2",
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[BUFFER_COLOR3] = "color3",
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[BUFFER_COLOR4] = "color4",
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[BUFFER_COLOR5] = "color5",
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[BUFFER_COLOR6] = "color6",
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[BUFFER_COLOR7] = "color7",
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};
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static void
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debug_mask(const char *name, GLbitfield mask)
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{
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GLuint i;
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if (unlikely(INTEL_DEBUG & DEBUG_BLIT)) {
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DBG("%s clear:", name);
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for (i = 0; i < BUFFER_COUNT; i++) {
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if (mask & (1 << i))
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DBG(" %s", buffer_names[i]);
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}
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DBG("\n");
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}
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}
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/**
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* Called by ctx->Driver.Clear.
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*/
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static void
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intelClear(struct gl_context *ctx, GLbitfield mask)
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{
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struct intel_context *intel = intel_context(ctx);
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GLbitfield tri_mask = 0;
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GLbitfield blit_mask = 0;
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GLbitfield swrast_mask = 0;
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struct gl_framebuffer *fb = ctx->DrawBuffer;
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struct intel_renderbuffer *irb;
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int i;
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if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
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intel->front_buffer_dirty = true;
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}
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if (0)
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fprintf(stderr, "%s\n", __func__);
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/* Get SW clears out of the way: Anything without an intel_renderbuffer */
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for (i = 0; i < BUFFER_COUNT; i++) {
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if (!(mask & (1 << i)))
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continue;
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irb = intel_get_renderbuffer(fb, i);
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if (unlikely(!irb)) {
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swrast_mask |= (1 << i);
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mask &= ~(1 << i);
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}
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}
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if (unlikely(swrast_mask)) {
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debug_mask("swrast", swrast_mask);
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_swrast_Clear(ctx, swrast_mask);
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}
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/* HW color buffers (front, back, aux, generic FBO, etc) */
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if (GET_COLORMASK(ctx->Color.ColorMask, 0) == 0xf) {
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/* clear all R,G,B,A */
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blit_mask |= (mask & BUFFER_BITS_COLOR);
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}
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else {
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/* glColorMask in effect */
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tri_mask |= (mask & BUFFER_BITS_COLOR);
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}
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/* Make sure we have up to date buffers before we start looking at
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* the tiling bits to determine how to clear. */
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intel_prepare_render(intel);
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/* HW stencil */
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if (mask & BUFFER_BIT_STENCIL) {
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const struct intel_region *stencilRegion
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= intel_get_rb_region(fb, BUFFER_STENCIL);
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if (stencilRegion) {
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/* have hw stencil */
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if (stencilRegion->tiling == I915_TILING_Y ||
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(ctx->Stencil.WriteMask[0] & 0xff) != 0xff) {
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/* We have to use the 3D engine if we're clearing a partial mask
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* of the stencil buffer, or if we're on a 965 which has a tiled
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* depth/stencil buffer in a layout we can't blit to.
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*/
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tri_mask |= BUFFER_BIT_STENCIL;
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}
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else {
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/* clearing all stencil bits, use blitting */
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blit_mask |= BUFFER_BIT_STENCIL;
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}
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}
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}
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/* HW depth */
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if (mask & BUFFER_BIT_DEPTH) {
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const struct intel_region *irb = intel_get_rb_region(fb, BUFFER_DEPTH);
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/* clear depth with whatever method is used for stencil (see above) */
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if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
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tri_mask |= BUFFER_BIT_DEPTH;
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else
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blit_mask |= BUFFER_BIT_DEPTH;
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}
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/* If we're doing a tri pass for depth/stencil, include a likely color
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* buffer with it.
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*/
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if (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) {
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int color_bit = ffs(mask & BUFFER_BITS_COLOR);
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if (color_bit != 0) {
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tri_mask |= blit_mask & (1 << (color_bit - 1));
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blit_mask &= ~(1 << (color_bit - 1));
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}
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}
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/* Anything left, just use tris */
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tri_mask |= mask & ~blit_mask;
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if (blit_mask) {
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debug_mask("blit", blit_mask);
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tri_mask |= intelClearWithBlit(ctx, blit_mask);
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}
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if (tri_mask) {
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debug_mask("tri", tri_mask);
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if (!ctx->Extensions.ARB_fragment_shader)
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_mesa_meta_Clear(&intel->ctx, tri_mask);
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else
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_mesa_meta_glsl_Clear(&intel->ctx, tri_mask);
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}
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}
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void
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intelInitClearFuncs(struct dd_function_table *functions)
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{
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functions->Clear = intelClear;
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}
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