859 lines
25 KiB
C
859 lines
25 KiB
C
/**************************************************************************
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*
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* Copyright 2003 VMware, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#include "main/glheader.h"
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#include "main/mtypes.h"
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#include "main/macros.h"
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#include "main/renderbuffer.h"
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#include "main/framebuffer.h"
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#include "tnl/tnl.h"
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#include "tnl/t_context.h"
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#include "tnl/t_vertex.h"
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#include "swrast_setup/swrast_setup.h"
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#include "intel_batchbuffer.h"
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#include "intel_mipmap_tree.h"
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#include "intel_regions.h"
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#include "intel_tris.h"
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#include "intel_fbo.h"
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#include "intel_buffers.h"
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#include "i915_reg.h"
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#include "i915_context.h"
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static void
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i915_render_prevalidate(struct intel_context *intel)
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{
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struct i915_context *i915 = i915_context(&intel->ctx);
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i915ValidateFragmentProgram(i915);
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}
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static void
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i915_render_start(struct intel_context *intel)
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{
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intel_prepare_render(intel);
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}
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static void
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i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
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{
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struct i915_context *i915 = i915_context(&intel->ctx);
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GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
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st1 &= ~ST1_ENABLE;
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switch (rprim) {
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case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
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case GL_TRIANGLES:
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if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
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st1 |= ST1_ENABLE;
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break;
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case GL_LINES:
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case GL_POINTS:
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default:
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break;
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}
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i915->intel.reduced_primitive = rprim;
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if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
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INTEL_FIREVERTICES(intel);
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I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
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i915->state.Stipple[I915_STPREG_ST1] = st1;
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}
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}
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/* Pull apart the vertex format registers and figure out how large a
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* vertex is supposed to be.
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*/
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static bool
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i915_check_vertex_size(struct intel_context *intel, GLuint expected)
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{
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struct i915_context *i915 = i915_context(&intel->ctx);
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int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
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int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
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int i, sz = 0;
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switch (lis4 & S4_VFMT_XYZW_MASK) {
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case S4_VFMT_XY:
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sz = 2;
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break;
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case S4_VFMT_XYZ:
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sz = 3;
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break;
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case S4_VFMT_XYW:
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sz = 3;
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break;
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case S4_VFMT_XYZW:
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sz = 4;
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break;
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default:
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fprintf(stderr, "no xyzw specified\n");
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return 0;
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}
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if (lis4 & S4_VFMT_SPEC_FOG)
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sz++;
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if (lis4 & S4_VFMT_COLOR)
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sz++;
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if (lis4 & S4_VFMT_DEPTH_OFFSET)
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sz++;
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if (lis4 & S4_VFMT_POINT_WIDTH)
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sz++;
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if (lis4 & S4_VFMT_FOG_PARAM)
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sz++;
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for (i = 0; i < 8; i++) {
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switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
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case TEXCOORDFMT_2D:
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sz += 2;
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break;
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case TEXCOORDFMT_3D:
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sz += 3;
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break;
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case TEXCOORDFMT_4D:
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sz += 4;
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break;
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case TEXCOORDFMT_1D:
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sz += 1;
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break;
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case TEXCOORDFMT_2D_16:
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sz += 1;
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break;
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case TEXCOORDFMT_4D_16:
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sz += 2;
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break;
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case TEXCOORDFMT_NOT_PRESENT:
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break;
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default:
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fprintf(stderr, "bad texcoord fmt %d\n", i);
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return false;
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}
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lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
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}
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if (sz != expected)
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fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
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return sz == expected;
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}
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static void
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i915_emit_invarient_state(struct intel_context *intel)
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{
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BATCH_LOCALS;
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BEGIN_BATCH(15);
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OUT_BATCH(_3DSTATE_AA_CMD |
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AA_LINE_ECAAR_WIDTH_ENABLE |
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AA_LINE_ECAAR_WIDTH_1_0 |
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AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
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OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
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OUT_BATCH(0);
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OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
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OUT_BATCH(0);
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OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
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OUT_BATCH(0);
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/* Don't support texture crossbar yet */
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OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
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CSB_TCB(0, 0) |
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CSB_TCB(1, 1) |
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CSB_TCB(2, 2) |
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CSB_TCB(3, 3) |
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CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
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OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* XXX: Use this */
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OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
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OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
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OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
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OUT_BATCH(0);
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ADVANCE_BATCH();
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}
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#define emit(intel, state, size ) \
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intel_batchbuffer_data(intel, state, size)
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static GLuint
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get_dirty(struct i915_hw_state *state)
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{
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GLuint dirty;
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/* Workaround the multitex hang - if one texture unit state is
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* modified, emit all texture units.
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*/
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dirty = state->active & ~state->emitted;
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if (dirty & I915_UPLOAD_TEX_ALL)
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state->emitted &= ~I915_UPLOAD_TEX_ALL;
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dirty = state->active & ~state->emitted;
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return dirty;
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}
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static GLuint
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get_state_size(struct i915_hw_state *state)
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{
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GLuint dirty = get_dirty(state);
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GLuint i;
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GLuint sz = 0;
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if (dirty & I915_UPLOAD_INVARIENT)
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sz += 30 * 4;
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if (dirty & I915_UPLOAD_RASTER_RULES)
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sz += sizeof(state->RasterRules);
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if (dirty & I915_UPLOAD_CTX)
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sz += sizeof(state->Ctx);
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if (dirty & I915_UPLOAD_BLEND)
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sz += sizeof(state->Blend);
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if (dirty & I915_UPLOAD_BUFFERS)
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sz += sizeof(state->Buffer);
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if (dirty & I915_UPLOAD_STIPPLE)
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sz += sizeof(state->Stipple);
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if (dirty & I915_UPLOAD_TEX_ALL) {
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int nr = 0;
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for (i = 0; i < I915_TEX_UNITS; i++)
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if (dirty & I915_UPLOAD_TEX(i))
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nr++;
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sz += (2 + nr * 3) * sizeof(GLuint) * 2;
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}
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if (dirty & I915_UPLOAD_CONSTANTS)
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sz += state->ConstantSize * sizeof(GLuint);
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if (dirty & I915_UPLOAD_PROGRAM)
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sz += state->ProgramSize * sizeof(GLuint);
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return sz;
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}
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/* Push the state into the sarea and/or texture memory.
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*/
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static void
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i915_emit_state(struct intel_context *intel)
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{
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struct i915_context *i915 = i915_context(&intel->ctx);
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struct i915_hw_state *state = &i915->state;
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int i, count, aper_count;
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GLuint dirty;
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drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
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GET_CURRENT_CONTEXT(ctx);
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BATCH_LOCALS;
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/* We don't hold the lock at this point, so want to make sure that
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* there won't be a buffer wrap between the state emits and the primitive
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* emit header.
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*
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* It might be better to talk about explicit places where
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* scheduling is allowed, rather than assume that it is whenever a
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* batchbuffer fills up.
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*/
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intel_batchbuffer_require_space(intel,
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get_state_size(state) +
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INTEL_PRIM_EMIT_SIZE);
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count = 0;
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again:
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if (intel->batch.bo == NULL) {
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_mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
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assert(0);
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}
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aper_count = 0;
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dirty = get_dirty(state);
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aper_array[aper_count++] = intel->batch.bo;
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if (dirty & I915_UPLOAD_BUFFERS) {
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if (state->draw_region)
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aper_array[aper_count++] = state->draw_region->bo;
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if (state->depth_region)
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aper_array[aper_count++] = state->depth_region->bo;
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}
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if (dirty & I915_UPLOAD_TEX_ALL) {
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for (i = 0; i < I915_TEX_UNITS; i++) {
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if (dirty & I915_UPLOAD_TEX(i)) {
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if (state->tex_buffer[i]) {
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aper_array[aper_count++] = state->tex_buffer[i];
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}
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}
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}
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}
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if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
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if (count == 0) {
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count++;
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intel_batchbuffer_flush(intel);
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goto again;
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} else {
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_mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
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assert(0);
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}
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}
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/* work out list of buffers to emit */
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/* Do this here as we may have flushed the batchbuffer above,
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* causing more state to be dirty!
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*/
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dirty = get_dirty(state);
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state->emitted |= dirty;
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assert(get_dirty(state) == 0);
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "%s dirty: %x\n", __func__, dirty);
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if (dirty & I915_UPLOAD_INVARIENT) {
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
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i915_emit_invarient_state(intel);
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}
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if (dirty & I915_UPLOAD_RASTER_RULES) {
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
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emit(intel, state->RasterRules, sizeof(state->RasterRules));
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}
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if (dirty & I915_UPLOAD_CTX) {
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "I915_UPLOAD_CTX:\n");
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emit(intel, state->Ctx, sizeof(state->Ctx));
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}
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if (dirty & I915_UPLOAD_BLEND) {
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "I915_UPLOAD_BLEND:\n");
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emit(intel, state->Blend, sizeof(state->Blend));
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}
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if (dirty & I915_UPLOAD_BUFFERS) {
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GLuint count;
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
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count = 17;
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if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
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count++;
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BEGIN_BATCH(count);
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OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
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OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
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if (state->draw_region) {
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OUT_RELOC(state->draw_region->bo,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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} else {
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OUT_BATCH(0);
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}
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OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
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OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
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if (state->depth_region) {
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OUT_RELOC(state->depth_region->bo,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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} else {
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OUT_BATCH(0);
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}
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OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
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OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
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OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
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OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
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OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
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OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
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if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
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OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
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OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
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OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
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OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
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OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
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OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
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ADVANCE_BATCH();
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}
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if (dirty & I915_UPLOAD_STIPPLE) {
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
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emit(intel, state->Stipple, sizeof(state->Stipple));
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}
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/* Combine all the dirty texture state into a single command to
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* avoid lockups on I915 hardware.
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*/
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if (dirty & I915_UPLOAD_TEX_ALL) {
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int nr = 0;
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GLuint unwind;
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for (i = 0; i < I915_TEX_UNITS; i++)
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if (dirty & I915_UPLOAD_TEX(i))
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nr++;
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BEGIN_BATCH(2 + nr * 3);
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OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
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OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
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for (i = 0; i < I915_TEX_UNITS; i++)
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if (dirty & I915_UPLOAD_TEX(i)) {
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OUT_RELOC(state->tex_buffer[i],
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I915_GEM_DOMAIN_SAMPLER, 0,
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state->tex_offset[i]);
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OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
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OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
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}
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ADVANCE_BATCH();
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unwind = intel->batch.used;
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BEGIN_BATCH(2 + nr * 3);
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OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
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OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
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for (i = 0; i < I915_TEX_UNITS; i++)
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if (dirty & I915_UPLOAD_TEX(i)) {
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OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
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OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
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OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
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}
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ADVANCE_BATCH();
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if (i915->last_sampler &&
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memcmp(intel->batch.map + i915->last_sampler,
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intel->batch.map + unwind,
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(2 + nr*3)*sizeof(int)) == 0)
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intel->batch.used = unwind;
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else
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i915->last_sampler = unwind;
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}
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if (dirty & I915_UPLOAD_CONSTANTS) {
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
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emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
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}
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if (dirty & I915_UPLOAD_PROGRAM) {
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if (state->ProgramSize) {
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if (INTEL_DEBUG & DEBUG_STATE)
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fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
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assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
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emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
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if (INTEL_DEBUG & DEBUG_STATE)
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i915_disassemble_program(state->Program, state->ProgramSize);
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}
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}
|
|
|
|
assert(get_dirty(state) == 0);
|
|
}
|
|
|
|
static void
|
|
i915_destroy_context(struct intel_context *intel)
|
|
{
|
|
GLuint i;
|
|
struct i915_context *i915 = i915_context(&intel->ctx);
|
|
|
|
intel_region_release(&i915->state.draw_region);
|
|
intel_region_release(&i915->state.depth_region);
|
|
|
|
for (i = 0; i < I915_TEX_UNITS; i++) {
|
|
if (i915->state.tex_buffer[i] != NULL) {
|
|
drm_intel_bo_unreference(i915->state.tex_buffer[i]);
|
|
i915->state.tex_buffer[i] = NULL;
|
|
}
|
|
}
|
|
|
|
_tnl_free_vertices(&intel->ctx);
|
|
}
|
|
|
|
void
|
|
i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
|
|
uint32_t buffer_id)
|
|
{
|
|
state[0] = _3DSTATE_BUF_INFO_CMD;
|
|
state[1] = buffer_id;
|
|
|
|
if (region != NULL) {
|
|
state[1] |= BUF_3D_PITCH(region->pitch);
|
|
|
|
if (region->tiling != I915_TILING_NONE) {
|
|
state[1] |= BUF_3D_TILED_SURFACE;
|
|
if (region->tiling == I915_TILING_Y)
|
|
state[1] |= BUF_3D_TILE_WALK_Y;
|
|
}
|
|
} else {
|
|
/* Fill in a default pitch, since 0 is invalid. We'll be
|
|
* setting the buffer offset to 0 and not referencing the
|
|
* buffer, so the pitch could really be any valid value.
|
|
*/
|
|
state[1] |= BUF_3D_PITCH(4096);
|
|
}
|
|
}
|
|
|
|
static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
|
|
{
|
|
[MESA_FORMAT_B8G8R8A8_UNORM] = DV_PF_8888,
|
|
[MESA_FORMAT_B8G8R8X8_UNORM] = DV_PF_8888,
|
|
[MESA_FORMAT_B5G6R5_UNORM] = DV_PF_565 | DITHER_FULL_ALWAYS,
|
|
[MESA_FORMAT_B5G5R5A1_UNORM] = DV_PF_1555 | DITHER_FULL_ALWAYS,
|
|
[MESA_FORMAT_B4G4R4A4_UNORM] = DV_PF_4444 | DITHER_FULL_ALWAYS,
|
|
};
|
|
|
|
static bool
|
|
i915_render_target_supported(struct intel_context *intel,
|
|
struct gl_renderbuffer *rb)
|
|
{
|
|
mesa_format format = rb->Format;
|
|
|
|
if (format == MESA_FORMAT_Z24_UNORM_S8_UINT ||
|
|
format == MESA_FORMAT_Z24_UNORM_X8_UINT ||
|
|
format == MESA_FORMAT_Z_UNORM16) {
|
|
return true;
|
|
}
|
|
|
|
return i915_render_target_format_for_mesa_format[format] != 0;
|
|
}
|
|
|
|
static void
|
|
i915_set_draw_region(struct intel_context *intel,
|
|
struct intel_region *color_regions[],
|
|
struct intel_region *depth_region,
|
|
GLuint num_regions)
|
|
{
|
|
struct i915_context *i915 = i915_context(&intel->ctx);
|
|
struct gl_context *ctx = &intel->ctx;
|
|
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
|
|
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
|
|
struct gl_renderbuffer *drb;
|
|
struct intel_renderbuffer *idrb = NULL;
|
|
GLuint value;
|
|
struct i915_hw_state *state = &i915->state;
|
|
uint32_t draw_x, draw_y, draw_offset;
|
|
|
|
if (state->draw_region != color_regions[0]) {
|
|
intel_region_reference(&state->draw_region, color_regions[0]);
|
|
}
|
|
if (state->depth_region != depth_region) {
|
|
intel_region_reference(&state->depth_region, depth_region);
|
|
}
|
|
|
|
/*
|
|
* Set stride/cpp values
|
|
*/
|
|
i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
|
|
color_regions[0], BUF_3D_ID_COLOR_BACK);
|
|
|
|
i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
|
|
depth_region, BUF_3D_ID_DEPTH);
|
|
|
|
/*
|
|
* Compute/set I915_DESTREG_DV1 value
|
|
*/
|
|
value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
|
|
DSTORG_VERT_BIAS(0x8) | /* .5 */
|
|
LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
|
|
if (irb != NULL) {
|
|
value |= i915_render_target_format_for_mesa_format[intel_rb_format(irb)];
|
|
} else {
|
|
value |= DV_PF_8888;
|
|
}
|
|
|
|
if (depth_region && depth_region->cpp == 4) {
|
|
value |= DEPTH_FRMT_24_FIXED_8_OTHER;
|
|
}
|
|
else {
|
|
value |= DEPTH_FRMT_16_FIXED;
|
|
}
|
|
state->Buffer[I915_DESTREG_DV1] = value;
|
|
|
|
drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
|
|
if (!drb)
|
|
drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
|
|
|
|
if (drb)
|
|
idrb = intel_renderbuffer(drb);
|
|
|
|
/* We set up the drawing rectangle to be offset into the color
|
|
* region's location in the miptree. If it doesn't match with
|
|
* depth's offsets, we can't render to it.
|
|
*
|
|
* (Well, not actually true -- the hw grew a bit to let depth's
|
|
* offset get forced to 0,0. We may want to use that if people are
|
|
* hitting that case. Also, some configurations may be supportable
|
|
* by tweaking the start offset of the buffers around, which we
|
|
* can't do in general due to tiling)
|
|
*/
|
|
FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
|
|
idrb && irb && (idrb->draw_x != irb->draw_x ||
|
|
idrb->draw_y != irb->draw_y));
|
|
|
|
if (irb) {
|
|
draw_x = irb->draw_x;
|
|
draw_y = irb->draw_y;
|
|
} else if (idrb) {
|
|
draw_x = idrb->draw_x;
|
|
draw_y = idrb->draw_y;
|
|
} else {
|
|
draw_x = 0;
|
|
draw_y = 0;
|
|
}
|
|
|
|
draw_offset = (draw_y << 16) | draw_x;
|
|
|
|
FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
|
|
(ctx->DrawBuffer->Width + draw_x > 2048) ||
|
|
(ctx->DrawBuffer->Height + draw_y > 2048));
|
|
/* When changing drawing rectangle offset, an MI_FLUSH is first required. */
|
|
if (draw_offset != i915->last_draw_offset) {
|
|
state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
|
|
i915->last_draw_offset = draw_offset;
|
|
} else
|
|
state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
|
|
|
|
state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
|
|
state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
|
|
state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
|
|
state->Buffer[I915_DESTREG_DRAWRECT4] =
|
|
((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
|
|
((ctx->DrawBuffer->Height + draw_y - 1) << 16);
|
|
state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
|
|
|
|
I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
|
|
}
|
|
|
|
static void
|
|
i915_update_color_write_enable(struct i915_context *i915, bool enable)
|
|
{
|
|
uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
|
|
if (enable)
|
|
dw |= S6_COLOR_WRITE_ENABLE;
|
|
else
|
|
dw &= ~S6_COLOR_WRITE_ENABLE;
|
|
if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
|
|
I915_STATECHANGE(i915, I915_UPLOAD_CTX);
|
|
i915->state.Ctx[I915_CTXREG_LIS6] = dw;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Update the hardware state for drawing into a window or framebuffer object.
|
|
*
|
|
* Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
|
|
* places within the driver.
|
|
*
|
|
* Basically, this needs to be called any time the current framebuffer
|
|
* changes, the renderbuffers change, or we need to draw into different
|
|
* color buffers.
|
|
*/
|
|
static void
|
|
i915_update_draw_buffer(struct intel_context *intel)
|
|
{
|
|
struct i915_context *i915 = (struct i915_context *)intel;
|
|
struct gl_context *ctx = &intel->ctx;
|
|
struct gl_framebuffer *fb = ctx->DrawBuffer;
|
|
struct intel_region *colorRegion = NULL, *depthRegion = NULL;
|
|
struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
|
|
|
|
if (!fb) {
|
|
/* this can happen during the initial context initialization */
|
|
return;
|
|
}
|
|
|
|
irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
|
|
irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
|
|
|
|
/* Do this here, not core Mesa, since this function is called from
|
|
* many places within the driver.
|
|
*/
|
|
if (ctx->NewState & _NEW_BUFFERS) {
|
|
/* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
|
|
_mesa_update_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer);
|
|
/* this updates the DrawBuffer's Width/Height if it's a FBO */
|
|
_mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
|
|
}
|
|
|
|
if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
|
|
/* this may occur when we're called by glBindFrameBuffer() during
|
|
* the process of someone setting up renderbuffers, etc.
|
|
*/
|
|
/*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
|
|
return;
|
|
}
|
|
|
|
/* How many color buffers are we drawing into?
|
|
*
|
|
* If there is more than one drawbuffer (GL_FRONT_AND_BACK), or the
|
|
* drawbuffers are too big, we have to fallback to software.
|
|
*/
|
|
if ((fb->Width > ctx->Const.MaxRenderbufferSize)
|
|
|| (fb->Height > ctx->Const.MaxRenderbufferSize)) {
|
|
FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
|
|
} else if (fb->_NumColorDrawBuffers > 1) {
|
|
FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
|
|
} else {
|
|
struct intel_renderbuffer *irb;
|
|
irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
|
|
colorRegion = (irb && irb->mt) ? irb->mt->region : NULL;
|
|
FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
|
|
}
|
|
|
|
/* Check for depth fallback. */
|
|
if (irbDepth && irbDepth->mt) {
|
|
FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
|
|
depthRegion = irbDepth->mt->region;
|
|
} else if (irbDepth && !irbDepth->mt) {
|
|
FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true);
|
|
depthRegion = NULL;
|
|
} else { /* !irbDepth */
|
|
/* No fallback is needed because there is no depth buffer. */
|
|
FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
|
|
depthRegion = NULL;
|
|
}
|
|
|
|
/* Check for stencil fallback. */
|
|
if (irbStencil && irbStencil->mt) {
|
|
assert(intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT);
|
|
FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
|
|
} else if (irbStencil && !irbStencil->mt) {
|
|
FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
|
|
} else { /* !irbStencil */
|
|
/* No fallback is needed because there is no stencil buffer. */
|
|
FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
|
|
}
|
|
|
|
/* If we have a (packed) stencil buffer attached but no depth buffer,
|
|
* we still need to set up the shared depth/stencil state so we can use it.
|
|
*/
|
|
if (depthRegion == NULL && irbStencil && irbStencil->mt
|
|
&& intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT) {
|
|
depthRegion = irbStencil->mt->region;
|
|
}
|
|
|
|
/*
|
|
* Update depth and stencil test state
|
|
*/
|
|
ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
|
|
ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
|
|
|
|
i915_update_color_write_enable(i915, colorRegion != NULL);
|
|
|
|
intel->vtbl.set_draw_region(intel, &colorRegion, depthRegion,
|
|
fb->_NumColorDrawBuffers);
|
|
intel->NewGLState |= _NEW_BUFFERS;
|
|
|
|
/* Set state we know depends on drawable parameters:
|
|
*/
|
|
intelCalcViewport(ctx);
|
|
ctx->Driver.Scissor(ctx);
|
|
|
|
/* Update culling direction which changes depending on the
|
|
* orientation of the buffer:
|
|
*/
|
|
ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
|
|
}
|
|
|
|
static void
|
|
i915_new_batch(struct intel_context *intel)
|
|
{
|
|
struct i915_context *i915 = i915_context(&intel->ctx);
|
|
|
|
/* Mark all state as needing to be emitted when starting a new batchbuffer.
|
|
* Using hardware contexts would be an alternative, but they have some
|
|
* difficulties associated with them (physical address requirements).
|
|
*/
|
|
i915->state.emitted = 0;
|
|
i915->last_draw_offset = 0;
|
|
i915->last_sampler = 0;
|
|
|
|
i915->current_vb_bo = NULL;
|
|
i915->current_vertex_size = 0;
|
|
}
|
|
|
|
static void
|
|
i915_assert_not_dirty( struct intel_context *intel )
|
|
{
|
|
struct i915_context *i915 = i915_context(&intel->ctx);
|
|
GLuint dirty = get_dirty(&i915->state);
|
|
assert(!dirty);
|
|
(void) dirty;
|
|
}
|
|
|
|
static void
|
|
i915_invalidate_state(struct intel_context *intel, GLuint new_state)
|
|
{
|
|
struct gl_context *ctx = &intel->ctx;
|
|
|
|
_swsetup_InvalidateState(ctx, new_state);
|
|
_tnl_InvalidateState(ctx, new_state);
|
|
_tnl_invalidate_vertex_state(ctx, new_state);
|
|
}
|
|
|
|
void
|
|
i915InitVtbl(struct i915_context *i915)
|
|
{
|
|
i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
|
|
i915->intel.vtbl.destroy = i915_destroy_context;
|
|
i915->intel.vtbl.emit_state = i915_emit_state;
|
|
i915->intel.vtbl.new_batch = i915_new_batch;
|
|
i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
|
|
i915->intel.vtbl.render_start = i915_render_start;
|
|
i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
|
|
i915->intel.vtbl.set_draw_region = i915_set_draw_region;
|
|
i915->intel.vtbl.update_draw_buffer = i915_update_draw_buffer;
|
|
i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
|
|
i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
|
|
i915->intel.vtbl.finish_batch = intel_finish_vb;
|
|
i915->intel.vtbl.invalidate_state = i915_invalidate_state;
|
|
i915->intel.vtbl.render_target_supported = i915_render_target_supported;
|
|
}
|