115 lines
4.4 KiB
C
115 lines
4.4 KiB
C
/*
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* Copyright (c) 2021 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/*
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* Lower the shading rate output from the bit field format described in the
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* SPIRV spec :
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*
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* bit | name | description
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* 0 | Vertical2Pixels | Fragment invocation covers 2 pixels vertically
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* 1 | Vertical4Pixels | Fragment invocation covers 4 pixels vertically
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* 2 | Horizontal2Pixels | Fragment invocation covers 2 pixels horizontally
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* 3 | Horizontal4Pixels | Fragment invocation covers 4 pixels horizontally
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*
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* into a single dword composed of 2 fp16 to be stored in the dword 0 of the
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* VUE header.
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*
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* When no horizontal/vertical bits are set, the size in pixel size in that
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* dimension is assumed to be 1.
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*
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* According to the specification, the shading rate output can be read &
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* written. A read after a write should report a different value if the
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* implementation decides on different primitive shading rate for some reason.
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* This is never the case in our implementation.
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*/
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#include "brw_nir.h"
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#include "compiler/nir/nir_builder.h"
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static bool
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lower_shading_rate_output_instr(nir_builder *b, nir_instr *instr,
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UNUSED void *_state)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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nir_intrinsic_op op = intrin->intrinsic;
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if (op != nir_intrinsic_load_output &&
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op != nir_intrinsic_store_output &&
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op != nir_intrinsic_load_per_primitive_output &&
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op != nir_intrinsic_store_per_primitive_output)
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return false;
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struct nir_io_semantics io = nir_intrinsic_io_semantics(intrin);
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if (io.location != VARYING_SLOT_PRIMITIVE_SHADING_RATE)
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return false;
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bool is_store = op == nir_intrinsic_store_output ||
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op == nir_intrinsic_store_per_primitive_output;
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b->cursor = is_store ? nir_before_instr(instr) : nir_after_instr(instr);
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if (is_store) {
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assert(intrin->src[0].is_ssa);
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nir_ssa_def *bit_field = intrin->src[0].ssa;
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nir_ssa_def *fp16_x =
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nir_i2f16(b,
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nir_ishl(b, nir_imm_int(b, 1),
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nir_ishr_imm(b, bit_field, 2)));
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nir_ssa_def *fp16_y =
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nir_i2f16(b,
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nir_ishl(b, nir_imm_int(b, 1),
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nir_iand_imm(b, bit_field, 0x3)));
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nir_ssa_def *packed_fp16_xy = nir_pack_32_2x16_split(b, fp16_x, fp16_y);
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nir_instr_rewrite_src(instr, &intrin->src[0],
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nir_src_for_ssa(packed_fp16_xy));
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} else {
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nir_ssa_def *packed_fp16_xy = &intrin->dest.ssa;
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nir_ssa_def *u32_x =
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nir_i2i32(b, nir_unpack_32_2x16_split_x(b, packed_fp16_xy));
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nir_ssa_def *u32_y =
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nir_i2i32(b, nir_unpack_32_2x16_split_y(b, packed_fp16_xy));
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nir_ssa_def *bit_field =
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nir_ior(b, nir_ishl_imm(b, nir_ushr_imm(b, u32_x, 1), 2),
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nir_ushr_imm(b, u32_y, 1));
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nir_ssa_def_rewrite_uses_after(packed_fp16_xy, bit_field,
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bit_field->parent_instr);
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}
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return true;
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}
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bool
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brw_nir_lower_shading_rate_output(nir_shader *nir)
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{
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return nir_shader_instructions_pass(nir, lower_shading_rate_output_instr,
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nir_metadata_block_index |
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nir_metadata_dominance, NULL);
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}
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