380 lines
14 KiB
C
380 lines
14 KiB
C
/*
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* Copyright (c) 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <math.h>
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#include "util/debug.h"
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#include "util/macros.h"
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#include "util/u_math.h"
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#include "compiler/shader_enums.h"
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#include "intel_l3_config.h"
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/**
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* The following diagram shows how we partition the URB:
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*
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* 16kb or 32kb Rest of the URB space
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* __________-__________ _________________-_________________
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* / \ / \
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* +-------------------------------------------------------------+
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* | VS/HS/DS/GS/FS Push | VS/HS/DS/GS URB |
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* | Constants | Entries |
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* +-------------------------------------------------------------+
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*
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* Push constants must be stored at the beginning of the URB space,
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* while URB entries can be stored anywhere. We choose to lay them
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* out in pipeline order (VS -> HS -> DS -> GS).
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*/
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/**
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* Decide how to partition the URB among the various stages.
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*
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* \param[in] push_constant_bytes - space allocate for push constants.
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* \param[in] urb_size_bytes - total size of the URB (from L3 config).
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* \param[in] tess_present - are tessellation shaders active?
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* \param[in] gs_present - are geometry shaders active?
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* \param[in] entry_size - the URB entry size (from the shader compiler)
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* \param[out] entries - the number of URB entries for each stage
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* \param[out] start - the starting offset for each stage
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* \param[out] deref_block_size - deref block size for 3DSTATE_SF
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* \param[out] constrained - true if we wanted more space than we had
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*/
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void
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intel_get_urb_config(const struct intel_device_info *devinfo,
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const struct intel_l3_config *l3_cfg,
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bool tess_present, bool gs_present,
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const unsigned entry_size[4],
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unsigned entries[4], unsigned start[4],
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enum intel_urb_deref_block_size *deref_block_size,
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bool *constrained)
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{
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unsigned urb_size_kB = intel_get_l3_config_urb_size(devinfo, l3_cfg);
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/* RCU_MODE register for Gfx12LP in BSpec says:
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*
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* "HW reserves 4KB of URB space per bank for Compute Engine out of the
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* total storage available in L3. SW must consider that 4KB of storage
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* per bank will be reduced from what is programmed for the URB space
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* in L3 for Render Engine executed workloads.
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*
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* Example: When URB space programmed is 64KB (per bank) for Render
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* Engine, the actual URB space available for operation is only 60KB
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* (per bank). Similarly when URB space programmed is 128KB (per bank)
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* for render engine, the actual URB space available for operation is
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* only 124KB (per bank). More detailed description available in "L3
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* Cache" section of the B-Spec."
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*/
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if (devinfo->verx10 == 120) {
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assert(devinfo->num_slices == 1);
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urb_size_kB -= 4 * devinfo->l3_banks;
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}
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const unsigned push_constant_kB = devinfo->max_constant_urb_size_kb;
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const bool active[4] = { true, tess_present, tess_present, gs_present };
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/* URB allocations must be done in 8k chunks. */
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const unsigned chunk_size_kB = 8;
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const unsigned chunk_size_bytes = chunk_size_kB * 1024;
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const unsigned push_constant_chunks = push_constant_kB / chunk_size_kB;
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const unsigned urb_chunks = urb_size_kB / chunk_size_kB;
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/* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
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*
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* VS Number of URB Entries must be divisible by 8 if the VS URB Entry
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* Allocation Size is less than 9 512-bit URB entries.
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*
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* Similar text exists for HS, DS and GS.
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*/
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unsigned granularity[4];
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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granularity[i] = (entry_size[i] < 9) ? 8 : 1;
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}
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unsigned min_entries[4] = {
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/* VS has a lower limit on the number of URB entries.
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*
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* From the Broadwell PRM, 3DSTATE_URB_VS instruction:
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* "When tessellation is enabled, the VS Number of URB Entries must be
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* greater than or equal to 192."
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*/
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[MESA_SHADER_VERTEX] = tess_present && devinfo->ver == 8 ?
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192 : devinfo->urb.min_entries[MESA_SHADER_VERTEX],
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/* There are two constraints on the minimum amount of URB space we can
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* allocate:
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*
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* (1) We need room for at least 2 URB entries, since we always operate
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* the GS in DUAL_OBJECT mode.
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*
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* (2) We can't allocate less than nr_gs_entries_granularity.
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*/
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[MESA_SHADER_GEOMETRY] = gs_present ? 2 : 0,
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[MESA_SHADER_TESS_CTRL] = tess_present ? 1 : 0,
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[MESA_SHADER_TESS_EVAL] = tess_present ?
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devinfo->urb.min_entries[MESA_SHADER_TESS_EVAL] : 0,
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};
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/* Min VS Entries isn't a multiple of 8 on Cherryview/Broxton; round up.
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* Round them all up.
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*/
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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min_entries[i] = ALIGN(min_entries[i], granularity[i]);
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}
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unsigned entry_size_bytes[4];
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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entry_size_bytes[i] = 64 * entry_size[i];
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}
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/* Initially, assign each stage the minimum amount of URB space it needs,
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* and make a note of how much additional space it "wants" (the amount of
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* additional space it could actually make use of).
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*/
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unsigned chunks[4];
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unsigned wants[4];
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unsigned total_needs = push_constant_chunks;
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unsigned total_wants = 0;
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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if (active[i]) {
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chunks[i] = DIV_ROUND_UP(min_entries[i] * entry_size_bytes[i],
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chunk_size_bytes);
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wants[i] =
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DIV_ROUND_UP(devinfo->urb.max_entries[i] * entry_size_bytes[i],
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chunk_size_bytes) - chunks[i];
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} else {
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chunks[i] = 0;
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wants[i] = 0;
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}
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total_needs += chunks[i];
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total_wants += wants[i];
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}
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assert(total_needs <= urb_chunks);
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*constrained = total_needs + total_wants > urb_chunks;
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/* Mete out remaining space (if any) in proportion to "wants". */
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unsigned remaining_space = MIN2(urb_chunks - total_needs, total_wants);
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if (remaining_space > 0) {
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for (int i = MESA_SHADER_VERTEX;
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total_wants > 0 && i <= MESA_SHADER_TESS_EVAL; i++) {
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unsigned additional = (unsigned)
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roundf(wants[i] * (((float) remaining_space) / total_wants));
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chunks[i] += additional;
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remaining_space -= additional;
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total_wants -= wants[i];
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}
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chunks[MESA_SHADER_GEOMETRY] += remaining_space;
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}
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/* Sanity check that we haven't over-allocated. */
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unsigned total_chunks = push_constant_chunks;
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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total_chunks += chunks[i];
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}
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assert(total_chunks <= urb_chunks);
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/* Finally, compute the number of entries that can fit in the space
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* allocated to each stage.
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*/
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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entries[i] = chunks[i] * chunk_size_bytes / entry_size_bytes[i];
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/* Since we rounded up when computing wants[], this may be slightly
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* more than the maximum allowed amount, so correct for that.
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*/
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entries[i] = MIN2(entries[i], devinfo->urb.max_entries[i]);
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/* Ensure that we program a multiple of the granularity. */
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entries[i] = ROUND_DOWN_TO(entries[i], granularity[i]);
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/* Finally, sanity check to make sure we have at least the minimum
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* number of entries needed for each stage.
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*/
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assert(entries[i] >= min_entries[i]);
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}
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/* Lay out the URB in pipeline order: push constants, VS, HS, DS, GS. */
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int first_urb = push_constant_chunks;
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/* From the BDW PRM: for 3DSTATE_URB_*: VS URB Starting Address
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*
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* "Value: [4,48] Device [SliceCount] GT 1"
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*
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* From the ICL PRMs and above :
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*
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* "If CTXT_SR_CTL::POSH_Enable is clear and Push Constants are required
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* or Device[SliceCount] GT 1, the lower limit is 4."
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*
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* "If Push Constants are not required andDevice[SliceCount] == 1, the
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* lower limit is 0."
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*/
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if ((devinfo->ver == 8 && devinfo->num_slices == 1) ||
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(devinfo->ver >= 11 && push_constant_chunks > 0 && devinfo->num_slices == 1))
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first_urb = MAX2(first_urb, 4);
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int next_urb = first_urb;
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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if (entries[i]) {
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start[i] = next_urb;
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next_urb += chunks[i];
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} else {
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/* Put disabled stages at the beginning of the valid range */
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start[i] = first_urb;
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}
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}
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if (deref_block_size) {
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if (devinfo->ver >= 12) {
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/* From the Gfx12 BSpec:
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*
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* "Deref Block size depends on the last enabled shader and number
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* of handles programmed for that shader
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*
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* 1) For GS last shader enabled cases, the deref block is
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* always set to a per poly(within hardware)
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*
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* If the last enabled shader is VS or DS.
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*
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* 1) If DS is last enabled shader then if the number of DS
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* handles is less than 324, need to set per poly deref.
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*
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* 2) If VS is last enabled shader then if the number of VS
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* handles is less than 192, need to set per poly deref"
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*
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* The default is 32 so we assume that's the right choice if we're
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* not in one of the explicit cases listed above.
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*/
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if (gs_present) {
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*deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
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} else if (tess_present) {
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if (entries[MESA_SHADER_TESS_EVAL] < 324)
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*deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
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else
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*deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_32;
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} else {
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if (entries[MESA_SHADER_VERTEX] < 192)
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*deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
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else
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*deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_32;
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}
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} else {
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*deref_block_size = 0;
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}
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}
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}
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struct intel_mesh_urb_allocation
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intel_get_mesh_urb_config(const struct intel_device_info *devinfo,
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const struct intel_l3_config *l3_cfg,
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unsigned tue_size_dw, unsigned mue_size_dw)
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{
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struct intel_mesh_urb_allocation r = {0};
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/* Allocation Size must be aligned to 64B. */
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r.task_entry_size_64b = DIV_ROUND_UP(tue_size_dw * 4, 64);
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r.mesh_entry_size_64b = DIV_ROUND_UP(mue_size_dw * 4, 64);
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assert(r.task_entry_size_64b <= 1024);
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assert(r.mesh_entry_size_64b <= 1024);
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/* Per-slice URB size. */
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unsigned total_urb_kb = intel_get_l3_config_urb_size(devinfo, l3_cfg);
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/* Programming Note in bspec requires all the slice to have the same number
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* of entries, so we need to discount the space for constants for all of
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* them. See 3DSTATE_URB_ALLOC_MESH and 3DSTATE_URB_ALLOC_TASK.
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*/
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const unsigned push_constant_kb = devinfo->max_constant_urb_size_kb;
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total_urb_kb -= push_constant_kb;
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/* TODO(mesh): Take push constant size as parameter instead of considering always
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* the max? */
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float task_urb_share = 0.0f;
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if (r.task_entry_size_64b > 0) {
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/* By default, assign 10% to TASK and 90% to MESH, since we expect MESH
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* to use larger URB entries since it contains all the vertex and
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* primitive data. Environment variable allow us to tweak it.
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*
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* TODO(mesh): Re-evaluate if this is a good default once there are more
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* workloads.
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*/
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static int task_urb_share_percentage = -1;
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if (task_urb_share_percentage < 0) {
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task_urb_share_percentage =
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MIN2(env_var_as_unsigned("INTEL_MESH_TASK_URB_SHARE", 10), 100);
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}
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task_urb_share = task_urb_share_percentage / 100.0f;
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}
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const unsigned task_urb_kb = ALIGN(total_urb_kb * task_urb_share, 8);
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const unsigned mesh_urb_kb = total_urb_kb - task_urb_kb;
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/* TODO(mesh): Could we avoid allocating URB for Mesh if rasterization is
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* disabled? */
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unsigned next_address_8kb = DIV_ROUND_UP(push_constant_kb, 8);
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if (r.task_entry_size_64b > 0) {
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r.task_entries = MIN2((task_urb_kb * 16) / r.task_entry_size_64b, 1548);
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/* 3DSTATE_URB_ALLOC_TASK_BODY says
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*
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* TASK Number of URB Entries must be divisible by 8 if the TASK URB
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* Entry Allocation Size is less than 9 512-bit URB entries.
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*/
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if (r.task_entry_size_64b < 9)
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r.task_entries = ROUND_DOWN_TO(r.task_entries, 8);
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r.task_starting_address_8kb = next_address_8kb;
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assert(task_urb_kb % 8 == 0);
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next_address_8kb += task_urb_kb / 8;
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}
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r.mesh_entries = MIN2((mesh_urb_kb * 16) / r.mesh_entry_size_64b, 1548);
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/* Similar restriction to TASK. */
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if (r.mesh_entry_size_64b < 9)
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r.mesh_entries = ROUND_DOWN_TO(r.mesh_entries, 8);
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r.mesh_starting_address_8kb = next_address_8kb;
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r.deref_block_size = r.mesh_entries > 32 ?
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INTEL_URB_DEREF_BLOCK_SIZE_MESH :
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INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
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return r;
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}
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