313 lines
10 KiB
C
313 lines
10 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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* based on amdgpu winsys.
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* Copyright © 2011 Marek Olšák <maraeo@gmail.com>
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* Copyright © 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "radv_amdgpu_winsys.h"
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#include <assert.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "drm-uapi/amdgpu_drm.h"
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#include "ac_surface.h"
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#include "radv_amdgpu_bo.h"
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#include "radv_amdgpu_cs.h"
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#include "radv_amdgpu_surface.h"
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#include "radv_amdgpu_winsys_public.h"
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#include "radv_debug.h"
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#include "vk_drm_syncobj.h"
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#include "xf86drm.h"
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static bool
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do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
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{
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if (!ac_query_gpu_info(fd, ws->dev, &ws->info))
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return false;
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if (ws->info.drm_minor < 23) {
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fprintf(stderr, "radv/amdgpu: DRM 3.23+ is required (Linux kernel 4.15+)\n");
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return false;
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}
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ws->addrlib = ac_addrlib_create(&ws->info, &ws->info.max_alignment);
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if (!ws->addrlib) {
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fprintf(stderr, "radv/amdgpu: Cannot create addrlib.\n");
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return false;
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}
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ws->info.ip[AMD_IP_SDMA].num_queues = MIN2(ws->info.ip[AMD_IP_SDMA].num_queues, MAX_RINGS_PER_TYPE);
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ws->info.ip[AMD_IP_COMPUTE].num_queues = MIN2(ws->info.ip[AMD_IP_COMPUTE].num_queues, MAX_RINGS_PER_TYPE);
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ws->use_ib_bos = ws->info.gfx_level >= GFX7;
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return true;
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}
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static void
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radv_amdgpu_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
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{
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*info = ((struct radv_amdgpu_winsys *)rws)->info;
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}
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static uint64_t
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radv_amdgpu_winsys_query_value(struct radeon_winsys *rws, enum radeon_value_id value)
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{
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struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
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struct amdgpu_heap_info heap;
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uint64_t retval = 0;
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switch (value) {
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case RADEON_ALLOCATED_VRAM:
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return ws->allocated_vram;
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case RADEON_ALLOCATED_VRAM_VIS:
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return ws->allocated_vram_vis;
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case RADEON_ALLOCATED_GTT:
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return ws->allocated_gtt;
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case RADEON_TIMESTAMP:
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amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
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return retval;
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case RADEON_NUM_BYTES_MOVED:
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amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
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return retval;
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case RADEON_NUM_EVICTIONS:
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amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
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return retval;
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case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
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amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
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return retval;
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case RADEON_VRAM_USAGE:
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amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
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return heap.heap_usage;
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case RADEON_VRAM_VIS_USAGE:
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amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
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&heap);
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return heap.heap_usage;
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case RADEON_GTT_USAGE:
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amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
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return heap.heap_usage;
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case RADEON_GPU_TEMPERATURE:
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amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
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return retval;
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case RADEON_CURRENT_SCLK:
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amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
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return retval;
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case RADEON_CURRENT_MCLK:
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amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
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return retval;
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default:
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unreachable("invalid query value");
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}
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return 0;
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}
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static bool
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radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws, unsigned reg_offset,
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unsigned num_registers, uint32_t *out)
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{
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struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
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return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, 0xffffffff, 0, out) == 0;
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}
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static const char *
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radv_amdgpu_winsys_get_chip_name(struct radeon_winsys *rws)
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{
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amdgpu_device_handle dev = ((struct radv_amdgpu_winsys *)rws)->dev;
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return amdgpu_get_marketing_name(dev);
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}
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static simple_mtx_t winsys_creation_mutex = _SIMPLE_MTX_INITIALIZER_NP;
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static struct hash_table *winsyses = NULL;
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static void
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radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
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{
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struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
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bool destroy = false;
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simple_mtx_lock(&winsys_creation_mutex);
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if (!--ws->refcount) {
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_mesa_hash_table_remove_key(winsyses, ws->dev);
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/* Clean the hashtable up if empty, though there is no
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* empty function. */
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if (_mesa_hash_table_num_entries(winsyses) == 0) {
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_mesa_hash_table_destroy(winsyses, NULL);
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winsyses = NULL;
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}
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destroy = true;
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}
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simple_mtx_unlock(&winsys_creation_mutex);
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if (!destroy)
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return;
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u_rwlock_destroy(&ws->global_bo_list.lock);
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free(ws->global_bo_list.bos);
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if (ws->reserve_vmid)
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amdgpu_vm_unreserve_vmid(ws->dev, 0);
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u_rwlock_destroy(&ws->log_bo_list_lock);
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ac_addrlib_destroy(ws->addrlib);
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amdgpu_device_deinitialize(ws->dev);
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FREE(rws);
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}
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static int
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radv_amdgpu_winsys_get_fd(struct radeon_winsys *rws)
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{
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struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
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return amdgpu_device_get_fd(ws->dev);
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}
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static const struct vk_sync_type *const *
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radv_amdgpu_winsys_get_sync_types(struct radeon_winsys *rws)
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{
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struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
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return ws->sync_types;
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}
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struct radeon_winsys *
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radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags, bool reserve_vmid)
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{
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uint32_t drm_major, drm_minor, r;
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amdgpu_device_handle dev;
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struct radv_amdgpu_winsys *ws = NULL;
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r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
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if (r) {
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fprintf(stderr, "radv/amdgpu: failed to initialize device.\n");
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return NULL;
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}
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/* We have to keep this lock till insertion. */
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simple_mtx_lock(&winsys_creation_mutex);
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if (!winsyses)
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winsyses = _mesa_pointer_hash_table_create(NULL);
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if (!winsyses) {
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fprintf(stderr, "radv/amdgpu: failed to alloc winsys hash table.\n");
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goto fail;
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}
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struct hash_entry *entry = _mesa_hash_table_search(winsyses, dev);
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if (entry) {
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ws = (struct radv_amdgpu_winsys *)entry->data;
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++ws->refcount;
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}
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if (ws) {
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simple_mtx_unlock(&winsys_creation_mutex);
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amdgpu_device_deinitialize(dev);
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/* Check that options don't differ from the existing winsys. */
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if (((debug_flags & RADV_DEBUG_ALL_BOS) && !ws->debug_all_bos) ||
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((debug_flags & RADV_DEBUG_HANG) && !ws->debug_log_bos) ||
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((debug_flags & RADV_DEBUG_NO_IBS) && ws->use_ib_bos) ||
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(perftest_flags != ws->perftest)) {
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fprintf(stderr, "radv/amdgpu: Found options that differ from the existing winsys.\n");
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return NULL;
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}
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/* RADV_DEBUG_ZERO_VRAM is the only option that is allowed to be set again. */
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if (debug_flags & RADV_DEBUG_ZERO_VRAM)
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ws->zero_all_vram_allocs = true;
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return &ws->base;
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}
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ws = calloc(1, sizeof(struct radv_amdgpu_winsys));
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if (!ws)
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goto fail;
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ws->refcount = 1;
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ws->dev = dev;
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ws->info.drm_major = drm_major;
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ws->info.drm_minor = drm_minor;
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if (!do_winsys_init(ws, fd))
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goto winsys_fail;
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ws->debug_all_bos = !!(debug_flags & RADV_DEBUG_ALL_BOS);
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ws->debug_log_bos = debug_flags & RADV_DEBUG_HANG;
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if (debug_flags & RADV_DEBUG_NO_IBS)
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ws->use_ib_bos = false;
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ws->reserve_vmid = reserve_vmid;
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if (ws->reserve_vmid) {
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r = amdgpu_vm_reserve_vmid(dev, 0);
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if (r) {
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fprintf(stderr, "radv/amdgpu: failed to reserve vmid.\n");
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goto vmid_fail;
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}
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}
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int num_sync_types = 0;
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ws->syncobj_sync_type = vk_drm_syncobj_get_type(amdgpu_device_get_fd(ws->dev));
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if (ws->syncobj_sync_type.features) {
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ws->sync_types[num_sync_types++] = &ws->syncobj_sync_type;
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if (!(ws->syncobj_sync_type.features & VK_SYNC_FEATURE_TIMELINE)) {
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ws->emulated_timeline_sync_type = vk_sync_timeline_get_type(&ws->syncobj_sync_type);
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ws->sync_types[num_sync_types++] = &ws->emulated_timeline_sync_type.sync;
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}
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}
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ws->sync_types[num_sync_types++] = NULL;
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assert(num_sync_types <= ARRAY_SIZE(ws->sync_types));
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ws->perftest = perftest_flags;
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ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
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u_rwlock_init(&ws->global_bo_list.lock);
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list_inithead(&ws->log_bo_list);
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u_rwlock_init(&ws->log_bo_list_lock);
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ws->base.query_info = radv_amdgpu_winsys_query_info;
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ws->base.query_value = radv_amdgpu_winsys_query_value;
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ws->base.read_registers = radv_amdgpu_winsys_read_registers;
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ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
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ws->base.destroy = radv_amdgpu_winsys_destroy;
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ws->base.get_fd = radv_amdgpu_winsys_get_fd;
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ws->base.get_sync_types = radv_amdgpu_winsys_get_sync_types;
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radv_amdgpu_bo_init_functions(ws);
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radv_amdgpu_cs_init_functions(ws);
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radv_amdgpu_surface_init_functions(ws);
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_mesa_hash_table_insert(winsyses, dev, ws);
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simple_mtx_unlock(&winsys_creation_mutex);
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return &ws->base;
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vmid_fail:
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ac_addrlib_destroy(ws->addrlib);
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winsys_fail:
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free(ws);
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fail:
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if (winsyses && _mesa_hash_table_num_entries(winsyses) == 0) {
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_mesa_hash_table_destroy(winsyses, NULL);
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winsyses = NULL;
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}
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simple_mtx_unlock(&winsys_creation_mutex);
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amdgpu_device_deinitialize(dev);
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return NULL;
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}
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