555 lines
18 KiB
JSON
555 lines
18 KiB
JSON
{
|
|
"enums": {
|
|
"COMMAND__SAIC": {
|
|
"entries": [
|
|
{"name": "INCREMENT", "value": 0},
|
|
{"name": "NO_INCREMENT", "value": 1}
|
|
]
|
|
},
|
|
"COMMAND__SAS": {
|
|
"entries": [
|
|
{"name": "MEMORY", "value": 0},
|
|
{"name": "REGISTER", "value": 1}
|
|
]
|
|
},
|
|
"COMMAND__SRC_SWAP": {
|
|
"entries": [
|
|
{"name": "NONE", "value": 0},
|
|
{"name": "8_IN_16", "value": 1},
|
|
{"name": "8_IN_32", "value": 2},
|
|
{"name": "8_IN_64", "value": 3}
|
|
]
|
|
},
|
|
"CONTROL__DST_SEL": {
|
|
"entries": [
|
|
{"name": "MEM_MAPPED_REGISTER", "value": 0},
|
|
{"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
|
|
{"name": "TC_L2", "value": 2},
|
|
{"name": "GDS", "value": 3},
|
|
{"name": "RESERVED", "value": 4}
|
|
]
|
|
},
|
|
"CONTROL__DST_SEL_cik": {
|
|
"entries": [
|
|
{"name": "MEM_MAPPED_REGISTER", "value": 0},
|
|
{"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
|
|
{"name": "TC_L2", "value": 2},
|
|
{"name": "GDS", "value": 3},
|
|
{"name": "RESERVED", "value": 4},
|
|
{"name": "MEM", "value": 5}
|
|
]
|
|
},
|
|
"CONTROL__ENGINE_SEL": {
|
|
"entries": [
|
|
{"name": "ME", "value": 0},
|
|
{"name": "PFP", "value": 1},
|
|
{"name": "CE", "value": 2},
|
|
{"name": "DE", "value": 3}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1__DST_SEL": {
|
|
"entries": [
|
|
{"name": "DST_ADDR", "value": 0},
|
|
{"comment": "program DAS to 1 as well", "name": "GDS", "value": 1}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1__DST_SEL_cik": {
|
|
"entries": [
|
|
{"name": "DST_ADDR", "value": 0},
|
|
{"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
|
|
{"name": "DST_ADDR_TC_L2", "value": 3}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1__DST_SEL_gfx9": {
|
|
"entries": [
|
|
{"name": "DST_ADDR", "value": 0},
|
|
{"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
|
|
{"name": "NOWHERE", "value": 2},
|
|
{"name": "DST_ADDR_TC_L2", "value": 3}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1__ENGINE": {
|
|
"entries": [
|
|
{"name": "ME", "value": 0},
|
|
{"name": "PFP", "value": 1}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1__SRC_SEL": {
|
|
"entries": [
|
|
{"name": "SRC_ADDR", "value": 0},
|
|
{"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
|
|
{"name": "DATA", "value": 2}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1__SRC_SEL_cik": {
|
|
"entries": [
|
|
{"name": "SRC_ADDR", "value": 0},
|
|
{"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
|
|
{"name": "DATA", "value": 2},
|
|
{"name": "SRC_ADDR_TC_L2", "value": 3}
|
|
]
|
|
},
|
|
"GCR_GL1_RANGE": {
|
|
"entries": [
|
|
{"name": "GL1_ALL", "value": 0},
|
|
{"name": "GL1_RANGE", "value": 2},
|
|
{"name": "GL1_FIRST_LAST", "value": 3}
|
|
]
|
|
},
|
|
"GCR_GL2_RANGE": {
|
|
"entries": [
|
|
{"name": "GL2_ALL", "value": 0},
|
|
{"name": "GL2_VOL", "value": 1},
|
|
{"name": "GL2_RANGE", "value": 2},
|
|
{"name": "GL2_FIRST_LAST", "value": 3}
|
|
]
|
|
},
|
|
"GCR_GLI_INV": {
|
|
"entries": [
|
|
{"name": "GLI_NOP", "value": 0},
|
|
{"name": "GLI_ALL", "value": 1},
|
|
{"name": "GLI_RANGE", "value": 2},
|
|
{"name": "GLI_FIRST_LAST", "value": 3}
|
|
]
|
|
},
|
|
"GCR_SEQ": {
|
|
"entries": [
|
|
{"name": "SEQ_PARALLEL", "value": 0},
|
|
{"name": "SEQ_FORWARD", "value": 1},
|
|
{"name": "SEQ_REVERSE", "value": 2}
|
|
]
|
|
},
|
|
"PWS_STAGE_SEL": {
|
|
"entries": [
|
|
{"name": "PRE_DEPTH", "value": 0},
|
|
{"name": "PRE_SHADER", "value": 1},
|
|
{"name": "PRE_COLOR", "value": 2},
|
|
{"name": "PRE_PIX_SHADER", "value": 3},
|
|
{"name": "CP_PFP", "value": 4},
|
|
{"name": "CP_ME", "value": 5}
|
|
]
|
|
},
|
|
"PWS_COUNTER_SEL": {
|
|
"entries": [
|
|
{"name": "TS_SELECT", "value": 0},
|
|
{"name": "PS_SELECT", "value": 1},
|
|
{"name": "CS_SELECT", "value": 2}
|
|
]
|
|
},
|
|
"VGT_EVENT_TYPE_gfx11": {
|
|
"entries": [
|
|
{"name": "Reserved_0x00", "value": 0},
|
|
{"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
|
|
{"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
|
|
{"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
|
|
{"name": "CACHE_FLUSH_TS", "value": 4},
|
|
{"name": "CONTEXT_DONE", "value": 5},
|
|
{"name": "CACHE_FLUSH", "value": 6},
|
|
{"name": "CS_PARTIAL_FLUSH", "value": 7},
|
|
{"name": "VGT_STREAMOUT_SYNC", "value": 8},
|
|
{"name": "Reserved_0x09", "value": 9},
|
|
{"name": "VGT_STREAMOUT_RESET", "value": 10},
|
|
{"name": "END_OF_PIPE_INCR_DE", "value": 11},
|
|
{"name": "END_OF_PIPE_IB_END", "value": 12},
|
|
{"name": "RST_PIX_CNT", "value": 13},
|
|
{"name": "BREAK_BATCH", "value": 14},
|
|
{"name": "VS_PARTIAL_FLUSH", "value": 15},
|
|
{"name": "PS_PARTIAL_FLUSH", "value": 16},
|
|
{"name": "FLUSH_HS_OUTPUT", "value": 17},
|
|
{"name": "FLUSH_DFSM", "value": 18},
|
|
{"name": "RESET_TO_LOWEST_VGT", "value": 19},
|
|
{"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
|
|
{"name": "WAIT_SYNC", "value": 21},
|
|
{"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
|
|
{"name": "PERFCOUNTER_START", "value": 23},
|
|
{"name": "PERFCOUNTER_STOP", "value": 24},
|
|
{"name": "PIPELINESTAT_START", "value": 25},
|
|
{"name": "PIPELINESTAT_STOP", "value": 26},
|
|
{"name": "PERFCOUNTER_SAMPLE", "value": 27},
|
|
{"name": "FLUSH_ES_OUTPUT", "value": 28},
|
|
{"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
|
|
{"name": "SAMPLE_PIPELINESTAT", "value": 30},
|
|
{"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
|
|
{"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
|
|
{"name": "RESET_VTX_CNT", "value": 33},
|
|
{"name": "BLOCK_CONTEXT_DONE", "value": 34},
|
|
{"name": "CS_CONTEXT_DONE", "value": 35},
|
|
{"name": "VGT_FLUSH", "value": 36},
|
|
{"name": "TGID_ROLLOVER", "value": 37},
|
|
{"name": "SQ_NON_EVENT", "value": 38},
|
|
{"name": "SC_SEND_DB_VPZ", "value": 39},
|
|
{"name": "BOTTOM_OF_PIPE_TS", "value": 40},
|
|
{"name": "FLUSH_SX_TS", "value": 41},
|
|
{"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
|
|
{"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
|
|
{"name": "FLUSH_AND_INV_DB_META", "value": 44},
|
|
{"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
|
|
{"name": "FLUSH_AND_INV_CB_META", "value": 46},
|
|
{"name": "CS_DONE", "value": 47},
|
|
{"name": "PS_DONE", "value": 48},
|
|
{"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
|
|
{"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
|
|
{"name": "THREAD_TRACE_START", "value": 51},
|
|
{"name": "THREAD_TRACE_STOP", "value": 52},
|
|
{"name": "THREAD_TRACE_MARKER", "value": 53},
|
|
{"name": "THREAD_TRACE_DRAW", "value": 54},
|
|
{"name": "THREAD_TRACE_FINISH", "value": 55},
|
|
{"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
|
|
{"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
|
|
{"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
|
|
{"name": "CONTEXT_SUSPEND", "value": 59},
|
|
{"name": "OFFCHIP_HS_DEALLOC", "value": 60},
|
|
{"name": "ENABLE_NGG_PIPELINE", "value": 61},
|
|
{"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
|
|
{"name": "DRAW_DONE", "value": 63}
|
|
]
|
|
}
|
|
},
|
|
"register_mappings": [
|
|
{
|
|
"comment": "This is at offset 0x415 instead of 0x414 due to a conflict with SQ_WAVE_GPR_ALLOC",
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81"],
|
|
"map": {"at": 1045, "to": "pkt3"},
|
|
"name": "COMMAND",
|
|
"type_ref": "COMMAND"
|
|
},
|
|
{
|
|
"chips": ["gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1045, "to": "pkt3"},
|
|
"name": "COMMAND",
|
|
"type_ref": "COMMAND_gfx9"
|
|
},
|
|
{
|
|
"chips": ["gfx6"],
|
|
"map": {"at": 880, "to": "pkt3"},
|
|
"name": "CONTROL",
|
|
"type_ref": "CONTROL"
|
|
},
|
|
{
|
|
"chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 880, "to": "pkt3"},
|
|
"name": "CONTROL",
|
|
"type_ref": "CONTROL_cik"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1040, "to": "pkt3"},
|
|
"name": "CP_DMA_WORD0",
|
|
"type_ref": "CP_DMA_WORD0"
|
|
},
|
|
{
|
|
"chips": ["gfx6"],
|
|
"map": {"at": 1041, "to": "pkt3"},
|
|
"name": "CP_DMA_WORD1",
|
|
"type_ref": "CP_DMA_WORD1"
|
|
},
|
|
{
|
|
"chips": ["gfx7", "gfx8", "gfx81"],
|
|
"map": {"at": 1041, "to": "pkt3"},
|
|
"name": "CP_DMA_WORD1",
|
|
"type_ref": "CP_DMA_WORD1_cik"
|
|
},
|
|
{
|
|
"chips": ["gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1041, "to": "pkt3"},
|
|
"name": "CP_DMA_WORD1",
|
|
"type_ref": "CP_DMA_WORD1_gfx9"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1042, "to": "pkt3"},
|
|
"name": "CP_DMA_WORD2",
|
|
"type_ref": "CP_DMA_WORD2"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1043, "to": "pkt3"},
|
|
"name": "CP_DMA_WORD3",
|
|
"type_ref": "CP_DMA_WORD3"
|
|
},
|
|
{
|
|
"chips": ["gfx6"],
|
|
"map": {"at": 1280, "to": "pkt3"},
|
|
"name": "DMA_DATA_WORD0",
|
|
"type_ref": "DMA_DATA_WORD0"
|
|
},
|
|
{
|
|
"chips": ["gfx7", "gfx8", "gfx81"],
|
|
"map": {"at": 1280, "to": "pkt3"},
|
|
"name": "DMA_DATA_WORD0",
|
|
"type_ref": "DMA_DATA_WORD0_cik"
|
|
},
|
|
{
|
|
"chips": ["gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1280, "to": "pkt3"},
|
|
"name": "DMA_DATA_WORD0",
|
|
"type_ref": "DMA_DATA_WORD0_gfx9"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 882, "to": "pkt3"},
|
|
"name": "DST_ADDR_HI"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1284, "to": "pkt3"},
|
|
"name": "DST_ADDR_HI"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 881, "to": "pkt3"},
|
|
"name": "DST_ADDR_LO"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1283, "to": "pkt3"},
|
|
"name": "DST_ADDR_LO"
|
|
},
|
|
{
|
|
"chips": ["gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1414, "to": "pkt3"},
|
|
"name": "GCR_CNTL",
|
|
"type_ref": "GCR_CNTL"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1009, "to": "pkt3"},
|
|
"name": "IB_BASE_HI"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1008, "to": "pkt3"},
|
|
"name": "IB_BASE_LO"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1010, "to": "pkt3"},
|
|
"name": "IB_CONTROL",
|
|
"type_ref": "IB_CONTROL"
|
|
},
|
|
{
|
|
"chips": ["gfx10", "gfx103"],
|
|
"map": {"at": 1168, "to": "pkt3"},
|
|
"name": "RELEASE_MEM_OP",
|
|
"type_ref": "RELEASE_MEM_OP"
|
|
},
|
|
{
|
|
"chips": ["gfx11"],
|
|
"map": {"at": 1168, "to": "pkt3"},
|
|
"name": "RELEASE_MEM_OP",
|
|
"type_ref": "RELEASE_MEM_OP_gfx11"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1282, "to": "pkt3"},
|
|
"name": "SRC_ADDR_HI"
|
|
},
|
|
{
|
|
"chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103", "gfx11"],
|
|
"map": {"at": 1281, "to": "pkt3"},
|
|
"name": "SRC_ADDR_LO"
|
|
},
|
|
{
|
|
"chips": ["gfx11"],
|
|
"map": {"at": 1408, "to": "pkt3"},
|
|
"name": "ACQUIRE_MEM_PWS_2",
|
|
"type_ref": "ACQUIRE_MEM_PWS_2"
|
|
},
|
|
{
|
|
"chips": ["gfx11"],
|
|
"map": {"at": 1413, "to": "pkt3"},
|
|
"name": "ACQUIRE_MEM_PWS_7",
|
|
"type_ref": "ACQUIRE_MEM_PWS_7"
|
|
}
|
|
],
|
|
"register_types": {
|
|
"COMMAND": {
|
|
"fields": [
|
|
{"bits": [0, 20], "name": "BYTE_COUNT"},
|
|
{"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"},
|
|
{"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"},
|
|
{"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"},
|
|
{"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
|
|
{"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
|
|
{"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
|
|
{"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
|
|
{"bits": [30, 30], "name": "RAW_WAIT"}
|
|
]
|
|
},
|
|
"COMMAND_gfx9": {
|
|
"fields": [
|
|
{"bits": [0, 25], "name": "BYTE_COUNT"},
|
|
{"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
|
|
{"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
|
|
{"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
|
|
{"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
|
|
{"bits": [30, 30], "name": "RAW_WAIT"},
|
|
{"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"}
|
|
]
|
|
},
|
|
"CONTROL": {
|
|
"fields": [
|
|
{"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"},
|
|
{"bits": [16, 16], "name": "WR_ONE_ADDR"},
|
|
{"bits": [20, 20], "name": "WR_CONFIRM"},
|
|
{"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
|
|
]
|
|
},
|
|
"CONTROL_cik": {
|
|
"fields": [
|
|
{"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"},
|
|
{"bits": [16, 16], "name": "WR_ONE_ADDR"},
|
|
{"bits": [20, 20], "name": "WR_CONFIRM"},
|
|
{"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
|
|
]
|
|
},
|
|
"CP_DMA_WORD0": {
|
|
"fields": [
|
|
{"bits": [0, 31], "name": "SRC_ADDR_LO"}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1": {
|
|
"fields": [
|
|
{"bits": [0, 15], "name": "SRC_ADDR_HI"},
|
|
{"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
|
|
{"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
|
|
{"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
|
|
{"bits": [31, 31], "name": "CP_SYNC"}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1_cik": {
|
|
"fields": [
|
|
{"bits": [0, 15], "name": "SRC_ADDR_HI"},
|
|
{"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
|
|
{"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
|
|
{"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
|
|
{"bits": [31, 31], "name": "CP_SYNC"}
|
|
]
|
|
},
|
|
"CP_DMA_WORD1_gfx9": {
|
|
"fields": [
|
|
{"bits": [0, 15], "name": "SRC_ADDR_HI"},
|
|
{"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
|
|
{"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
|
|
{"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
|
|
{"bits": [31, 31], "name": "CP_SYNC"}
|
|
]
|
|
},
|
|
"CP_DMA_WORD2": {
|
|
"fields": [
|
|
{"bits": [0, 31], "name": "DST_ADDR_LO"}
|
|
]
|
|
},
|
|
"CP_DMA_WORD3": {
|
|
"fields": [
|
|
{"bits": [0, 15], "name": "DST_ADDR_HI"}
|
|
]
|
|
},
|
|
"DMA_DATA_WORD0": {
|
|
"fields": [
|
|
{"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
|
|
{"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
|
|
{"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
|
|
{"bits": [31, 31], "name": "CP_SYNC"}
|
|
]
|
|
},
|
|
"DMA_DATA_WORD0_cik": {
|
|
"fields": [
|
|
{"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
|
|
{"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
|
|
{"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
|
|
{"bits": [25, 26], "name": "DST_CACHE_POLICY"},
|
|
{"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
|
|
{"bits": [31, 31], "name": "CP_SYNC"}
|
|
]
|
|
},
|
|
"DMA_DATA_WORD0_gfx9": {
|
|
"fields": [
|
|
{"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
|
|
{"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
|
|
{"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
|
|
{"bits": [25, 26], "name": "DST_CACHE_POLICY"},
|
|
{"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
|
|
{"bits": [31, 31], "name": "CP_SYNC"}
|
|
]
|
|
},
|
|
"GCR_CNTL": {
|
|
"fields": [
|
|
{"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"},
|
|
{"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"},
|
|
{"bits": [4, 4], "name": "GLM_WB"},
|
|
{"bits": [5, 5], "name": "GLM_INV"},
|
|
{"bits": [6, 6], "name": "GLK_WB"},
|
|
{"bits": [7, 7], "name": "GLK_INV"},
|
|
{"bits": [8, 8], "name": "GLV_INV"},
|
|
{"bits": [9, 9], "name": "GL1_INV"},
|
|
{"bits": [10, 10], "name": "GL2_US"},
|
|
{"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
|
|
{"bits": [13, 13], "name": "GL2_DISCARD"},
|
|
{"bits": [14, 14], "name": "GL2_INV"},
|
|
{"bits": [15, 15], "name": "GL2_WB"},
|
|
{"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
|
|
{"bits": [18, 18], "name": "RANGE_IS_PA"}
|
|
]
|
|
},
|
|
"IB_CONTROL": {
|
|
"fields": [
|
|
{"bits": [0, 19], "name": "IB_SIZE"},
|
|
{"bits": [20, 20], "name": "CHAIN"},
|
|
{"bits": [23, 23], "name": "VALID"}
|
|
]
|
|
},
|
|
"RELEASE_MEM_OP": {
|
|
"fields": [
|
|
{"bits": [0, 5], "name": "EVENT_TYPE"},
|
|
{"bits": [8, 11], "name": "EVENT_INDEX"},
|
|
{"bits": [12, 12], "name": "GLM_WB"},
|
|
{"bits": [13, 13], "name": "GLM_INV"},
|
|
{"bits": [14, 14], "name": "GLV_INV"},
|
|
{"bits": [15, 15], "name": "GL1_INV"},
|
|
{"bits": [16, 16], "name": "GL2_US"},
|
|
{"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
|
|
{"bits": [19, 19], "name": "GL2_DISCARD"},
|
|
{"bits": [20, 20], "name": "GL2_INV"},
|
|
{"bits": [21, 21], "name": "GL2_WB"},
|
|
{"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}
|
|
]
|
|
},
|
|
"RELEASE_MEM_OP_gfx11": {
|
|
"fields": [
|
|
{"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE_gfx11", "name": "EVENT_TYPE"},
|
|
{"bits": [7, 7], "name": "WAIT_SYNC"},
|
|
{"bits": [8, 11], "name": "EVENT_INDEX"},
|
|
{"bits": [12, 12], "name": "GLM_WB"},
|
|
{"bits": [13, 13], "name": "GLM_INV"},
|
|
{"bits": [14, 14], "name": "GLV_INV"},
|
|
{"bits": [15, 15], "name": "GL1_INV"},
|
|
{"bits": [16, 16], "name": "GL2_US"},
|
|
{"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
|
|
{"bits": [19, 19], "name": "GL2_DISCARD"},
|
|
{"bits": [20, 20], "name": "GL2_INV"},
|
|
{"bits": [21, 21], "name": "GL2_WB"},
|
|
{"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"},
|
|
{"bits": [24, 24], "name": "GLK_WB"},
|
|
{"bits": [25, 26], "name": "CACHE_POLICY"},
|
|
{"bits": [28, 29], "name": "EXECUTE"},
|
|
{"bits": [30, 30], "name": "GLK_INV"},
|
|
{"bits": [31, 31], "name": "PWS_ENABLE"}
|
|
]
|
|
},
|
|
"ACQUIRE_MEM_PWS_2": {
|
|
"fields": [
|
|
{"bits": [11, 13], "enum_ref": "PWS_STAGE_SEL", "name": "PWS_STAGE_SEL"},
|
|
{"bits": [14, 15], "enum_ref": "PWS_COUNTER_SEL", "name": "PWS_COUNTER_SEL"},
|
|
{"bits": [17, 17], "name": "PWS_ENA2"},
|
|
{"bits": [18, 23], "name": "PWS_COUNT"}
|
|
]
|
|
},
|
|
"ACQUIRE_MEM_PWS_7": {
|
|
"fields": [
|
|
{"bits": [31, 31], "name": "PWS_ENA"}
|
|
]
|
|
}
|
|
}
|
|
}
|