586 lines
19 KiB
C++
586 lines
19 KiB
C++
/*
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* Copyright © 2021 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <stdio.h>
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#include <stdarg.h>
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#include "common/intel_gem.h"
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#include "perf/intel_perf.h"
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#include "util/hash_table.h"
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#include "util/u_process.h"
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#include "intel_driver_ds.h"
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#include "intel_pps_priv.h"
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#include "intel_tracepoints.h"
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#ifdef HAVE_PERFETTO
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#include "util/u_perfetto.h"
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#include "intel_tracepoints_perfetto.h"
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/* Just naming stages */
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static const struct {
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const char *name;
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/* Tells us if a given stage is pipelined. This is used to build stacks of
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* pipelined elements so that the perfetto UI doesn't get confused by elements
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* ending out of order.
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*/
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bool pipelined;
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/* The perfetto UI requires that there is a parent-child relationship
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* within a row of elements. Which means that all children elements must
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* end within the lifespan of their parent.
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*
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* Some elements like stalls and command buffers follow that relationship,
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* but not all. This tells us in which UI row the elements should live.
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*/
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enum intel_ds_queue_stage draw_stage;
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} intel_queue_stage_desc[INTEL_DS_QUEUE_STAGE_N_STAGES] = {
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/* Order must match the enum! */
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{
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"cmd-buffer",
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false,
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INTEL_DS_QUEUE_STAGE_CMD_BUFFER,
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},
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{
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"stall",
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false,
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INTEL_DS_QUEUE_STAGE_STALL,
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},
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{
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"compute",
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true,
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INTEL_DS_QUEUE_STAGE_COMPUTE,
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},
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{
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"render-pass",
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true,
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INTEL_DS_QUEUE_STAGE_RENDER_PASS,
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},
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{
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"blorp",
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true,
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INTEL_DS_QUEUE_STAGE_BLORP,
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},
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{
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"draw",
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true,
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INTEL_DS_QUEUE_STAGE_DRAW,
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},
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};
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struct IntelRenderpassIncrementalState {
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bool was_cleared = true;
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};
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struct IntelRenderpassTraits : public perfetto::DefaultDataSourceTraits {
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using IncrementalStateType = IntelRenderpassIncrementalState;
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};
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class IntelRenderpassDataSource : public perfetto::DataSource<IntelRenderpassDataSource,
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IntelRenderpassTraits> {
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public:
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void OnSetup(const SetupArgs &) override
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{
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// Use this callback to apply any custom configuration to your data source
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// based on the TraceConfig in SetupArgs.
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}
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void OnStart(const StartArgs &) override
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{
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// This notification can be used to initialize the GPU driver, enable
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// counters, etc. StartArgs will contains the DataSourceDescriptor,
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// which can be extended.
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u_trace_perfetto_start();
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PERFETTO_LOG("Tracing started");
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}
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void OnStop(const StopArgs &) override
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{
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PERFETTO_LOG("Tracing stopped");
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// Undo any initialization done in OnStart.
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u_trace_perfetto_stop();
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// TODO we should perhaps block until queued traces are flushed?
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Trace([](IntelRenderpassDataSource::TraceContext ctx) {
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auto packet = ctx.NewTracePacket();
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packet->Finalize();
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ctx.Flush();
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});
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}
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};
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PERFETTO_DECLARE_DATA_SOURCE_STATIC_MEMBERS(IntelRenderpassDataSource);
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PERFETTO_DEFINE_DATA_SOURCE_STATIC_MEMBERS(IntelRenderpassDataSource);
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using perfetto::protos::pbzero::InternedGpuRenderStageSpecification_RenderStageCategory;
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enum InternedGpuRenderStageSpecification_RenderStageCategory
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i915_engine_class_to_category(enum drm_i915_gem_engine_class engine_class)
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{
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switch (engine_class) {
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case I915_ENGINE_CLASS_RENDER:
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return InternedGpuRenderStageSpecification_RenderStageCategory::
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InternedGpuRenderStageSpecification_RenderStageCategory_GRAPHICS;
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default:
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return InternedGpuRenderStageSpecification_RenderStageCategory::InternedGpuRenderStageSpecification_RenderStageCategory_OTHER;
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}
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}
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static void
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sync_timestamp(IntelRenderpassDataSource::TraceContext &ctx,
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struct intel_ds_device *device)
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{
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uint64_t cpu_ts = perfetto::base::GetBootTimeNs().count();
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uint64_t gpu_ts = intel_device_info_timebase_scale(&device->info,
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intel_read_gpu_timestamp(device->fd));
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if (cpu_ts < device->next_clock_sync_ns)
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return;
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PERFETTO_LOG("sending clocks gpu=0x%08x", device->gpu_clock_id);
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device->sync_gpu_ts = gpu_ts;
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device->next_clock_sync_ns = cpu_ts + 1000000000ull;
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auto packet = ctx.NewTracePacket();
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packet->set_timestamp_clock_id(perfetto::protos::pbzero::BUILTIN_CLOCK_BOOTTIME);
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packet->set_timestamp(cpu_ts);
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auto event = packet->set_clock_snapshot();
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{
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auto clock = event->add_clocks();
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clock->set_clock_id(perfetto::protos::pbzero::BUILTIN_CLOCK_BOOTTIME);
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clock->set_timestamp(cpu_ts);
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}
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{
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auto clock = event->add_clocks();
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clock->set_clock_id(device->gpu_clock_id);
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clock->set_timestamp(gpu_ts);
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}
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}
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static void
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send_descriptors(IntelRenderpassDataSource::TraceContext &ctx,
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struct intel_ds_device *device)
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{
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struct intel_ds_queue *queue;
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PERFETTO_LOG("Sending renderstage descriptors");
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device->event_id = 0;
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u_vector_foreach(queue, &device->queues) {
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for (uint32_t s = 0; s < ARRAY_SIZE(queue->stages); s++) {
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queue->stages[s].start_ns = 0;
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}
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}
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{
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auto packet = ctx.NewTracePacket();
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packet->set_timestamp(perfetto::base::GetBootTimeNs().count());
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packet->set_timestamp_clock_id(perfetto::protos::pbzero::BUILTIN_CLOCK_BOOTTIME);
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packet->set_sequence_flags(perfetto::protos::pbzero::TracePacket::SEQ_INCREMENTAL_STATE_CLEARED);
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auto interned_data = packet->set_interned_data();
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{
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auto desc = interned_data->add_graphics_contexts();
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desc->set_iid(device->iid);
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desc->set_pid(getpid());
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switch (device->api) {
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case INTEL_DS_API_OPENGL:
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desc->set_api(perfetto::protos::pbzero::InternedGraphicsContext_Api_OPEN_GL);
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break;
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case INTEL_DS_API_VULKAN:
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desc->set_api(perfetto::protos::pbzero::InternedGraphicsContext_Api_VULKAN);
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break;
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default:
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break;
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}
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}
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/* Emit all the IID picked at device/queue creation. */
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u_vector_foreach(queue, &device->queues) {
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for (unsigned s = 0; s < INTEL_DS_QUEUE_STAGE_N_STAGES; s++) {
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{
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/* We put the stage number in there so that all rows are order
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* by intel_ds_queue_stage.
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*/
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char name[100];
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snprintf(name, sizeof(name), "%.10s-%s-%u-%s",
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util_get_process_name(),
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queue->name, s, intel_queue_stage_desc[s].name);
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auto desc = interned_data->add_gpu_specifications();
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desc->set_iid(queue->stages[s].queue_iid);
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desc->set_name(name);
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}
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{
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auto desc = interned_data->add_gpu_specifications();
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desc->set_iid(queue->stages[s].stage_iid);
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desc->set_name(intel_queue_stage_desc[s].name);
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}
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}
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}
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}
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device->next_clock_sync_ns = 0;
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sync_timestamp(ctx, device);
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}
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typedef void (*trace_payload_as_extra_func)(perfetto::protos::pbzero::GpuRenderStageEvent *, const void*);
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static void
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begin_event(struct intel_ds_queue *queue, uint64_t ts_ns,
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enum intel_ds_queue_stage stage_id)
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{
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/* If we haven't managed to calibrate the alignment between GPU and CPU
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* timestamps yet, then skip this trace, otherwise perfetto won't know
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* what to do with it.
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*/
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if (!queue->device->sync_gpu_ts) {
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queue->stages[stage_id].start_ns = 0;
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return;
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}
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queue->stages[stage_id].start_ns = ts_ns;
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}
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static void
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end_event(struct intel_ds_queue *queue, uint64_t ts_ns,
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enum intel_ds_queue_stage stage_id,
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uint32_t submission_id, const void* payload = nullptr,
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trace_payload_as_extra_func payload_as_extra = nullptr)
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{
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struct intel_ds_device *device = queue->device;
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/* If we haven't managed to calibrate the alignment between GPU and CPU
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* timestamps yet, then skip this trace, otherwise perfetto won't know
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* what to do with it.
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*/
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if (!device->sync_gpu_ts)
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return;
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struct intel_ds_stage *stage = &queue->stages[stage_id];
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uint64_t start_ns = stage->start_ns;
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if (!start_ns)
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return;
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uint64_t evt_id = device->event_id++;
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IntelRenderpassDataSource::Trace([=](IntelRenderpassDataSource::TraceContext tctx) {
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if (auto state = tctx.GetIncrementalState(); state->was_cleared) {
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send_descriptors(tctx, queue->device);
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state->was_cleared = false;
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}
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sync_timestamp(tctx, queue->device);
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auto packet = tctx.NewTracePacket();
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packet->set_timestamp(start_ns);
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packet->set_timestamp_clock_id(queue->device->gpu_clock_id);
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assert(ts_ns >= start_ns);
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auto event = packet->set_gpu_render_stage_event();
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event->set_gpu_id(queue->device->gpu_id);
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event->set_hw_queue_iid(stage->queue_iid);
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event->set_stage_iid(stage->stage_iid);
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event->set_context(queue->device->iid);
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event->set_event_id(evt_id);
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event->set_duration(ts_ns - start_ns);
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event->set_submission_id(submission_id);
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if (payload && payload_as_extra) {
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payload_as_extra(event, payload);
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}
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});
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stage->start_ns = 0;
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}
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static void
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custom_trace_payload_as_extra_end_stall(perfetto::protos::pbzero::GpuRenderStageEvent *event,
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const struct trace_intel_end_stall *payload)
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{
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char buf[256];
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{
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auto data = event->add_extra_data();
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data->set_name("stall_reason");
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snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s : %s",
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(payload->flags & INTEL_DS_DEPTH_CACHE_FLUSH_BIT) ? "+depth_flush" : "",
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(payload->flags & INTEL_DS_DATA_CACHE_FLUSH_BIT) ? "+dc_flush" : "",
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(payload->flags & INTEL_DS_HDC_PIPELINE_FLUSH_BIT) ? "+hdc_flush" : "",
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(payload->flags & INTEL_DS_RENDER_TARGET_CACHE_FLUSH_BIT) ? "+rt_flush" : "",
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(payload->flags & INTEL_DS_TILE_CACHE_FLUSH_BIT) ? "+tile_flush" : "",
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(payload->flags & INTEL_DS_STATE_CACHE_INVALIDATE_BIT) ? "+state_inv" : "",
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(payload->flags & INTEL_DS_CONST_CACHE_INVALIDATE_BIT) ? "+const_inv" : "",
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(payload->flags & INTEL_DS_VF_CACHE_INVALIDATE_BIT) ? "+vf_inv" : "",
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(payload->flags & INTEL_DS_TEXTURE_CACHE_INVALIDATE_BIT) ? "+tex_inv" : "",
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(payload->flags & INTEL_DS_INST_CACHE_INVALIDATE_BIT) ? "+inst_inv" : "",
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(payload->flags & INTEL_DS_STALL_AT_SCOREBOARD_BIT) ? "+pb_stall" : "",
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(payload->flags & INTEL_DS_DEPTH_STALL_BIT) ? "+depth_stall" : "",
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(payload->flags & INTEL_DS_HDC_PIPELINE_FLUSH_BIT) ? "+hdc_flush" : "",
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(payload->flags & INTEL_DS_CS_STALL_BIT) ? "+cs_stall" : "",
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payload->reason ? payload->reason : "unknown");
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assert(strlen(buf) > 0);
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data->set_value(buf);
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}
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}
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#endif /* HAVE_PERFETTO */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef HAVE_PERFETTO
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/*
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* Trace callbacks, called from u_trace once the timestamps from GPU have been
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* collected.
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*/
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#define CREATE_DUAL_EVENT_CALLBACK(event_name, stage) \
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void \
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intel_ds_begin_##event_name(struct intel_ds_device *device, \
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uint64_t ts_ns, \
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const void *flush_data, \
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const struct trace_intel_begin_##event_name *payload) \
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{ \
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const struct intel_ds_flush_data *flush = \
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(const struct intel_ds_flush_data *) flush_data; \
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begin_event(flush->queue, ts_ns, stage); \
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} \
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\
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void \
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intel_ds_end_##event_name(struct intel_ds_device *device, \
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uint64_t ts_ns, \
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const void *flush_data, \
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const struct trace_intel_end_##event_name *payload) \
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{ \
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const struct intel_ds_flush_data *flush = \
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(const struct intel_ds_flush_data *) flush_data; \
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end_event(flush->queue, ts_ns, stage, flush->submission_id, \
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payload, \
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(trace_payload_as_extra_func) \
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&trace_payload_as_extra_intel_end_##event_name); \
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} \
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CREATE_DUAL_EVENT_CALLBACK(cmd_buffer, INTEL_DS_QUEUE_STAGE_CMD_BUFFER)
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CREATE_DUAL_EVENT_CALLBACK(render_pass, INTEL_DS_QUEUE_STAGE_RENDER_PASS)
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CREATE_DUAL_EVENT_CALLBACK(blorp, INTEL_DS_QUEUE_STAGE_BLORP)
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CREATE_DUAL_EVENT_CALLBACK(draw, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(draw_indexed, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(draw_indexed_multi, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(draw_indexed_indirect, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(draw_multi, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(draw_indirect, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(draw_indirect_count, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(draw_indirect_byte_count, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(draw_indexed_indirect_count, INTEL_DS_QUEUE_STAGE_DRAW)
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CREATE_DUAL_EVENT_CALLBACK(compute, INTEL_DS_QUEUE_STAGE_COMPUTE)
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void
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intel_ds_begin_stall(struct intel_ds_device *device,
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uint64_t ts_ns,
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const void *flush_data,
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const struct trace_intel_begin_stall *payload)
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{
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const struct intel_ds_flush_data *flush =
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(const struct intel_ds_flush_data *) flush_data;
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begin_event(flush->queue, ts_ns, INTEL_DS_QUEUE_STAGE_STALL);
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}
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void
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intel_ds_end_stall(struct intel_ds_device *device,
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uint64_t ts_ns,
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const void *flush_data,
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const struct trace_intel_end_stall *payload)
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{
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const struct intel_ds_flush_data *flush =
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(const struct intel_ds_flush_data *) flush_data;
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end_event(flush->queue, ts_ns, INTEL_DS_QUEUE_STAGE_STALL, flush->submission_id,
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payload,
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(trace_payload_as_extra_func)custom_trace_payload_as_extra_end_stall);
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}
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uint64_t
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intel_ds_begin_submit(struct intel_ds_queue *queue)
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{
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return perfetto::base::GetBootTimeNs().count();
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}
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void
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intel_ds_end_submit(struct intel_ds_queue *queue,
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uint64_t start_ts)
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{
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if (!u_trace_context_actively_tracing(&queue->device->trace_context)) {
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queue->device->sync_gpu_ts = 0;
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queue->device->next_clock_sync_ns = 0;
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return;
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}
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uint64_t end_ts = perfetto::base::GetBootTimeNs().count();
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uint32_t submission_id = queue->submission_id++;
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IntelRenderpassDataSource::Trace([=](IntelRenderpassDataSource::TraceContext tctx) {
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if (auto state = tctx.GetIncrementalState(); state->was_cleared) {
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send_descriptors(tctx, queue->device);
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state->was_cleared = false;
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}
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sync_timestamp(tctx, queue->device);
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auto packet = tctx.NewTracePacket();
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packet->set_timestamp(start_ts);
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auto event = packet->set_vulkan_api_event();
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auto submit = event->set_vk_queue_submit();
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// submit->set_pid(os_get_pid());
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// submit->set_tid(os_get_tid());
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submit->set_duration_ns(end_ts - start_ts);
|
|
submit->set_vk_queue((uintptr_t) queue);
|
|
submit->set_submission_id(submission_id);
|
|
});
|
|
}
|
|
|
|
#endif /* HAVE_PERFETTO */
|
|
|
|
static void
|
|
intel_driver_ds_init_once(void)
|
|
{
|
|
#ifdef HAVE_PERFETTO
|
|
util_perfetto_init();
|
|
perfetto::DataSourceDescriptor dsd;
|
|
dsd.set_name("gpu.renderstages.intel");
|
|
IntelRenderpassDataSource::Register(dsd);
|
|
#endif
|
|
}
|
|
|
|
static once_flag intel_driver_ds_once_flag = ONCE_FLAG_INIT;
|
|
|
|
static uint64_t get_iid()
|
|
{
|
|
static uint64_t iid = 1;
|
|
return iid++;
|
|
}
|
|
|
|
void
|
|
intel_driver_ds_init(void)
|
|
{
|
|
call_once(&intel_driver_ds_once_flag,
|
|
intel_driver_ds_init_once);
|
|
}
|
|
|
|
void
|
|
intel_ds_device_init(struct intel_ds_device *device,
|
|
struct intel_device_info *devinfo,
|
|
int drm_fd,
|
|
uint32_t gpu_id,
|
|
enum intel_ds_api api)
|
|
{
|
|
memset(device, 0, sizeof(*device));
|
|
|
|
assert(gpu_id < 128);
|
|
device->gpu_id = gpu_id;
|
|
device->gpu_clock_id = intel_pps_clock_id(gpu_id);
|
|
device->fd = drm_fd;
|
|
device->info = *devinfo;
|
|
device->iid = get_iid();
|
|
device->api = api;
|
|
u_vector_init(&device->queues, 4, sizeof(struct intel_ds_queue));
|
|
}
|
|
|
|
void
|
|
intel_ds_device_fini(struct intel_ds_device *device)
|
|
{
|
|
u_trace_context_fini(&device->trace_context);
|
|
u_vector_finish(&device->queues);
|
|
}
|
|
|
|
struct intel_ds_queue *
|
|
intel_ds_device_add_queue(struct intel_ds_device *device,
|
|
const char *fmt_name,
|
|
...)
|
|
{
|
|
struct intel_ds_queue *queue =
|
|
(struct intel_ds_queue *) u_vector_add(&device->queues);
|
|
va_list ap;
|
|
|
|
memset(queue, 0, sizeof(*queue));
|
|
|
|
queue->device = device;
|
|
queue->queue_id = u_vector_length(&device->queues) - 1;
|
|
|
|
va_start(ap, fmt_name);
|
|
vsnprintf(queue->name, sizeof(queue->name), fmt_name, ap);
|
|
va_end(ap);
|
|
|
|
for (unsigned s = 0; s < INTEL_DS_QUEUE_STAGE_N_STAGES; s++) {
|
|
queue->stages[s].queue_iid = get_iid();
|
|
queue->stages[s].stage_iid = get_iid();
|
|
}
|
|
|
|
return queue;
|
|
}
|
|
|
|
void intel_ds_flush_data_init(struct intel_ds_flush_data *data,
|
|
struct intel_ds_queue *queue,
|
|
uint64_t submission_id)
|
|
{
|
|
memset(data, 0, sizeof(*data));
|
|
|
|
data->queue = queue;
|
|
data->submission_id = submission_id;
|
|
|
|
u_trace_init(&data->trace, &queue->device->trace_context);
|
|
}
|
|
|
|
void intel_ds_flush_data_fini(struct intel_ds_flush_data *data)
|
|
{
|
|
u_trace_fini(&data->trace);
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|