201 lines
6.1 KiB
C
201 lines
6.1 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Tom Stellard <thomas.stellard@amd.com>
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* Michel Dänzer <michel.daenzer@amd.com>
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* Christian König <christian.koenig@amd.com>
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*/
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#ifndef SI_SHADER_H
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#define SI_SHADER_H
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#include <llvm-c/Core.h> /* LLVMModuleRef */
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#include "tgsi/tgsi_scan.h"
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#include "si_state.h"
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struct radeon_shader_binary;
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struct radeon_shader_reloc;
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#define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
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#define SI_SGPR_CONST 2
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#define SI_SGPR_SAMPLER 4
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#define SI_SGPR_RESOURCE 6
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#define SI_SGPR_VERTEX_BUFFER 8 /* VS only */
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#define SI_SGPR_BASE_VERTEX 10 /* VS only */
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#define SI_SGPR_START_INSTANCE 11 /* VS only */
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#define SI_SGPR_ALPHA_REF 8 /* PS only */
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#define SI_VS_NUM_USER_SGPR 12
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#define SI_GS_NUM_USER_SGPR 8
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#define SI_GSCOPY_NUM_USER_SGPR 4
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#define SI_PS_NUM_USER_SGPR 9
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/* LLVM function parameter indices */
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#define SI_PARAM_RW_BUFFERS 0
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#define SI_PARAM_CONST 1
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#define SI_PARAM_SAMPLER 2
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#define SI_PARAM_RESOURCE 3
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/* VS only parameters */
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#define SI_PARAM_VERTEX_BUFFER 4
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#define SI_PARAM_BASE_VERTEX 5
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#define SI_PARAM_START_INSTANCE 6
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/* the other VS parameters are assigned dynamically */
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/* ES only parameters */
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#define SI_PARAM_ES2GS_OFFSET 7
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/* GS only parameters */
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#define SI_PARAM_GS2VS_OFFSET 4
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#define SI_PARAM_GS_WAVE_ID 5
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#define SI_PARAM_VTX0_OFFSET 6
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#define SI_PARAM_VTX1_OFFSET 7
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#define SI_PARAM_PRIMITIVE_ID 8
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#define SI_PARAM_VTX2_OFFSET 9
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#define SI_PARAM_VTX3_OFFSET 10
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#define SI_PARAM_VTX4_OFFSET 11
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#define SI_PARAM_VTX5_OFFSET 12
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#define SI_PARAM_GS_INSTANCE_ID 13
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/* PS only parameters */
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#define SI_PARAM_ALPHA_REF 4
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#define SI_PARAM_PRIM_MASK 5
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#define SI_PARAM_PERSP_SAMPLE 6
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#define SI_PARAM_PERSP_CENTER 7
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#define SI_PARAM_PERSP_CENTROID 8
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#define SI_PARAM_PERSP_PULL_MODEL 9
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#define SI_PARAM_LINEAR_SAMPLE 10
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#define SI_PARAM_LINEAR_CENTER 11
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#define SI_PARAM_LINEAR_CENTROID 12
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#define SI_PARAM_LINE_STIPPLE_TEX 13
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#define SI_PARAM_POS_X_FLOAT 14
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#define SI_PARAM_POS_Y_FLOAT 15
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#define SI_PARAM_POS_Z_FLOAT 16
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#define SI_PARAM_POS_W_FLOAT 17
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#define SI_PARAM_FRONT_FACE 18
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#define SI_PARAM_ANCILLARY 19
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#define SI_PARAM_SAMPLE_COVERAGE 20
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#define SI_PARAM_POS_FIXED_PT 21
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#define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
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struct si_shader;
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struct si_shader_selector {
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struct si_shader *current;
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struct tgsi_token *tokens;
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struct pipe_stream_output_info so;
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struct tgsi_shader_info info;
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unsigned num_shaders;
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/* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
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unsigned type;
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unsigned gs_output_prim;
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unsigned gs_max_out_vertices;
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uint64_t gs_used_inputs; /* mask of "get_unique_index" bits */
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};
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union si_shader_key {
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struct {
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unsigned export_16bpc:8;
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unsigned last_cbuf:3;
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unsigned color_two_side:1;
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unsigned alpha_func:3;
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unsigned alpha_to_one:1;
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unsigned poly_stipple:1;
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unsigned poly_line_smoothing:1;
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} ps;
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struct {
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unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS];
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/* The mask of "get_unique_index" bits, needed for ES,
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* it describes how the ES->GS ring buffer is laid out. */
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uint64_t gs_used_inputs;
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unsigned as_es:1;
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} vs;
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};
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struct si_shader {
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struct si_shader_selector *selector;
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struct si_shader *next_variant;
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struct si_shader *gs_copy_shader;
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struct si_pm4_state *pm4;
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struct r600_resource *bo;
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struct r600_resource *scratch_bo;
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struct radeon_shader_binary binary;
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unsigned num_sgprs;
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unsigned num_vgprs;
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unsigned lds_size;
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unsigned spi_ps_input_ena;
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unsigned float_mode;
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unsigned scratch_bytes_per_wave;
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unsigned spi_shader_col_format;
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unsigned spi_shader_z_format;
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unsigned db_shader_control;
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unsigned cb_shader_mask;
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union si_shader_key key;
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unsigned nparam;
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unsigned vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
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unsigned ps_input_param_offset[PIPE_MAX_SHADER_INPUTS];
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bool uses_instanceid;
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unsigned nr_pos_exports;
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bool is_gs_copy_shader;
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bool dx10_clamp_mode; /* convert NaNs to 0 */
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};
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static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
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{
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return sctx->gs_shader ? &sctx->gs_shader->info
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: &sctx->vs_shader->info;
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}
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static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
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{
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if (sctx->gs_shader)
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return sctx->gs_shader->current->gs_copy_shader;
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else
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return sctx->vs_shader->current;
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}
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/* radeonsi_shader.c */
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int si_shader_create(struct si_screen *sscreen, struct si_shader *shader);
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int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
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LLVMModuleRef mod);
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void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader);
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unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
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int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader,
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const struct radeon_shader_binary *binary);
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void si_shader_apply_scratch_relocs(struct si_context *sctx,
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struct si_shader *shader,
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uint64_t scratch_va);
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void si_shader_binary_read_config(const struct si_screen *sscreen,
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struct si_shader *shader,
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unsigned symbol_offset);
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#endif
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