590 lines
18 KiB
C
590 lines
18 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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#include "tgsi/tgsi_text.h"
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#include "tgsi/tgsi_ureg.h"
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void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
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unsigned num_layers)
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{
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unsigned vs_blit_property;
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void **vs;
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switch (type) {
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case UTIL_BLITTER_ATTRIB_NONE:
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vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
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&sctx->vs_blit_pos;
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vs_blit_property = SI_VS_BLIT_SGPRS_POS;
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break;
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case UTIL_BLITTER_ATTRIB_COLOR:
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vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
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&sctx->vs_blit_color;
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vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
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break;
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case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
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case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
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assert(num_layers == 1);
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vs = &sctx->vs_blit_texcoord;
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vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
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break;
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default:
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assert(0);
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return NULL;
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}
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if (*vs)
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return *vs;
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struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
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if (!ureg)
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return NULL;
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/* Tell the shader to load VS inputs from SGPRs: */
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ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
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ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
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/* This is just a pass-through shader with 1-3 MOV instructions. */
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ureg_MOV(ureg,
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ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
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ureg_DECL_vs_input(ureg, 0));
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if (type != UTIL_BLITTER_ATTRIB_NONE) {
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ureg_MOV(ureg,
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ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
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ureg_DECL_vs_input(ureg, 1));
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}
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if (num_layers > 1) {
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struct ureg_src instance_id =
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ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
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struct ureg_dst layer =
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ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
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ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
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ureg_scalar(instance_id, TGSI_SWIZZLE_X));
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}
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ureg_END(ureg);
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*vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
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return *vs;
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}
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/**
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* This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
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* VS passes its outputs to TES directly, so the fixed-function shader only
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* has to write TESSOUTER and TESSINNER.
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*/
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void *si_create_fixed_func_tcs(struct si_context *sctx)
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{
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struct ureg_src outer, inner;
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struct ureg_dst tessouter, tessinner;
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struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
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if (!ureg)
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return NULL;
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outer = ureg_DECL_system_value(ureg,
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TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
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inner = ureg_DECL_system_value(ureg,
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TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
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tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
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tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
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ureg_MOV(ureg, tessouter, outer);
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ureg_MOV(ureg, tessinner, inner);
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ureg_END(ureg);
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return ureg_create_shader_and_destroy(ureg, &sctx->b);
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}
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/* Create a compute shader implementing clear_buffer or copy_buffer. */
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void *si_create_dma_compute_shader(struct pipe_context *ctx,
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unsigned num_dwords_per_thread,
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bool dst_stream_cache_policy, bool is_copy)
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{
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assert(util_is_power_of_two_nonzero(num_dwords_per_thread));
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unsigned store_qualifier = TGSI_MEMORY_COHERENT | TGSI_MEMORY_RESTRICT;
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if (dst_stream_cache_policy)
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store_qualifier |= TGSI_MEMORY_STREAM_CACHE_POLICY;
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/* Don't cache loads, because there is no reuse. */
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unsigned load_qualifier = store_qualifier | TGSI_MEMORY_STREAM_CACHE_POLICY;
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unsigned num_mem_ops = MAX2(1, num_dwords_per_thread / 4);
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unsigned *inst_dwords = alloca(num_mem_ops * sizeof(unsigned));
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for (unsigned i = 0; i < num_mem_ops; i++) {
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if (i*4 < num_dwords_per_thread)
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inst_dwords[i] = MIN2(4, num_dwords_per_thread - i*4);
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}
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struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE);
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if (!ureg)
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return NULL;
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ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 64);
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ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1);
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ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1);
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struct ureg_src value;
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if (!is_copy) {
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ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_DWORDS, inst_dwords[0]);
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value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA, 0);
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}
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struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
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struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0);
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struct ureg_dst store_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
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struct ureg_dst load_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
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struct ureg_dst dstbuf = ureg_dst(ureg_DECL_buffer(ureg, 0, false));
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struct ureg_src srcbuf;
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struct ureg_src *values = NULL;
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if (is_copy) {
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srcbuf = ureg_DECL_buffer(ureg, 1, false);
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values = malloc(num_mem_ops * sizeof(struct ureg_src));
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}
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/* If there are multiple stores, the first store writes into 0+tid,
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* the 2nd store writes into 64+tid, the 3rd store writes into 128+tid, etc.
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*/
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ureg_UMAD(ureg, store_addr, blk, ureg_imm1u(ureg, 64 * num_mem_ops), tid);
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/* Convert from a "store size unit" into bytes. */
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ureg_UMUL(ureg, store_addr, ureg_src(store_addr),
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ureg_imm1u(ureg, 4 * inst_dwords[0]));
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ureg_MOV(ureg, load_addr, ureg_src(store_addr));
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/* Distance between a load and a store for latency hiding. */
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unsigned load_store_distance = is_copy ? 8 : 0;
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for (unsigned i = 0; i < num_mem_ops + load_store_distance; i++) {
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int d = i - load_store_distance;
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if (is_copy && i < num_mem_ops) {
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if (i) {
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ureg_UADD(ureg, load_addr, ureg_src(load_addr),
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ureg_imm1u(ureg, 4 * inst_dwords[i] * 64));
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}
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values[i] = ureg_src(ureg_DECL_temporary(ureg));
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struct ureg_dst dst =
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ureg_writemask(ureg_dst(values[i]),
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u_bit_consecutive(0, inst_dwords[i]));
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struct ureg_src srcs[] = {srcbuf, ureg_src(load_addr)};
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ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dst, 1, srcs, 2,
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load_qualifier, TGSI_TEXTURE_BUFFER, 0);
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}
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if (d >= 0) {
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if (d) {
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ureg_UADD(ureg, store_addr, ureg_src(store_addr),
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ureg_imm1u(ureg, 4 * inst_dwords[d] * 64));
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}
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struct ureg_dst dst =
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ureg_writemask(dstbuf, u_bit_consecutive(0, inst_dwords[d]));
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struct ureg_src srcs[] =
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{ureg_src(store_addr), is_copy ? values[d] : value};
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ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst, 1, srcs, 2,
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store_qualifier, TGSI_TEXTURE_BUFFER, 0);
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}
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}
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ureg_END(ureg);
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struct pipe_compute_state state = {};
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state.ir_type = PIPE_SHADER_IR_TGSI;
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state.prog = ureg_get_tokens(ureg, NULL);
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void *cs = ctx->create_compute_state(ctx, &state);
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ureg_destroy(ureg);
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ureg_free_tokens(state.prog);
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free(values);
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return cs;
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}
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/* Create the compute shader that is used to collect the results.
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*
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* One compute grid with a single thread is launched for every query result
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* buffer. The thread (optionally) reads a previous summary buffer, then
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* accumulates data from the query result buffer, and writes the result either
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* to a summary buffer to be consumed by the next grid invocation or to the
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* user-supplied buffer.
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*
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* Data layout:
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*
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* CONST
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* 0.x = end_offset
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* 0.y = result_stride
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* 0.z = result_count
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* 0.w = bit field:
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* 1: read previously accumulated values
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* 2: write accumulated values for chaining
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* 4: write result available
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* 8: convert result to boolean (0/1)
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* 16: only read one dword and use that as result
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* 32: apply timestamp conversion
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* 64: store full 64 bits result
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* 128: store signed 32 bits result
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* 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
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* 1.x = fence_offset
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* 1.y = pair_stride
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* 1.z = pair_count
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*
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* BUFFER[0] = query result buffer
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* BUFFER[1] = previous summary buffer
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* BUFFER[2] = next summary buffer or user-supplied buffer
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*/
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void *si_create_query_result_cs(struct si_context *sctx)
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{
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/* TEMP[0].xy = accumulated result so far
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* TEMP[0].z = result not available
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*
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* TEMP[1].x = current result index
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* TEMP[1].y = current pair index
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*/
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static const char text_tmpl[] =
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"COMP\n"
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"PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
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"PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
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"PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
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"DCL BUFFER[0]\n"
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"DCL BUFFER[1]\n"
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"DCL BUFFER[2]\n"
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"DCL CONST[0][0..1]\n"
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"DCL TEMP[0..5]\n"
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"IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
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"IMM[1] UINT32 {1, 2, 4, 8}\n"
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"IMM[2] UINT32 {16, 32, 64, 128}\n"
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"IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
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"IMM[4] UINT32 {256, 0, 0, 0}\n"
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"AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
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"UIF TEMP[5]\n"
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/* Check result availability. */
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"LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
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"ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
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"MOV TEMP[1], TEMP[0].zzzz\n"
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"NOT TEMP[0].z, TEMP[0].zzzz\n"
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/* Load result if available. */
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"UIF TEMP[1]\n"
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"LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
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"ENDIF\n"
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"ELSE\n"
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/* Load previously accumulated result if requested. */
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"MOV TEMP[0], IMM[0].xxxx\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
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"UIF TEMP[4]\n"
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"LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
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"ENDIF\n"
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"MOV TEMP[1].x, IMM[0].xxxx\n"
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"BGNLOOP\n"
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/* Break if accumulated result so far is not available. */
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"UIF TEMP[0].zzzz\n"
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"BRK\n"
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"ENDIF\n"
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/* Break if result_index >= result_count. */
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"USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
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"UIF TEMP[5]\n"
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"BRK\n"
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"ENDIF\n"
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/* Load fence and check result availability */
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"UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
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"LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
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"ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
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"NOT TEMP[0].z, TEMP[0].zzzz\n"
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"UIF TEMP[0].zzzz\n"
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"BRK\n"
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"ENDIF\n"
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"MOV TEMP[1].y, IMM[0].xxxx\n"
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"BGNLOOP\n"
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/* Load start and end. */
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"UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
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"UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
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"LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
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"UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
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"LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
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"U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
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"AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
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"UIF TEMP[5].zzzz\n"
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/* Load second start/end half-pair and
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* take the difference
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*/
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"UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
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"LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
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"LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
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"U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
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"U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
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"ENDIF\n"
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"U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
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/* Increment pair index */
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"UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
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"USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
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"UIF TEMP[5]\n"
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"BRK\n"
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"ENDIF\n"
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"ENDLOOP\n"
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/* Increment result index */
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"UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
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"ENDLOOP\n"
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"ENDIF\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
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"UIF TEMP[4]\n"
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/* Store accumulated data for chaining. */
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"STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
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"ELSE\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
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"UIF TEMP[4]\n"
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/* Store result availability. */
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"NOT TEMP[0].z, TEMP[0]\n"
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"AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
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"STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
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"UIF TEMP[4]\n"
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"STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
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"ENDIF\n"
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"ELSE\n"
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/* Store result if it is available. */
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"NOT TEMP[4], TEMP[0].zzzz\n"
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"UIF TEMP[4]\n"
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/* Apply timestamp conversion */
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"AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
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"UIF TEMP[4]\n"
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"U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
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"U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
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"ENDIF\n"
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/* Convert to boolean */
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"AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
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"UIF TEMP[4]\n"
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"U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
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"AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
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"MOV TEMP[0].y, IMM[0].xxxx\n"
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"ENDIF\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
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"UIF TEMP[4]\n"
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"STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
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"ELSE\n"
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/* Clamping */
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"UIF TEMP[0].yyyy\n"
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"MOV TEMP[0].x, IMM[0].wwww\n"
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"ENDIF\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
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"UIF TEMP[4]\n"
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"UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
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"ENDIF\n"
|
|
|
|
"STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
|
|
"ENDIF\n"
|
|
"ENDIF\n"
|
|
"ENDIF\n"
|
|
"ENDIF\n"
|
|
|
|
"END\n";
|
|
|
|
char text[sizeof(text_tmpl) + 32];
|
|
struct tgsi_token tokens[1024];
|
|
struct pipe_compute_state state = {};
|
|
|
|
/* Hard code the frequency into the shader so that the backend can
|
|
* use the full range of optimizations for divide-by-constant.
|
|
*/
|
|
snprintf(text, sizeof(text), text_tmpl,
|
|
sctx->screen->info.clock_crystal_freq);
|
|
|
|
if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
|
|
assert(false);
|
|
return NULL;
|
|
}
|
|
|
|
state.ir_type = PIPE_SHADER_IR_TGSI;
|
|
state.prog = tokens;
|
|
|
|
return sctx->b.create_compute_state(&sctx->b, &state);
|
|
}
|
|
|
|
/* Create a compute shader implementing copy_image.
|
|
* Luckily, this works with all texture targets except 1D_ARRAY.
|
|
*/
|
|
void *si_create_copy_image_compute_shader(struct pipe_context *ctx)
|
|
{
|
|
static const char text[] =
|
|
"COMP\n"
|
|
"PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
|
|
"PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
|
|
"PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
|
|
"DCL SV[0], THREAD_ID\n"
|
|
"DCL SV[1], BLOCK_ID\n"
|
|
"DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
|
|
"DCL IMAGE[1], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
|
|
"DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
|
|
"DCL TEMP[0..4], LOCAL\n"
|
|
"IMM[0] UINT32 {8, 1, 0, 0}\n"
|
|
"MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
|
|
"UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
|
|
"UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
|
|
"LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
|
|
"MOV TEMP[4].xyz, CONST[0][1].xyzw\n"
|
|
"UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[4].xyzx\n"
|
|
"STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
|
|
"END\n";
|
|
|
|
struct tgsi_token tokens[1024];
|
|
struct pipe_compute_state state = {0};
|
|
|
|
if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
|
|
assert(false);
|
|
return NULL;
|
|
}
|
|
|
|
state.ir_type = PIPE_SHADER_IR_TGSI;
|
|
state.prog = tokens;
|
|
|
|
return ctx->create_compute_state(ctx, &state);
|
|
}
|
|
|
|
void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx)
|
|
{
|
|
static const char text[] =
|
|
"COMP\n"
|
|
"PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
|
|
"PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
|
|
"PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
|
|
"DCL SV[0], THREAD_ID\n"
|
|
"DCL SV[1], BLOCK_ID\n"
|
|
"DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
|
|
"DCL IMAGE[1], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
|
|
"DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
|
|
"DCL TEMP[0..4], LOCAL\n"
|
|
"IMM[0] UINT32 {64, 1, 0, 0}\n"
|
|
"MOV TEMP[0].xy, CONST[0][0].xzzw\n"
|
|
"UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
|
|
"UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n"
|
|
"LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
|
|
"MOV TEMP[4].xy, CONST[0][1].xzzw\n"
|
|
"UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[4].xyzx\n"
|
|
"STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
|
|
"END\n";
|
|
|
|
struct tgsi_token tokens[1024];
|
|
struct pipe_compute_state state = {0};
|
|
|
|
if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
|
|
assert(false);
|
|
return NULL;
|
|
}
|
|
|
|
state.ir_type = PIPE_SHADER_IR_TGSI;
|
|
state.prog = tokens;
|
|
|
|
return ctx->create_compute_state(ctx, &state);
|
|
}
|
|
|
|
void *si_clear_render_target_shader(struct pipe_context *ctx)
|
|
{
|
|
static const char text[] =
|
|
"COMP\n"
|
|
"PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
|
|
"PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
|
|
"PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
|
|
"DCL SV[0], THREAD_ID\n"
|
|
"DCL SV[1], BLOCK_ID\n"
|
|
"DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
|
|
"DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
|
|
"DCL TEMP[0..3], LOCAL\n"
|
|
"IMM[0] UINT32 {8, 1, 0, 0}\n"
|
|
"MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
|
|
"UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
|
|
"UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
|
|
"MOV TEMP[3].xyzw, CONST[0][1].xyzw\n"
|
|
"STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
|
|
"END\n";
|
|
|
|
struct tgsi_token tokens[1024];
|
|
struct pipe_compute_state state = {0};
|
|
|
|
if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
|
|
assert(false);
|
|
return NULL;
|
|
}
|
|
|
|
state.ir_type = PIPE_SHADER_IR_TGSI;
|
|
state.prog = tokens;
|
|
|
|
return ctx->create_compute_state(ctx, &state);
|
|
}
|
|
|
|
/* TODO: Didn't really test 1D_ARRAY */
|
|
void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx)
|
|
{
|
|
static const char text[] =
|
|
"COMP\n"
|
|
"PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
|
|
"PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
|
|
"PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
|
|
"DCL SV[0], THREAD_ID\n"
|
|
"DCL SV[1], BLOCK_ID\n"
|
|
"DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
|
|
"DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
|
|
"DCL TEMP[0..3], LOCAL\n"
|
|
"IMM[0] UINT32 {64, 1, 0, 0}\n"
|
|
"MOV TEMP[0].xy, CONST[0][0].xzzw\n"
|
|
"UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
|
|
"UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n"
|
|
"MOV TEMP[3].xyzw, CONST[0][1].xyzw\n"
|
|
"STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
|
|
"END\n";
|
|
|
|
struct tgsi_token tokens[1024];
|
|
struct pipe_compute_state state = {0};
|
|
|
|
if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
|
|
assert(false);
|
|
return NULL;
|
|
}
|
|
|
|
state.ir_type = PIPE_SHADER_IR_TGSI;
|
|
state.prog = tokens;
|
|
|
|
return ctx->create_compute_state(ctx, &state);
|
|
}
|