653 lines
24 KiB
C
653 lines
24 KiB
C
/*
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* Copyright © 2021 Raspberry Pi Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "v3dv_private.h"
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#include "broadcom/common/v3d_macros.h"
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#include "broadcom/cle/v3dx_pack.h"
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#include "broadcom/compiler/v3d_compiler.h"
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static uint8_t
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blend_factor(VkBlendFactor factor, bool dst_alpha_one, bool *needs_constants)
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{
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switch (factor) {
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case VK_BLEND_FACTOR_ZERO:
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case VK_BLEND_FACTOR_ONE:
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case VK_BLEND_FACTOR_SRC_COLOR:
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case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
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case VK_BLEND_FACTOR_DST_COLOR:
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case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
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case VK_BLEND_FACTOR_SRC_ALPHA:
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case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
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case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
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return factor;
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case VK_BLEND_FACTOR_CONSTANT_COLOR:
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case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
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case VK_BLEND_FACTOR_CONSTANT_ALPHA:
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case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
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*needs_constants = true;
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return factor;
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case VK_BLEND_FACTOR_DST_ALPHA:
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return dst_alpha_one ? V3D_BLEND_FACTOR_ONE :
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V3D_BLEND_FACTOR_DST_ALPHA;
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case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
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return dst_alpha_one ? V3D_BLEND_FACTOR_ZERO :
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V3D_BLEND_FACTOR_INV_DST_ALPHA;
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case VK_BLEND_FACTOR_SRC1_COLOR:
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case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
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case VK_BLEND_FACTOR_SRC1_ALPHA:
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case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
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assert(!"Invalid blend factor: dual source blending not supported.");
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default:
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assert(!"Unknown blend factor.");
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}
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/* Should be handled by the switch, added to avoid a "end of non-void
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* function" error
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*/
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unreachable("Unknown blend factor.");
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}
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static void
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pack_blend(struct v3dv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *cb_info)
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{
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/* By default, we are not enabling blending and all color channel writes are
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* enabled. Color write enables are independent of whether blending is
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* enabled or not.
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*
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* Vulkan specifies color write masks so that bits set correspond to
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* enabled channels. Our hardware does it the other way around.
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*/
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pipeline->blend.enables = 0;
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pipeline->blend.color_write_masks = 0; /* All channels enabled */
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if (!cb_info)
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return;
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assert(pipeline->subpass);
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if (pipeline->subpass->color_count == 0)
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return;
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assert(pipeline->subpass->color_count == cb_info->attachmentCount);
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pipeline->blend.needs_color_constants = false;
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uint32_t color_write_masks = 0;
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for (uint32_t i = 0; i < pipeline->subpass->color_count; i++) {
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const VkPipelineColorBlendAttachmentState *b_state =
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&cb_info->pAttachments[i];
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uint32_t attachment_idx =
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pipeline->subpass->color_attachments[i].attachment;
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if (attachment_idx == VK_ATTACHMENT_UNUSED)
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continue;
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color_write_masks |= (~b_state->colorWriteMask & 0xf) << (4 * i);
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if (!b_state->blendEnable)
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continue;
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VkAttachmentDescription2 *desc =
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&pipeline->pass->attachments[attachment_idx].desc;
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const struct v3dv_format *format = v3dX(get_format)(desc->format);
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bool dst_alpha_one = (format->swizzle[3] == PIPE_SWIZZLE_1);
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uint8_t rt_mask = 1 << i;
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pipeline->blend.enables |= rt_mask;
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v3dvx_pack(pipeline->blend.cfg[i], BLEND_CFG, config) {
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config.render_target_mask = rt_mask;
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config.color_blend_mode = b_state->colorBlendOp;
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config.color_blend_dst_factor =
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blend_factor(b_state->dstColorBlendFactor, dst_alpha_one,
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&pipeline->blend.needs_color_constants);
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config.color_blend_src_factor =
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blend_factor(b_state->srcColorBlendFactor, dst_alpha_one,
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&pipeline->blend.needs_color_constants);
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config.alpha_blend_mode = b_state->alphaBlendOp;
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config.alpha_blend_dst_factor =
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blend_factor(b_state->dstAlphaBlendFactor, dst_alpha_one,
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&pipeline->blend.needs_color_constants);
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config.alpha_blend_src_factor =
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blend_factor(b_state->srcAlphaBlendFactor, dst_alpha_one,
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&pipeline->blend.needs_color_constants);
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}
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}
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pipeline->blend.color_write_masks = color_write_masks;
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}
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/* This requires that pack_blend() had been called before so we can set
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* the overall blend enable bit in the CFG_BITS packet.
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*/
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static void
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pack_cfg_bits(struct v3dv_pipeline *pipeline,
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const VkPipelineDepthStencilStateCreateInfo *ds_info,
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const VkPipelineRasterizationStateCreateInfo *rs_info,
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const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *pv_info,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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assert(sizeof(pipeline->cfg_bits) == cl_packet_length(CFG_BITS));
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pipeline->msaa =
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ms_info && ms_info->rasterizationSamples > VK_SAMPLE_COUNT_1_BIT;
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v3dvx_pack(pipeline->cfg_bits, CFG_BITS, config) {
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config.enable_forward_facing_primitive =
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rs_info ? !(rs_info->cullMode & VK_CULL_MODE_FRONT_BIT) : false;
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config.enable_reverse_facing_primitive =
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rs_info ? !(rs_info->cullMode & VK_CULL_MODE_BACK_BIT) : false;
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/* Seems like the hardware is backwards regarding this setting... */
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config.clockwise_primitives =
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rs_info ? rs_info->frontFace == VK_FRONT_FACE_COUNTER_CLOCKWISE : false;
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config.enable_depth_offset = rs_info ? rs_info->depthBiasEnable: false;
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/* This is required to pass line rasterization tests in CTS while
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* exposing, at least, a minimum of 4-bits of subpixel precision
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* (the minimum requirement).
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*/
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config.line_rasterization = V3D_LINE_RASTERIZATION_PERP_END_CAPS;
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if (rs_info && rs_info->polygonMode != VK_POLYGON_MODE_FILL) {
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config.direct3d_wireframe_triangles_mode = true;
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config.direct3d_point_fill_mode =
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rs_info->polygonMode == VK_POLYGON_MODE_POINT;
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}
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config.rasterizer_oversample_mode = pipeline->msaa ? 1 : 0;
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/* From the Vulkan spec:
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*
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* "Provoking Vertex:
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*
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* The vertex in a primitive from which flat shaded attribute
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* values are taken. This is generally the “first” vertex in the
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* primitive, and depends on the primitive topology."
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*
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* First vertex is the Direct3D style for provoking vertex. OpenGL uses
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* the last vertex by default.
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*/
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if (pv_info) {
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config.direct3d_provoking_vertex =
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pv_info->provokingVertexMode ==
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VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT;
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} else {
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config.direct3d_provoking_vertex = true;
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}
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config.blend_enable = pipeline->blend.enables != 0;
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/* Disable depth/stencil if we don't have a D/S attachment */
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bool has_ds_attachment =
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pipeline->subpass->ds_attachment.attachment != VK_ATTACHMENT_UNUSED;
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if (ds_info && ds_info->depthTestEnable && has_ds_attachment) {
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config.z_updates_enable = ds_info->depthWriteEnable;
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config.depth_test_function = ds_info->depthCompareOp;
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} else {
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config.depth_test_function = VK_COMPARE_OP_ALWAYS;
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}
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/* EZ state will be updated at draw time based on bound pipeline state */
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config.early_z_updates_enable = false;
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config.early_z_enable = false;
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config.stencil_enable =
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ds_info ? ds_info->stencilTestEnable && has_ds_attachment: false;
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pipeline->z_updates_enable = config.z_updates_enable;
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};
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}
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static uint32_t
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translate_stencil_op(enum pipe_stencil_op op)
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{
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switch (op) {
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case VK_STENCIL_OP_KEEP:
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return V3D_STENCIL_OP_KEEP;
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case VK_STENCIL_OP_ZERO:
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return V3D_STENCIL_OP_ZERO;
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case VK_STENCIL_OP_REPLACE:
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return V3D_STENCIL_OP_REPLACE;
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case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
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return V3D_STENCIL_OP_INCR;
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case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
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return V3D_STENCIL_OP_DECR;
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case VK_STENCIL_OP_INVERT:
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return V3D_STENCIL_OP_INVERT;
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case VK_STENCIL_OP_INCREMENT_AND_WRAP:
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return V3D_STENCIL_OP_INCWRAP;
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case VK_STENCIL_OP_DECREMENT_AND_WRAP:
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return V3D_STENCIL_OP_DECWRAP;
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default:
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unreachable("bad stencil op");
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}
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}
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static void
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pack_single_stencil_cfg(struct v3dv_pipeline *pipeline,
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uint8_t *stencil_cfg,
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bool is_front,
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bool is_back,
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const VkStencilOpState *stencil_state)
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{
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/* From the Vulkan spec:
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*
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* "Reference is an integer reference value that is used in the unsigned
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* stencil comparison. The reference value used by stencil comparison
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* must be within the range [0,2^s-1] , where s is the number of bits in
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* the stencil framebuffer attachment, otherwise the reference value is
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* considered undefined."
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*
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* In our case, 's' is always 8, so we clamp to that to prevent our packing
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* functions to assert in debug mode if they see larger values.
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*
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* If we have dynamic state we need to make sure we set the corresponding
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* state bits to 0, since cl_emit_with_prepacked ORs the new value with
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* the old.
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*/
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const uint8_t write_mask =
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pipeline->dynamic_state.mask & V3DV_DYNAMIC_STENCIL_WRITE_MASK ?
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0 : stencil_state->writeMask & 0xff;
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const uint8_t compare_mask =
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pipeline->dynamic_state.mask & V3DV_DYNAMIC_STENCIL_COMPARE_MASK ?
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0 : stencil_state->compareMask & 0xff;
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const uint8_t reference =
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pipeline->dynamic_state.mask & V3DV_DYNAMIC_STENCIL_COMPARE_MASK ?
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0 : stencil_state->reference & 0xff;
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v3dvx_pack(stencil_cfg, STENCIL_CFG, config) {
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config.front_config = is_front;
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config.back_config = is_back;
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config.stencil_write_mask = write_mask;
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config.stencil_test_mask = compare_mask;
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config.stencil_test_function = stencil_state->compareOp;
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config.stencil_pass_op = translate_stencil_op(stencil_state->passOp);
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config.depth_test_fail_op = translate_stencil_op(stencil_state->depthFailOp);
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config.stencil_test_fail_op = translate_stencil_op(stencil_state->failOp);
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config.stencil_ref_value = reference;
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}
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}
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static void
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pack_stencil_cfg(struct v3dv_pipeline *pipeline,
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const VkPipelineDepthStencilStateCreateInfo *ds_info)
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{
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assert(sizeof(pipeline->stencil_cfg) == 2 * cl_packet_length(STENCIL_CFG));
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if (!ds_info || !ds_info->stencilTestEnable)
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return;
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if (pipeline->subpass->ds_attachment.attachment == VK_ATTACHMENT_UNUSED)
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return;
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const uint32_t dynamic_stencil_states = V3DV_DYNAMIC_STENCIL_COMPARE_MASK |
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V3DV_DYNAMIC_STENCIL_WRITE_MASK |
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V3DV_DYNAMIC_STENCIL_REFERENCE;
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/* If front != back or we have dynamic stencil state we can't emit a single
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* packet for both faces.
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*/
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bool needs_front_and_back = false;
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if ((pipeline->dynamic_state.mask & dynamic_stencil_states) ||
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memcmp(&ds_info->front, &ds_info->back, sizeof(ds_info->front)))
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needs_front_and_back = true;
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/* If the front and back configurations are the same we can emit both with
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* a single packet.
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*/
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pipeline->emit_stencil_cfg[0] = true;
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if (!needs_front_and_back) {
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pack_single_stencil_cfg(pipeline, pipeline->stencil_cfg[0],
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true, true, &ds_info->front);
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} else {
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pipeline->emit_stencil_cfg[1] = true;
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pack_single_stencil_cfg(pipeline, pipeline->stencil_cfg[0],
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true, false, &ds_info->front);
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pack_single_stencil_cfg(pipeline, pipeline->stencil_cfg[1],
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false, true, &ds_info->back);
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}
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}
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void
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v3dX(pipeline_pack_state)(struct v3dv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *cb_info,
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const VkPipelineDepthStencilStateCreateInfo *ds_info,
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const VkPipelineRasterizationStateCreateInfo *rs_info,
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const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *pv_info,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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pack_blend(pipeline, cb_info);
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pack_cfg_bits(pipeline, ds_info, rs_info, pv_info, ms_info);
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pack_stencil_cfg(pipeline, ds_info);
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}
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static void
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pack_shader_state_record(struct v3dv_pipeline *pipeline)
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{
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assert(sizeof(pipeline->shader_state_record) ==
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cl_packet_length(GL_SHADER_STATE_RECORD));
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struct v3d_fs_prog_data *prog_data_fs =
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pipeline->shared_data->variants[BROADCOM_SHADER_FRAGMENT]->prog_data.fs;
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struct v3d_vs_prog_data *prog_data_vs =
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pipeline->shared_data->variants[BROADCOM_SHADER_VERTEX]->prog_data.vs;
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struct v3d_vs_prog_data *prog_data_vs_bin =
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pipeline->shared_data->variants[BROADCOM_SHADER_VERTEX_BIN]->prog_data.vs;
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/* Note: we are not packing addresses, as we need the job (see
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* cl_pack_emit_reloc). Additionally uniforms can't be filled up at this
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* point as they depend on dynamic info that can be set after create the
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* pipeline (like viewport), . Would need to be filled later, so we are
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* doing a partial prepacking.
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*/
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v3dvx_pack(pipeline->shader_state_record, GL_SHADER_STATE_RECORD, shader) {
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shader.enable_clipping = true;
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if (!pipeline->has_gs) {
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shader.point_size_in_shaded_vertex_data =
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pipeline->topology == PIPE_PRIM_POINTS;
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} else {
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struct v3d_gs_prog_data *prog_data_gs =
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pipeline->shared_data->variants[BROADCOM_SHADER_GEOMETRY]->prog_data.gs;
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shader.point_size_in_shaded_vertex_data = prog_data_gs->writes_psiz;
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}
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/* Must be set if the shader modifies Z, discards, or modifies
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* the sample mask. For any of these cases, the fragment
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* shader needs to write the Z value (even just discards).
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*/
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shader.fragment_shader_does_z_writes = prog_data_fs->writes_z;
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/* Set if the EZ test must be disabled (due to shader side
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* effects and the early_z flag not being present in the
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* shader).
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*/
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shader.turn_off_early_z_test = prog_data_fs->disable_ez;
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shader.fragment_shader_uses_real_pixel_centre_w_in_addition_to_centroid_w2 =
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prog_data_fs->uses_center_w;
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/* The description for gl_SampleID states that if a fragment shader reads
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* it, then we should automatically activate per-sample shading. However,
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* the Vulkan spec also states that if a framebuffer has no attachments:
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*
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* "The subpass continues to use the width, height, and layers of the
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* framebuffer to define the dimensions of the rendering area, and the
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* rasterizationSamples from each pipeline’s
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* VkPipelineMultisampleStateCreateInfo to define the number of
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* samples used in rasterization multisample rasterization."
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*
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* So in this scenario, if the pipeline doesn't enable multiple samples
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* but the fragment shader accesses gl_SampleID we would be requested
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* to do per-sample shading in single sample rasterization mode, which
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* is pointless, so just disable it in that case.
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*/
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shader.enable_sample_rate_shading =
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pipeline->sample_rate_shading ||
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(pipeline->msaa && prog_data_fs->force_per_sample_msaa);
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shader.any_shader_reads_hardware_written_primitive_id = false;
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shader.do_scoreboard_wait_on_first_thread_switch =
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prog_data_fs->lock_scoreboard_on_first_thrsw;
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shader.disable_implicit_point_line_varyings =
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!prog_data_fs->uses_implicit_point_line_varyings;
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shader.number_of_varyings_in_fragment_shader =
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prog_data_fs->num_inputs;
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shader.coordinate_shader_propagate_nans = true;
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shader.vertex_shader_propagate_nans = true;
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shader.fragment_shader_propagate_nans = true;
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/* Note: see previous note about adresses */
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/* shader.coordinate_shader_code_address */
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/* shader.vertex_shader_code_address */
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/* shader.fragment_shader_code_address */
|
||
|
||
/* FIXME: Use combined input/output size flag in the common case (also
|
||
* on v3d, see v3dx_draw).
|
||
*/
|
||
shader.coordinate_shader_has_separate_input_and_output_vpm_blocks =
|
||
prog_data_vs_bin->separate_segments;
|
||
shader.vertex_shader_has_separate_input_and_output_vpm_blocks =
|
||
prog_data_vs->separate_segments;
|
||
|
||
shader.coordinate_shader_input_vpm_segment_size =
|
||
prog_data_vs_bin->separate_segments ?
|
||
prog_data_vs_bin->vpm_input_size : 1;
|
||
shader.vertex_shader_input_vpm_segment_size =
|
||
prog_data_vs->separate_segments ?
|
||
prog_data_vs->vpm_input_size : 1;
|
||
|
||
shader.coordinate_shader_output_vpm_segment_size =
|
||
prog_data_vs_bin->vpm_output_size;
|
||
shader.vertex_shader_output_vpm_segment_size =
|
||
prog_data_vs->vpm_output_size;
|
||
|
||
/* Note: see previous note about adresses */
|
||
/* shader.coordinate_shader_uniforms_address */
|
||
/* shader.vertex_shader_uniforms_address */
|
||
/* shader.fragment_shader_uniforms_address */
|
||
|
||
shader.min_coord_shader_input_segments_required_in_play =
|
||
pipeline->vpm_cfg_bin.As;
|
||
shader.min_vertex_shader_input_segments_required_in_play =
|
||
pipeline->vpm_cfg.As;
|
||
|
||
shader.min_coord_shader_output_segments_required_in_play_in_addition_to_vcm_cache_size =
|
||
pipeline->vpm_cfg_bin.Ve;
|
||
shader.min_vertex_shader_output_segments_required_in_play_in_addition_to_vcm_cache_size =
|
||
pipeline->vpm_cfg.Ve;
|
||
|
||
shader.coordinate_shader_4_way_threadable =
|
||
prog_data_vs_bin->base.threads == 4;
|
||
shader.vertex_shader_4_way_threadable =
|
||
prog_data_vs->base.threads == 4;
|
||
shader.fragment_shader_4_way_threadable =
|
||
prog_data_fs->base.threads == 4;
|
||
|
||
shader.coordinate_shader_start_in_final_thread_section =
|
||
prog_data_vs_bin->base.single_seg;
|
||
shader.vertex_shader_start_in_final_thread_section =
|
||
prog_data_vs->base.single_seg;
|
||
shader.fragment_shader_start_in_final_thread_section =
|
||
prog_data_fs->base.single_seg;
|
||
|
||
shader.vertex_id_read_by_coordinate_shader =
|
||
prog_data_vs_bin->uses_vid;
|
||
shader.base_instance_id_read_by_coordinate_shader =
|
||
prog_data_vs_bin->uses_biid;
|
||
shader.instance_id_read_by_coordinate_shader =
|
||
prog_data_vs_bin->uses_iid;
|
||
shader.vertex_id_read_by_vertex_shader =
|
||
prog_data_vs->uses_vid;
|
||
shader.base_instance_id_read_by_vertex_shader =
|
||
prog_data_vs->uses_biid;
|
||
shader.instance_id_read_by_vertex_shader =
|
||
prog_data_vs->uses_iid;
|
||
|
||
/* Note: see previous note about adresses */
|
||
/* shader.address_of_default_attribute_values */
|
||
}
|
||
}
|
||
|
||
static void
|
||
pack_vcm_cache_size(struct v3dv_pipeline *pipeline)
|
||
{
|
||
assert(sizeof(pipeline->vcm_cache_size) ==
|
||
cl_packet_length(VCM_CACHE_SIZE));
|
||
|
||
v3dvx_pack(pipeline->vcm_cache_size, VCM_CACHE_SIZE, vcm) {
|
||
vcm.number_of_16_vertex_batches_for_binning = pipeline->vpm_cfg_bin.Vc;
|
||
vcm.number_of_16_vertex_batches_for_rendering = pipeline->vpm_cfg.Vc;
|
||
}
|
||
}
|
||
|
||
/* As defined on the GL_SHADER_STATE_ATTRIBUTE_RECORD */
|
||
static uint8_t
|
||
get_attr_type(const struct util_format_description *desc)
|
||
{
|
||
uint32_t r_size = desc->channel[0].size;
|
||
uint8_t attr_type = ATTRIBUTE_FLOAT;
|
||
|
||
switch (desc->channel[0].type) {
|
||
case UTIL_FORMAT_TYPE_FLOAT:
|
||
if (r_size == 32) {
|
||
attr_type = ATTRIBUTE_FLOAT;
|
||
} else {
|
||
assert(r_size == 16);
|
||
attr_type = ATTRIBUTE_HALF_FLOAT;
|
||
}
|
||
break;
|
||
|
||
case UTIL_FORMAT_TYPE_SIGNED:
|
||
case UTIL_FORMAT_TYPE_UNSIGNED:
|
||
switch (r_size) {
|
||
case 32:
|
||
attr_type = ATTRIBUTE_INT;
|
||
break;
|
||
case 16:
|
||
attr_type = ATTRIBUTE_SHORT;
|
||
break;
|
||
case 10:
|
||
attr_type = ATTRIBUTE_INT2_10_10_10;
|
||
break;
|
||
case 8:
|
||
attr_type = ATTRIBUTE_BYTE;
|
||
break;
|
||
default:
|
||
fprintf(stderr,
|
||
"format %s unsupported\n",
|
||
desc->name);
|
||
attr_type = ATTRIBUTE_BYTE;
|
||
abort();
|
||
}
|
||
break;
|
||
|
||
default:
|
||
fprintf(stderr,
|
||
"format %s unsupported\n",
|
||
desc->name);
|
||
abort();
|
||
}
|
||
|
||
return attr_type;
|
||
}
|
||
|
||
static void
|
||
pack_shader_state_attribute_record(struct v3dv_pipeline *pipeline,
|
||
uint32_t index,
|
||
const VkVertexInputAttributeDescription *vi_desc)
|
||
{
|
||
const uint32_t packet_length =
|
||
cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD);
|
||
|
||
const struct util_format_description *desc =
|
||
vk_format_description(vi_desc->format);
|
||
|
||
uint32_t binding = vi_desc->binding;
|
||
|
||
v3dvx_pack(&pipeline->vertex_attrs[index * packet_length],
|
||
GL_SHADER_STATE_ATTRIBUTE_RECORD, attr) {
|
||
|
||
/* vec_size == 0 means 4 */
|
||
attr.vec_size = desc->nr_channels & 3;
|
||
attr.signed_int_type = (desc->channel[0].type ==
|
||
UTIL_FORMAT_TYPE_SIGNED);
|
||
attr.normalized_int_type = desc->channel[0].normalized;
|
||
attr.read_as_int_uint = desc->channel[0].pure_integer;
|
||
|
||
attr.instance_divisor = MIN2(pipeline->vb[binding].instance_divisor,
|
||
0xffff);
|
||
attr.stride = pipeline->vb[binding].stride;
|
||
attr.type = get_attr_type(desc);
|
||
}
|
||
}
|
||
|
||
void
|
||
v3dX(pipeline_pack_compile_state)(struct v3dv_pipeline *pipeline,
|
||
const VkPipelineVertexInputStateCreateInfo *vi_info,
|
||
const VkPipelineVertexInputDivisorStateCreateInfoEXT *vd_info)
|
||
{
|
||
pack_shader_state_record(pipeline);
|
||
pack_vcm_cache_size(pipeline);
|
||
|
||
pipeline->vb_count = vi_info->vertexBindingDescriptionCount;
|
||
for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
|
||
const VkVertexInputBindingDescription *desc =
|
||
&vi_info->pVertexBindingDescriptions[i];
|
||
|
||
pipeline->vb[desc->binding].stride = desc->stride;
|
||
pipeline->vb[desc->binding].instance_divisor = desc->inputRate;
|
||
}
|
||
|
||
if (vd_info) {
|
||
for (uint32_t i = 0; i < vd_info->vertexBindingDivisorCount; i++) {
|
||
const VkVertexInputBindingDivisorDescriptionEXT *desc =
|
||
&vd_info->pVertexBindingDivisors[i];
|
||
|
||
pipeline->vb[desc->binding].instance_divisor = desc->divisor;
|
||
}
|
||
}
|
||
|
||
pipeline->va_count = 0;
|
||
struct v3d_vs_prog_data *prog_data_vs =
|
||
pipeline->shared_data->variants[BROADCOM_SHADER_VERTEX]->prog_data.vs;
|
||
|
||
for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
|
||
const VkVertexInputAttributeDescription *desc =
|
||
&vi_info->pVertexAttributeDescriptions[i];
|
||
uint32_t location = desc->location + VERT_ATTRIB_GENERIC0;
|
||
|
||
/* We use a custom driver_location_map instead of
|
||
* nir_find_variable_with_location because if we were able to get the
|
||
* shader variant from the cache, we would not have the nir shader
|
||
* available.
|
||
*/
|
||
uint32_t driver_location =
|
||
prog_data_vs->driver_location_map[location];
|
||
|
||
if (driver_location != -1) {
|
||
assert(driver_location < MAX_VERTEX_ATTRIBS);
|
||
pipeline->va[driver_location].offset = desc->offset;
|
||
pipeline->va[driver_location].binding = desc->binding;
|
||
pipeline->va[driver_location].vk_format = desc->format;
|
||
|
||
pack_shader_state_attribute_record(pipeline, driver_location, desc);
|
||
|
||
pipeline->va_count++;
|
||
}
|
||
}
|
||
}
|