653 lines
20 KiB
C
653 lines
20 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Marek Olšák
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*/
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#include "r600_cs.h"
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#include "evergreen_compute.h"
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#include "compute_memory_pool.h"
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#include "util/u_memory.h"
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#include "util/u_upload_mgr.h"
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#include <inttypes.h>
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#include <stdio.h>
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bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
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struct pb_buffer *buf,
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unsigned usage)
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{
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if (ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs, buf, usage)) {
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return true;
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}
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if (radeon_emitted(&ctx->dma.cs, 0) &&
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ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs, buf, usage)) {
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return true;
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}
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return false;
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}
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void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
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struct r600_resource *resource,
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unsigned usage)
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{
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unsigned rusage = RADEON_USAGE_READWRITE;
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bool busy = false;
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assert(!(resource->flags & RADEON_FLAG_SPARSE));
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if (usage & PIPE_MAP_UNSYNCHRONIZED) {
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return ctx->ws->buffer_map(ctx->ws, resource->buf, NULL, usage);
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}
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if (!(usage & PIPE_MAP_WRITE)) {
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/* have to wait for the last write */
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rusage = RADEON_USAGE_WRITE;
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}
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if (radeon_emitted(&ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
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ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs,
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resource->buf, rusage)) {
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if (usage & PIPE_MAP_DONTBLOCK) {
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ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
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return NULL;
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} else {
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ctx->gfx.flush(ctx, 0, NULL);
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busy = true;
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}
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}
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if (radeon_emitted(&ctx->dma.cs, 0) &&
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ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs,
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resource->buf, rusage)) {
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if (usage & PIPE_MAP_DONTBLOCK) {
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ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
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return NULL;
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} else {
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ctx->dma.flush(ctx, 0, NULL);
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busy = true;
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}
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}
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if (busy || !ctx->ws->buffer_wait(ctx->ws, resource->buf, 0, rusage)) {
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if (usage & PIPE_MAP_DONTBLOCK) {
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return NULL;
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} else {
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/* We will be wait for the GPU. Wait for any offloaded
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* CS flush to complete to avoid busy-waiting in the winsys. */
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ctx->ws->cs_sync_flush(&ctx->gfx.cs);
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if (ctx->dma.cs.priv)
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ctx->ws->cs_sync_flush(&ctx->dma.cs);
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}
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}
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/* Setting the CS to NULL will prevent doing checks we have done already. */
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return ctx->ws->buffer_map(ctx->ws, resource->buf, NULL, usage);
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}
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void r600_init_resource_fields(struct r600_common_screen *rscreen,
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struct r600_resource *res,
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uint64_t size, unsigned alignment)
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{
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struct r600_texture *rtex = (struct r600_texture*)res;
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res->bo_size = size;
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res->bo_alignment = alignment;
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res->flags = 0;
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res->texture_handle_allocated = false;
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res->image_handle_allocated = false;
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switch (res->b.b.usage) {
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case PIPE_USAGE_STREAM:
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res->flags = RADEON_FLAG_GTT_WC;
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FALLTHROUGH;
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case PIPE_USAGE_STAGING:
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/* Transfers are likely to occur more often with these
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* resources. */
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res->domains = RADEON_DOMAIN_GTT;
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break;
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case PIPE_USAGE_DYNAMIC:
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case PIPE_USAGE_DEFAULT:
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case PIPE_USAGE_IMMUTABLE:
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default:
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/* Not listing GTT here improves performance in some
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* apps. */
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res->domains = RADEON_DOMAIN_VRAM;
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res->flags |= RADEON_FLAG_GTT_WC;
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break;
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}
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/* Tiled textures are unmappable. Always put them in VRAM. */
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if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
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res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
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res->domains = RADEON_DOMAIN_VRAM;
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res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
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RADEON_FLAG_GTT_WC;
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}
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/* Displayable and shareable surfaces are not suballocated. */
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if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
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res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
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else
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res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
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if (rscreen->debug_flags & DBG_NO_WC)
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res->flags &= ~RADEON_FLAG_GTT_WC;
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/* Set expected VRAM and GART usage for the buffer. */
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res->vram_usage = 0;
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res->gart_usage = 0;
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if (res->domains & RADEON_DOMAIN_VRAM)
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res->vram_usage = size;
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else if (res->domains & RADEON_DOMAIN_GTT)
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res->gart_usage = size;
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}
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bool r600_alloc_resource(struct r600_common_screen *rscreen,
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struct r600_resource *res)
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{
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struct pb_buffer *old_buf, *new_buf;
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/* Allocate a new resource. */
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new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
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res->bo_alignment,
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res->domains, res->flags);
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if (!new_buf) {
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return false;
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}
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/* Replace the pointer such that if res->buf wasn't NULL, it won't be
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* NULL. This should prevent crashes with multiple contexts using
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* the same buffer where one of the contexts invalidates it while
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* the others are using it. */
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old_buf = res->buf;
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res->buf = new_buf; /* should be atomic */
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if (rscreen->info.r600_has_virtual_memory)
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res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
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else
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res->gpu_address = 0;
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pb_reference(&old_buf, NULL);
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util_range_set_empty(&res->valid_buffer_range);
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/* Print debug information. */
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if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
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fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
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res->gpu_address, res->gpu_address + res->buf->size,
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res->buf->size);
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}
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return true;
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}
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void r600_buffer_destroy(struct pipe_screen *screen, struct pipe_resource *buf)
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{
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struct r600_resource *rbuffer = r600_resource(buf);
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threaded_resource_deinit(buf);
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util_range_destroy(&rbuffer->valid_buffer_range);
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pipe_resource_reference((struct pipe_resource**)&rbuffer->immed_buffer, NULL);
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pb_reference(&rbuffer->buf, NULL);
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FREE(rbuffer);
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}
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static bool
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r600_invalidate_buffer(struct r600_common_context *rctx,
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struct r600_resource *rbuffer)
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{
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/* Shared buffers can't be reallocated. */
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if (rbuffer->b.is_shared)
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return false;
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/* Sparse buffers can't be reallocated. */
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if (rbuffer->flags & RADEON_FLAG_SPARSE)
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return false;
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/* In AMD_pinned_memory, the user pointer association only gets
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* broken when the buffer is explicitly re-allocated.
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*/
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if (rbuffer->b.is_user_ptr)
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return false;
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/* Check if mapping this buffer would cause waiting for the GPU. */
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if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
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!rctx->ws->buffer_wait(rctx->ws, rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
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rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
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} else {
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util_range_set_empty(&rbuffer->valid_buffer_range);
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}
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return true;
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}
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/* Replace the storage of dst with src. */
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void r600_replace_buffer_storage(struct pipe_context *ctx,
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struct pipe_resource *dst,
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struct pipe_resource *src)
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{
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struct r600_common_context *rctx = (struct r600_common_context *)ctx;
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struct r600_resource *rdst = r600_resource(dst);
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struct r600_resource *rsrc = r600_resource(src);
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uint64_t old_gpu_address = rdst->gpu_address;
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pb_reference(&rdst->buf, rsrc->buf);
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rdst->gpu_address = rsrc->gpu_address;
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rdst->b.b.bind = rsrc->b.b.bind;
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rdst->flags = rsrc->flags;
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assert(rdst->vram_usage == rsrc->vram_usage);
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assert(rdst->gart_usage == rsrc->gart_usage);
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assert(rdst->bo_size == rsrc->bo_size);
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assert(rdst->bo_alignment == rsrc->bo_alignment);
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assert(rdst->domains == rsrc->domains);
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rctx->rebind_buffer(ctx, dst, old_gpu_address);
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}
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void r600_invalidate_resource(struct pipe_context *ctx,
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struct pipe_resource *resource)
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{
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struct r600_common_context *rctx = (struct r600_common_context*)ctx;
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struct r600_resource *rbuffer = r600_resource(resource);
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/* We currently only do anyting here for buffers */
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if (resource->target == PIPE_BUFFER)
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(void)r600_invalidate_buffer(rctx, rbuffer);
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}
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static void *r600_buffer_get_transfer(struct pipe_context *ctx,
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struct pipe_resource *resource,
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unsigned usage,
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const struct pipe_box *box,
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struct pipe_transfer **ptransfer,
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void *data, struct r600_resource *staging,
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unsigned offset)
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{
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struct r600_common_context *rctx = (struct r600_common_context*)ctx;
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struct r600_transfer *transfer;
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if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
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transfer = slab_zalloc(&rctx->pool_transfers_unsync);
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else
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transfer = slab_zalloc(&rctx->pool_transfers);
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pipe_resource_reference(&transfer->b.b.resource, resource);
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transfer->b.b.usage = usage;
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transfer->b.b.box = *box;
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transfer->b.b.offset = offset;
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transfer->staging = staging;
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*ptransfer = &transfer->b.b;
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return data;
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}
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static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
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unsigned dstx, unsigned srcx, unsigned size)
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{
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bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
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return rctx->screen->has_cp_dma ||
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(dword_aligned && (rctx->dma.cs.priv ||
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rctx->screen->has_streamout));
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}
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void *r600_buffer_transfer_map(struct pipe_context *ctx,
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struct pipe_resource *resource,
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unsigned level,
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unsigned usage,
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const struct pipe_box *box,
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struct pipe_transfer **ptransfer)
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{
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struct r600_common_context *rctx = (struct r600_common_context*)ctx;
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struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
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struct r600_resource *rbuffer = r600_resource(resource);
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uint8_t *data;
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if (r600_resource(resource)->compute_global_bo) {
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if ((data = r600_compute_global_transfer_map(ctx, resource, level, usage, box, ptransfer)))
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return data;
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}
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assert(box->x + box->width <= resource->width0);
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/* From GL_AMD_pinned_memory issues:
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*
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* 4) Is glMapBuffer on a shared buffer guaranteed to return the
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* same system address which was specified at creation time?
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*
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* RESOLVED: NO. The GL implementation might return a different
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* virtual mapping of that memory, although the same physical
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* page will be used.
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*
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* So don't ever use staging buffers.
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*/
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if (rbuffer->b.is_user_ptr)
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usage |= PIPE_MAP_PERSISTENT;
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/* See if the buffer range being mapped has never been initialized,
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* in which case it can be mapped unsynchronized. */
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if (!(usage & (PIPE_MAP_UNSYNCHRONIZED |
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TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
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usage & PIPE_MAP_WRITE &&
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!rbuffer->b.is_shared &&
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!util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
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usage |= PIPE_MAP_UNSYNCHRONIZED;
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}
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/* If discarding the entire range, discard the whole resource instead. */
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if (usage & PIPE_MAP_DISCARD_RANGE &&
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box->x == 0 && box->width == resource->width0) {
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usage |= PIPE_MAP_DISCARD_WHOLE_RESOURCE;
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}
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if (usage & PIPE_MAP_DISCARD_WHOLE_RESOURCE &&
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!(usage & (PIPE_MAP_UNSYNCHRONIZED |
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TC_TRANSFER_MAP_NO_INVALIDATE))) {
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assert(usage & PIPE_MAP_WRITE);
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if (r600_invalidate_buffer(rctx, rbuffer)) {
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/* At this point, the buffer is always idle. */
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usage |= PIPE_MAP_UNSYNCHRONIZED;
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} else {
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/* Fall back to a temporary buffer. */
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usage |= PIPE_MAP_DISCARD_RANGE;
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}
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}
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if ((usage & PIPE_MAP_DISCARD_RANGE) &&
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!(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
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((!(usage & (PIPE_MAP_UNSYNCHRONIZED |
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PIPE_MAP_PERSISTENT)) &&
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r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
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(rbuffer->flags & RADEON_FLAG_SPARSE))) {
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assert(usage & PIPE_MAP_WRITE);
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/* Check if mapping this buffer would cause waiting for the GPU.
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*/
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if (rbuffer->flags & RADEON_FLAG_SPARSE ||
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r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
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!rctx->ws->buffer_wait(rctx->ws, rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
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/* Do a wait-free write-only transfer using a temporary buffer. */
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unsigned offset;
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struct r600_resource *staging = NULL;
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u_upload_alloc(ctx->stream_uploader, 0,
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box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
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rctx->screen->info.tcc_cache_line_size,
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&offset, (struct pipe_resource**)&staging,
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(void**)&data);
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if (staging) {
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data += box->x % R600_MAP_BUFFER_ALIGNMENT;
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return r600_buffer_get_transfer(ctx, resource, usage, box,
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ptransfer, data, staging, offset);
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} else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
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return NULL;
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}
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} else {
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/* At this point, the buffer is always idle (we checked it above). */
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usage |= PIPE_MAP_UNSYNCHRONIZED;
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}
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}
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/* Use a staging buffer in cached GTT for reads. */
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else if (((usage & PIPE_MAP_READ) &&
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!(usage & PIPE_MAP_PERSISTENT) &&
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(rbuffer->domains & RADEON_DOMAIN_VRAM ||
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rbuffer->flags & RADEON_FLAG_GTT_WC) &&
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r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
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(rbuffer->flags & RADEON_FLAG_SPARSE)) {
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struct r600_resource *staging;
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assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
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staging = (struct r600_resource*) pipe_buffer_create(
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ctx->screen, 0, PIPE_USAGE_STAGING,
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box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
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if (staging) {
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/* Copy the VRAM buffer to the staging buffer. */
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rctx->dma_copy(ctx, &staging->b.b, 0,
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box->x % R600_MAP_BUFFER_ALIGNMENT,
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0, 0, resource, 0, box);
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data = r600_buffer_map_sync_with_rings(rctx, staging,
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usage & ~PIPE_MAP_UNSYNCHRONIZED);
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if (!data) {
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r600_resource_reference(&staging, NULL);
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return NULL;
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}
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data += box->x % R600_MAP_BUFFER_ALIGNMENT;
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return r600_buffer_get_transfer(ctx, resource, usage, box,
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ptransfer, data, staging, 0);
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} else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
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return NULL;
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}
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}
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data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
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if (!data) {
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return NULL;
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}
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data += box->x;
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return r600_buffer_get_transfer(ctx, resource, usage, box,
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ptransfer, data, NULL, 0);
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}
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static void r600_buffer_do_flush_region(struct pipe_context *ctx,
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struct pipe_transfer *transfer,
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const struct pipe_box *box)
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{
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struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
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struct r600_resource *rbuffer = r600_resource(transfer->resource);
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if (rtransfer->staging) {
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struct pipe_resource *dst, *src;
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unsigned soffset;
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struct pipe_box dma_box;
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dst = transfer->resource;
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src = &rtransfer->staging->b.b;
|
|
soffset = rtransfer->b.b.offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
|
|
|
|
u_box_1d(soffset, box->width, &dma_box);
|
|
|
|
/* Copy the staging buffer into the original one. */
|
|
ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
|
|
}
|
|
|
|
util_range_add(&rbuffer->b.b, &rbuffer->valid_buffer_range, box->x,
|
|
box->x + box->width);
|
|
}
|
|
|
|
void r600_buffer_flush_region(struct pipe_context *ctx,
|
|
struct pipe_transfer *transfer,
|
|
const struct pipe_box *rel_box)
|
|
{
|
|
unsigned required_usage = PIPE_MAP_WRITE |
|
|
PIPE_MAP_FLUSH_EXPLICIT;
|
|
|
|
if (r600_resource(transfer->resource)->compute_global_bo)
|
|
return;
|
|
|
|
if ((transfer->usage & required_usage) == required_usage) {
|
|
struct pipe_box box;
|
|
|
|
u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
|
|
r600_buffer_do_flush_region(ctx, transfer, &box);
|
|
}
|
|
}
|
|
|
|
void r600_buffer_transfer_unmap(struct pipe_context *ctx,
|
|
struct pipe_transfer *transfer)
|
|
{
|
|
struct r600_common_context *rctx = (struct r600_common_context*)ctx;
|
|
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
|
|
struct r600_resource *rtransferr = r600_resource(transfer->resource);
|
|
|
|
if (rtransferr->compute_global_bo && !rtransferr->b.is_user_ptr) {
|
|
r600_compute_global_transfer_unmap(ctx, transfer);
|
|
return;
|
|
}
|
|
|
|
if (transfer->usage & PIPE_MAP_WRITE &&
|
|
!(transfer->usage & PIPE_MAP_FLUSH_EXPLICIT))
|
|
r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
|
|
|
|
r600_resource_reference(&rtransfer->staging, NULL);
|
|
assert(rtransfer->b.staging == NULL); /* for threaded context only */
|
|
pipe_resource_reference(&transfer->resource, NULL);
|
|
|
|
/* Don't use pool_transfers_unsync. We are always in the driver
|
|
* thread. */
|
|
slab_free(&rctx->pool_transfers, transfer);
|
|
}
|
|
|
|
void r600_buffer_subdata(struct pipe_context *ctx,
|
|
struct pipe_resource *buffer,
|
|
unsigned usage, unsigned offset,
|
|
unsigned size, const void *data)
|
|
{
|
|
struct pipe_transfer *transfer = NULL;
|
|
struct pipe_box box;
|
|
uint8_t *map = NULL;
|
|
|
|
usage |= PIPE_MAP_WRITE;
|
|
|
|
if (!(usage & PIPE_MAP_DIRECTLY))
|
|
usage |= PIPE_MAP_DISCARD_RANGE;
|
|
|
|
u_box_1d(offset, size, &box);
|
|
map = r600_buffer_transfer_map(ctx, buffer, 0, usage, &box, &transfer);
|
|
if (!map)
|
|
return;
|
|
|
|
memcpy(map, data, size);
|
|
r600_buffer_transfer_unmap(ctx, transfer);
|
|
}
|
|
|
|
static struct r600_resource *
|
|
r600_alloc_buffer_struct(struct pipe_screen *screen,
|
|
const struct pipe_resource *templ)
|
|
{
|
|
struct r600_resource *rbuffer;
|
|
|
|
rbuffer = MALLOC_STRUCT(r600_resource);
|
|
|
|
rbuffer->b.b = *templ;
|
|
rbuffer->b.b.next = NULL;
|
|
pipe_reference_init(&rbuffer->b.b.reference, 1);
|
|
rbuffer->b.b.screen = screen;
|
|
|
|
threaded_resource_init(&rbuffer->b.b, false);
|
|
|
|
rbuffer->buf = NULL;
|
|
rbuffer->bind_history = 0;
|
|
rbuffer->immed_buffer = NULL;
|
|
rbuffer->compute_global_bo = false;
|
|
util_range_init(&rbuffer->valid_buffer_range);
|
|
return rbuffer;
|
|
}
|
|
|
|
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
|
|
const struct pipe_resource *templ,
|
|
unsigned alignment)
|
|
{
|
|
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
|
|
struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
|
|
|
|
r600_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
|
|
|
|
if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
|
|
rbuffer->flags |= RADEON_FLAG_SPARSE;
|
|
|
|
if (!r600_alloc_resource(rscreen, rbuffer)) {
|
|
FREE(rbuffer);
|
|
return NULL;
|
|
}
|
|
return &rbuffer->b.b;
|
|
}
|
|
|
|
struct pipe_resource *r600_aligned_buffer_create(struct pipe_screen *screen,
|
|
unsigned flags,
|
|
unsigned usage,
|
|
unsigned size,
|
|
unsigned alignment)
|
|
{
|
|
struct pipe_resource buffer;
|
|
|
|
memset(&buffer, 0, sizeof buffer);
|
|
buffer.target = PIPE_BUFFER;
|
|
buffer.format = PIPE_FORMAT_R8_UNORM;
|
|
buffer.bind = 0;
|
|
buffer.usage = usage;
|
|
buffer.flags = flags;
|
|
buffer.width0 = size;
|
|
buffer.height0 = 1;
|
|
buffer.depth0 = 1;
|
|
buffer.array_size = 1;
|
|
return r600_buffer_create(screen, &buffer, alignment);
|
|
}
|
|
|
|
struct pipe_resource *
|
|
r600_buffer_from_user_memory(struct pipe_screen *screen,
|
|
const struct pipe_resource *templ,
|
|
void *user_memory)
|
|
{
|
|
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
|
|
struct radeon_winsys *ws = rscreen->ws;
|
|
struct r600_resource *rbuffer;
|
|
|
|
if ((templ->bind & PIPE_BIND_GLOBAL) &&
|
|
(templ->bind & PIPE_BIND_COMPUTE_RESOURCE)) {
|
|
rbuffer = r600_resource(r600_compute_global_buffer_create(screen, templ));
|
|
((struct r600_resource_global *)rbuffer)->chunk->real_buffer = rbuffer;
|
|
} else {
|
|
rbuffer = r600_alloc_buffer_struct(screen, templ);
|
|
}
|
|
|
|
rbuffer->domains = RADEON_DOMAIN_GTT;
|
|
rbuffer->flags = 0;
|
|
rbuffer->b.is_user_ptr = true;
|
|
util_range_add(&rbuffer->b.b, &rbuffer->valid_buffer_range, 0, templ->width0);
|
|
util_range_add(&rbuffer->b.b, &rbuffer->b.valid_buffer_range, 0, templ->width0);
|
|
|
|
/* Convert a user pointer to a buffer. */
|
|
rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0,
|
|
templ->usage == PIPE_USAGE_IMMUTABLE? RADEON_FLAG_READ_ONLY : 0);
|
|
if (!rbuffer->buf) {
|
|
FREE(rbuffer);
|
|
return NULL;
|
|
}
|
|
|
|
if (rscreen->info.r600_has_virtual_memory)
|
|
rbuffer->gpu_address =
|
|
ws->buffer_get_virtual_address(rbuffer->buf);
|
|
else
|
|
rbuffer->gpu_address = 0;
|
|
|
|
rbuffer->vram_usage = 0;
|
|
rbuffer->gart_usage = templ->width0;
|
|
|
|
return &rbuffer->b.b;
|
|
}
|