258 lines
8.0 KiB
C
258 lines
8.0 KiB
C
/*
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* Copyright (c) 2019 Zodiac Inflight Innovations
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jonathan Marek <jonathan@marek.ca>
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*/
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#include "etnaviv_compiler_nir.h"
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/* to map nir srcs should to etna_inst srcs */
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enum {
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SRC_0_1_2 = (0 << 0) | (1 << 2) | (2 << 4),
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SRC_0_1_X = (0 << 0) | (1 << 2) | (3 << 4),
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SRC_0_X_X = (0 << 0) | (3 << 2) | (3 << 4),
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SRC_0_X_1 = (0 << 0) | (3 << 2) | (1 << 4),
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SRC_0_1_0 = (0 << 0) | (1 << 2) | (0 << 4),
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SRC_X_X_0 = (3 << 0) | (3 << 2) | (0 << 4),
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SRC_0_X_0 = (0 << 0) | (3 << 2) | (0 << 4),
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};
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/* info to translate a nir op to etna_inst */
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struct etna_op_info {
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uint8_t opcode; /* INST_OPCODE_ */
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uint8_t src; /* SRC_ enum */
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uint8_t cond; /* INST_CONDITION_ */
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uint8_t type; /* INST_TYPE_ */
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};
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static const struct etna_op_info etna_ops[] = {
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[0 ... nir_num_opcodes - 1] = {0xff},
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#undef TRUE
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#undef FALSE
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#define OPCT(nir, op, src, cond, type) [nir_op_##nir] = { \
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INST_OPCODE_##op, \
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SRC_##src, \
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INST_CONDITION_##cond, \
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INST_TYPE_##type \
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}
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#define OPC(nir, op, src, cond) OPCT(nir, op, src, cond, F32)
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#define IOPC(nir, op, src, cond) OPCT(nir, op, src, cond, S32)
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#define UOPC(nir, op, src, cond) OPCT(nir, op, src, cond, U32)
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#define OP(nir, op, src) OPC(nir, op, src, TRUE)
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#define IOP(nir, op, src) IOPC(nir, op, src, TRUE)
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#define UOP(nir, op, src) UOPC(nir, op, src, TRUE)
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OP(mov, MOV, X_X_0), OP(fneg, MOV, X_X_0), OP(fabs, MOV, X_X_0), OP(fsat, MOV, X_X_0),
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OP(fmul, MUL, 0_1_X), OP(fadd, ADD, 0_X_1), OP(ffma, MAD, 0_1_2),
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OP(fdot2, DP2, 0_1_X), OP(fdot3, DP3, 0_1_X), OP(fdot4, DP4, 0_1_X),
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OPC(fmin, SELECT, 0_1_0, GT), OPC(fmax, SELECT, 0_1_0, LT),
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OP(ffract, FRC, X_X_0), OP(frcp, RCP, X_X_0), OP(frsq, RSQ, X_X_0),
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OP(fsqrt, SQRT, X_X_0), OP(fsin, SIN, X_X_0), OP(fcos, COS, X_X_0),
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OP(fsign, SIGN, X_X_0), OP(ffloor, FLOOR, X_X_0), OP(fceil, CEIL, X_X_0),
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OP(flog2, LOG, X_X_0), OP(fexp2, EXP, X_X_0),
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OPC(seq, SET, 0_1_X, EQ), OPC(sne, SET, 0_1_X, NE), OPC(sge, SET, 0_1_X, GE), OPC(slt, SET, 0_1_X, LT),
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OPC(fcsel, SELECT, 0_1_2, NZ),
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OP(fdiv, DIV, 0_1_X),
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OP(fddx, DSX, 0_X_0), OP(fddy, DSY, 0_X_0),
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/* type convert */
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IOP(i2f32, I2F, 0_X_X),
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UOP(u2f32, I2F, 0_X_X),
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IOP(f2i32, F2I, 0_X_X),
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UOP(f2u32, F2I, 0_X_X),
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UOP(b2f32, AND, 0_X_X), /* AND with fui(1.0f) */
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UOP(b2i32, AND, 0_X_X), /* AND with 1 */
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OPC(f2b32, CMP, 0_X_X, NE), /* != 0.0 */
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UOPC(i2b32, CMP, 0_X_X, NE), /* != 0 */
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/* arithmetic */
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IOP(iadd, ADD, 0_X_1),
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IOP(imul, IMULLO0, 0_1_X),
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/* IOP(imad, IMADLO0, 0_1_2), */
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IOP(ineg, ADD, X_X_0), /* ADD 0, -x */
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IOP(iabs, IABS, X_X_0),
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IOP(isign, SIGN, X_X_0),
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IOPC(imin, SELECT, 0_1_0, GT),
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IOPC(imax, SELECT, 0_1_0, LT),
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UOPC(umin, SELECT, 0_1_0, GT),
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UOPC(umax, SELECT, 0_1_0, LT),
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/* select */
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UOPC(b32csel, SELECT, 0_1_2, NZ),
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/* compare with int result */
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OPC(feq32, CMP, 0_1_X, EQ),
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OPC(fneu32, CMP, 0_1_X, NE),
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OPC(fge32, CMP, 0_1_X, GE),
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OPC(flt32, CMP, 0_1_X, LT),
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IOPC(ieq32, CMP, 0_1_X, EQ),
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IOPC(ine32, CMP, 0_1_X, NE),
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IOPC(ige32, CMP, 0_1_X, GE),
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IOPC(ilt32, CMP, 0_1_X, LT),
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UOPC(uge32, CMP, 0_1_X, GE),
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UOPC(ult32, CMP, 0_1_X, LT),
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/* bit ops */
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IOP(ior, OR, 0_X_1),
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IOP(iand, AND, 0_X_1),
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IOP(ixor, XOR, 0_X_1),
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IOP(inot, NOT, X_X_0),
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IOP(ishl, LSHIFT, 0_X_1),
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IOP(ishr, RSHIFT, 0_X_1),
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UOP(ushr, RSHIFT, 0_X_1),
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};
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void
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etna_emit_alu(struct etna_compile *c, nir_op op, struct etna_inst_dst dst,
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struct etna_inst_src src[3], bool saturate)
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{
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struct etna_op_info ei = etna_ops[op];
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unsigned swiz_scalar = INST_SWIZ_BROADCAST(ffs(dst.write_mask) - 1);
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if (ei.opcode == 0xff)
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compile_error(c, "Unhandled ALU op: %s\n", nir_op_infos[op].name);
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struct etna_inst inst = {
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.opcode = ei.opcode,
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.type = ei.type,
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.cond = ei.cond,
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.dst = dst,
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.sat = saturate,
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};
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switch (op) {
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case nir_op_fdiv:
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case nir_op_flog2:
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case nir_op_fsin:
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case nir_op_fcos:
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if (c->specs->has_new_transcendentals)
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inst.tex.amode = 1;
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/* fall through */
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case nir_op_frsq:
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case nir_op_frcp:
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case nir_op_fexp2:
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case nir_op_fsqrt:
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case nir_op_imul:
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/* scalar instructions we want src to be in x component */
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src[0].swiz = inst_swiz_compose(src[0].swiz, swiz_scalar);
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src[1].swiz = inst_swiz_compose(src[1].swiz, swiz_scalar);
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break;
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/* deal with instructions which don't have 1:1 mapping */
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case nir_op_b2f32:
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inst.src[2] = etna_immediate_float(1.0f);
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break;
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case nir_op_b2i32:
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inst.src[2] = etna_immediate_int(1);
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break;
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case nir_op_f2b32:
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inst.src[1] = etna_immediate_float(0.0f);
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break;
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case nir_op_i2b32:
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inst.src[1] = etna_immediate_int(0);
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break;
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case nir_op_ineg:
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inst.src[0] = etna_immediate_int(0);
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src[0].neg = 1;
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break;
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default:
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break;
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}
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/* set the "true" value for CMP instructions */
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if (inst.opcode == INST_OPCODE_CMP)
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inst.src[2] = etna_immediate_int(-1);
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for (unsigned j = 0; j < 3; j++) {
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unsigned i = ((ei.src >> j*2) & 3);
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if (i < 3)
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inst.src[j] = src[i];
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}
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emit_inst(c, &inst);
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}
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void
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etna_emit_tex(struct etna_compile *c, nir_texop op, unsigned texid, unsigned dst_swiz,
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struct etna_inst_dst dst, struct etna_inst_src coord,
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struct etna_inst_src lod_bias, struct etna_inst_src compare)
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{
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struct etna_inst inst = {
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.dst = dst,
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.tex.id = texid + (is_fs(c) ? 0 : c->specs->vertex_sampler_offset),
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.tex.swiz = dst_swiz,
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.src[0] = coord,
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};
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if (lod_bias.use)
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inst.src[1] = lod_bias;
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if (compare.use)
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inst.src[2] = compare;
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switch (op) {
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case nir_texop_tex: inst.opcode = INST_OPCODE_TEXLD; break;
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case nir_texop_txb: inst.opcode = INST_OPCODE_TEXLDB; break;
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case nir_texop_txl: inst.opcode = INST_OPCODE_TEXLDL; break;
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default:
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compile_error(c, "Unhandled NIR tex type: %d\n", op);
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}
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emit_inst(c, &inst);
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}
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void
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etna_emit_jump(struct etna_compile *c, unsigned block, struct etna_inst_src condition)
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{
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if (!condition.use) {
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emit_inst(c, &(struct etna_inst) {.opcode = INST_OPCODE_BRANCH, .imm = block });
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return;
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}
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struct etna_inst inst = {
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.opcode = INST_OPCODE_BRANCH,
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.cond = INST_CONDITION_NOT,
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.type = INST_TYPE_U32,
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.src[0] = condition,
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.imm = block,
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};
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inst.src[0].swiz = INST_SWIZ_BROADCAST(inst.src[0].swiz & 3);
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emit_inst(c, &inst);
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}
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void
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etna_emit_discard(struct etna_compile *c, struct etna_inst_src condition)
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{
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if (!condition.use) {
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emit_inst(c, &(struct etna_inst) { .opcode = INST_OPCODE_TEXKILL });
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return;
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}
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struct etna_inst inst = {
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.opcode = INST_OPCODE_TEXKILL,
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.cond = INST_CONDITION_NZ,
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.type = (c->specs->halti < 2) ? INST_TYPE_F32 : INST_TYPE_U32,
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.src[0] = condition,
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};
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inst.src[0].swiz = INST_SWIZ_BROADCAST(inst.src[0].swiz & 3);
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emit_inst(c, &inst);
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}
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