315 lines
14 KiB
C
315 lines
14 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "vk_format.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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static uint32_t
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get_depth_format(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
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switch (gfx->depth_att.vk_format) {
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case VK_FORMAT_D16_UNORM:
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case VK_FORMAT_D16_UNORM_S8_UINT:
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return D16_UNORM;
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case VK_FORMAT_X8_D24_UNORM_PACK32:
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case VK_FORMAT_D24_UNORM_S8_UINT:
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return D24_UNORM_X8_UINT;
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case VK_FORMAT_D32_SFLOAT:
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case VK_FORMAT_D32_SFLOAT_S8_UINT:
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return D32_FLOAT;
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default:
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return D16_UNORM;
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}
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}
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void
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genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
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const struct vk_dynamic_graphics_state *dyn =
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&cmd_buffer->vk.dynamic_graphics_state;
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if ((cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS)) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_CULL_MODE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_FRONT_FACE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_FACTORS) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_LINE_WIDTH)) {
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/* Take dynamic primitive topology in to account with
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* 3DSTATE_SF::MultisampleRasterizationMode
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*/
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VkPolygonMode dynamic_raster_mode =
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genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
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dyn->ia.primitive_topology);
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uint32_t ms_rast_mode =
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genX(ms_rasterization_mode)(pipeline, dynamic_raster_mode);
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bool aa_enable = anv_rasterization_aa_mode(dynamic_raster_mode,
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pipeline->line_mode);
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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.DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
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.LineWidth = dyn->rs.line.width,
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.AntialiasingEnable = aa_enable,
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.CullMode = genX(vk_to_intel_cullmode)[dyn->rs.cull_mode],
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.FrontWinding = genX(vk_to_intel_front_face)[dyn->rs.front_face],
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.MultisampleRasterizationMode = ms_rast_mode,
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.GlobalDepthOffsetEnableSolid = dyn->rs.depth_bias.enable,
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.GlobalDepthOffsetEnableWireframe = dyn->rs.depth_bias.enable,
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.GlobalDepthOffsetEnablePoint = dyn->rs.depth_bias.enable,
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.GlobalDepthOffsetConstant = dyn->rs.depth_bias.constant,
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.GlobalDepthOffsetScale = dyn->rs.depth_bias.slope,
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.GlobalDepthOffsetClamp = dyn->rs.depth_bias.clamp,
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};
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GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx7.sf);
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}
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if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_BLEND_CONSTANTS)) {
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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GENX(COLOR_CALC_STATE_length) * 4,
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64);
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struct GENX(COLOR_CALC_STATE) cc = {
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.BlendConstantColorRed = dyn->cb.blend_constants[0],
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.BlendConstantColorGreen = dyn->cb.blend_constants[1],
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.BlendConstantColorBlue = dyn->cb.blend_constants[2],
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.BlendConstantColorAlpha = dyn->cb.blend_constants[3],
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.StencilReferenceValue = dyn->ds.stencil.front.reference & 0xff,
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.BackfaceStencilReferenceValue = dyn->ds.stencil.back.reference & 0xff,
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};
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GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
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ccp.ColorCalcStatePointer = cc_state.offset;
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}
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}
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if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_LINE_STIPPLE)) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
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ls.LineStipplePattern = dyn->rs.line.stipple.pattern;
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ls.LineStippleInverseRepeatCount =
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1.0f / MAX2(1, dyn->rs.line.stipple.factor);
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ls.LineStippleRepeatCount = dyn->rs.line.stipple.factor;
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}
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}
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if ((cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS)) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_OP) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK)) {
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uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
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VkImageAspectFlags ds_aspects = 0;
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if (cmd_buffer->state.gfx.depth_att.vk_format != VK_FORMAT_UNDEFINED)
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ds_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
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if (cmd_buffer->state.gfx.stencil_att.vk_format != VK_FORMAT_UNDEFINED)
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ds_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
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struct vk_depth_stencil_state opt_ds = dyn->ds;
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vk_optimize_depth_stencil_state(&opt_ds, ds_aspects, true);
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struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
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.DoubleSidedStencilEnable = true,
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.StencilTestMask = opt_ds.stencil.front.compare_mask & 0xff,
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.StencilWriteMask = opt_ds.stencil.front.write_mask & 0xff,
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.BackfaceStencilTestMask = opt_ds.stencil.back.compare_mask & 0xff,
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.BackfaceStencilWriteMask = opt_ds.stencil.back.write_mask & 0xff,
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.DepthTestEnable = opt_ds.depth.test_enable,
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.DepthBufferWriteEnable = opt_ds.depth.write_enable,
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.DepthTestFunction = genX(vk_to_intel_compare_op)[opt_ds.depth.compare_op],
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.StencilTestEnable = opt_ds.stencil.test_enable,
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.StencilBufferWriteEnable = opt_ds.stencil.write_enable,
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.StencilFailOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.front.op.fail],
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.StencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.front.op.pass],
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.StencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.front.op.depth_fail],
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.StencilTestFunction = genX(vk_to_intel_compare_op)[opt_ds.stencil.front.op.compare],
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.BackfaceStencilFailOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.back.op.fail],
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.BackfaceStencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.back.op.pass],
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.BackfaceStencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.back.op.depth_fail],
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.BackfaceStencilTestFunction = genX(vk_to_intel_compare_op)[opt_ds.stencil.back.op.compare],
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};
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GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
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struct anv_state ds_state =
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anv_cmd_buffer_emit_dynamic(cmd_buffer, depth_stencil_dw,
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sizeof(depth_stencil_dw), 64);
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anv_batch_emit(&cmd_buffer->batch,
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GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
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dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
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}
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}
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if (cmd_buffer->state.gfx.index_buffer &&
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((cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER)) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE))) {
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struct anv_buffer *buffer = cmd_buffer->state.gfx.index_buffer;
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uint32_t offset = cmd_buffer->state.gfx.index_offset;
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#if GFX_VERx10 == 75
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anv_batch_emit(&cmd_buffer->batch, GFX75_3DSTATE_VF, vf) {
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vf.IndexedDrawCutIndexEnable = dyn->ia.primitive_restart_enable;
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vf.CutIndex = cmd_buffer->state.gfx.restart_index;
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}
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#endif
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
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#if GFX_VERx10 != 75
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ib.CutIndexEnable = dyn->ia.primitive_restart_enable;
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#endif
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ib.IndexFormat = cmd_buffer->state.gfx.index_type;
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ib.MOCS = anv_mocs(cmd_buffer->device,
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buffer->address.bo,
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ISL_SURF_USAGE_INDEX_BUFFER_BIT);
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ib.BufferStartingAddress = anv_address_add(buffer->address, offset);
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ib.BufferEndingAddress = anv_address_add(buffer->address,
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buffer->vk.size);
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}
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}
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/* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
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* threads or if we have dirty dynamic primitive topology state and
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* need to toggle 3DSTATE_WM::MultisampleRasterizationMode dynamically.
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*/
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if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
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VkPolygonMode dynamic_raster_mode =
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genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
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dyn->ia.primitive_topology);
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uint32_t dwords[GENX(3DSTATE_WM_length)];
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struct GENX(3DSTATE_WM) wm = {
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GENX(3DSTATE_WM_header),
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.ThreadDispatchEnable = anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) &&
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(pipeline->force_fragment_thread_dispatch ||
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!anv_cmd_buffer_all_color_write_masked(cmd_buffer)),
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.MultisampleRasterizationMode =
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genX(ms_rasterization_mode)(pipeline,
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dynamic_raster_mode),
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};
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GENX(3DSTATE_WM_pack)(NULL, dwords, &wm);
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx7.wm);
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}
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if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_RENDER_TARGETS) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS)) {
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const uint32_t samples = MAX2(1, cmd_buffer->state.gfx.samples);
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const struct vk_sample_locations_state *sl = dyn->ms.sample_locations;
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genX(emit_multisample)(&cmd_buffer->batch, samples,
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sl->per_pixel == samples ? sl : NULL);
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}
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if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
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const uint8_t color_writes = dyn->cb.color_write_enables;
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/* Blend states of each RT */
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uint32_t blend_dws[GENX(BLEND_STATE_length) +
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MAX_RTS * GENX(BLEND_STATE_ENTRY_length)];
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uint32_t *dws = blend_dws;
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memset(blend_dws, 0, sizeof(blend_dws));
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/* Skip this part */
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dws += GENX(BLEND_STATE_length);
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for (uint32_t i = 0; i < MAX_RTS; i++) {
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/* Disable anything above the current number of color attachments. */
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bool write_disabled = i >= cmd_buffer->state.gfx.color_att_count ||
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(color_writes & BITFIELD_BIT(i)) == 0;
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struct GENX(BLEND_STATE_ENTRY) entry = {
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.WriteDisableAlpha = write_disabled ||
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(pipeline->color_comp_writes[i] &
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VK_COLOR_COMPONENT_A_BIT) == 0,
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.WriteDisableRed = write_disabled ||
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(pipeline->color_comp_writes[i] &
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VK_COLOR_COMPONENT_R_BIT) == 0,
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.WriteDisableGreen = write_disabled ||
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(pipeline->color_comp_writes[i] &
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VK_COLOR_COMPONENT_G_BIT) == 0,
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.WriteDisableBlue = write_disabled ||
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(pipeline->color_comp_writes[i] &
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VK_COLOR_COMPONENT_B_BIT) == 0,
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.LogicOpFunction = genX(vk_to_intel_logic_op)[dyn->cb.logic_op],
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};
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GENX(BLEND_STATE_ENTRY_pack)(NULL, dws, &entry);
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dws += GENX(BLEND_STATE_ENTRY_length);
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}
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uint32_t num_dwords = GENX(BLEND_STATE_length) +
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GENX(BLEND_STATE_ENTRY_length) * MAX_RTS;
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struct anv_state blend_states =
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anv_cmd_buffer_merge_dynamic(cmd_buffer, blend_dws,
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pipeline->gfx7.blend_state, num_dwords, 64);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
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bsp.BlendStatePointer = blend_states.offset;
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}
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}
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/* When we're done, there is no more dirty gfx state. */
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vk_dynamic_graphics_state_clear_dirty(&cmd_buffer->vk.dynamic_graphics_state);
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cmd_buffer->state.gfx.dirty = 0;
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}
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void
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genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
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bool enable)
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{
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/* The NP PMA fix doesn't exist on gfx7 */
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}
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