514 lines
20 KiB
C
514 lines
20 KiB
C
/*
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* Copyright © Microsoft Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <directx/d3d12.h>
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#include "spirv_to_dxil.h"
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#include "nir_to_dxil.h"
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#include "nir_builder.h"
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#include "nir_vulkan.h"
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#include "dzn_nir.h"
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static nir_ssa_def *
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dzn_nir_create_bo_desc(nir_builder *b,
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nir_variable_mode mode,
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uint32_t desc_set,
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uint32_t binding,
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const char *name,
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unsigned access)
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{
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struct glsl_struct_field field = {
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.type = mode == nir_var_mem_ubo ?
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glsl_array_type(glsl_uint_type(), 4096, 4) :
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glsl_uint_type(),
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.name = "dummy_int",
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};
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const struct glsl_type *dummy_type =
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glsl_struct_type(&field, 1, "dummy_type", false);
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nir_variable *var =
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nir_variable_create(b->shader, mode, dummy_type, name);
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var->data.descriptor_set = desc_set;
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var->data.binding = binding;
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var->data.access = access;
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assert(mode == nir_var_mem_ubo || mode == nir_var_mem_ssbo);
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if (mode == nir_var_mem_ubo)
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b->shader->info.num_ubos++;
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else
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b->shader->info.num_ssbos++;
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VkDescriptorType desc_type =
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var->data.mode == nir_var_mem_ubo ?
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VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER :
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VK_DESCRIPTOR_TYPE_STORAGE_BUFFER;
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nir_address_format addr_format = nir_address_format_32bit_index_offset;
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nir_ssa_def *index =
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nir_vulkan_resource_index(b,
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nir_address_format_num_components(addr_format),
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nir_address_format_bit_size(addr_format),
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nir_imm_int(b, 0),
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.desc_set = desc_set,
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.binding = binding,
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.desc_type = desc_type);
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nir_ssa_def *desc =
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nir_load_vulkan_descriptor(b,
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nir_address_format_num_components(addr_format),
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nir_address_format_bit_size(addr_format),
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index,
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.desc_type = desc_type);
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return nir_channel(b, desc, 0);
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}
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nir_shader *
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dzn_nir_indirect_draw_shader(enum dzn_indirect_draw_type type)
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{
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const char *type_str[] = {
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"draw",
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"indexed_draw",
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"draw_triangle_fan",
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"indexed_draw_triangle_fan",
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};
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assert(type < ARRAY_SIZE(type_str));
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bool indexed = type == DZN_INDIRECT_INDEXED_DRAW ||
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type == DZN_INDIRECT_INDEXED_DRAW_TRIANGLE_FAN;
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bool triangle_fan = type == DZN_INDIRECT_DRAW_TRIANGLE_FAN ||
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type == DZN_INDIRECT_INDEXED_DRAW_TRIANGLE_FAN;
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nir_builder b =
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nir_builder_init_simple_shader(MESA_SHADER_COMPUTE,
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dxil_get_nir_compiler_options(),
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"dzn_meta_indirect_%s()",
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type_str[type]);
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b.shader->info.internal = true;
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struct glsl_struct_field field = {
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.type = glsl_uint_type(),
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.name = "dummy_int",
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};
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const struct glsl_type *dummy_type =
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glsl_struct_type(&field, 1, "dummy_type", false);
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nir_ssa_def *params_desc =
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dzn_nir_create_bo_desc(&b, nir_var_mem_ubo, 0, 0, "params", 0);
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nir_ssa_def *draw_buf_desc =
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dzn_nir_create_bo_desc(&b, nir_var_mem_ssbo, 0, 1, "draw_buf", ACCESS_NON_WRITEABLE);
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nir_ssa_def *exec_buf_desc =
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dzn_nir_create_bo_desc(&b, nir_var_mem_ssbo, 0, 2, "exec_buf", ACCESS_NON_READABLE);
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unsigned params_size =
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triangle_fan ?
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sizeof(struct dzn_indirect_draw_triangle_fan_rewrite_params) :
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sizeof(struct dzn_indirect_draw_rewrite_params);
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nir_ssa_def *params =
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nir_load_ubo(&b, params_size / 4, 32,
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params_desc, nir_imm_int(&b, 0),
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.align_mul = 4, .align_offset = 0, .range_base = 0, .range = ~0);
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nir_ssa_def *draw_stride = nir_channel(&b, params, 0);
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nir_ssa_def *exec_stride = nir_imm_int(&b, sizeof(struct dzn_indirect_draw_exec_params));
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nir_ssa_def *index =
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nir_channel(&b, nir_load_global_invocation_id(&b, 32), 0);
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nir_ssa_def *draw_offset = nir_imul(&b, draw_stride, index);
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nir_ssa_def *exec_offset = nir_imul(&b, exec_stride, index);
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nir_ssa_def *draw_info1 =
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nir_load_ssbo(&b, 4, 32, draw_buf_desc, draw_offset, .align_mul = 4);
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nir_ssa_def *draw_info2 =
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indexed ?
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nir_load_ssbo(&b, 1, 32, draw_buf_desc,
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nir_iadd_imm(&b, draw_offset, 16), .align_mul = 4) :
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nir_imm_int(&b, 0);
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nir_ssa_def *first_vertex = nir_channel(&b, draw_info1, indexed ? 3 : 2);
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nir_ssa_def *base_instance =
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indexed ? draw_info2 : nir_channel(&b, draw_info1, 3);
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nir_ssa_def *exec_vals[7] = {
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first_vertex,
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base_instance,
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};
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if (triangle_fan) {
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/* Patch {vertex,index}_count and first_index */
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nir_ssa_def *triangle_count =
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nir_usub_sat(&b, nir_channel(&b, draw_info1, 0), nir_imm_int(&b, 2));
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exec_vals[2] = nir_imul_imm(&b, triangle_count, 3);
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exec_vals[3] = nir_channel(&b, draw_info1, 1);
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exec_vals[4] = nir_imm_int(&b, 0);
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exec_vals[5] = indexed ? nir_channel(&b, draw_info1, 3) : nir_imm_int(&b, 0);
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exec_vals[6] = indexed ? draw_info2 : nir_channel(&b, draw_info1, 3);
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nir_ssa_def *triangle_fan_exec_buf_desc =
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dzn_nir_create_bo_desc(&b, nir_var_mem_ssbo, 0, 3,
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"triangle_fan_exec_buf",
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ACCESS_NON_READABLE);
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nir_ssa_def *triangle_fan_index_buf_stride = nir_channel(&b, params, 1);
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nir_ssa_def *triangle_fan_index_buf_addr_lo =
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nir_iadd(&b, nir_channel(&b, params, 2),
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nir_imul(&b, triangle_fan_index_buf_stride, index));
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nir_ssa_def *addr_lo_overflow =
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nir_ult(&b, triangle_fan_index_buf_addr_lo, nir_channel(&b, params, 2));
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nir_ssa_def *triangle_fan_index_buf_addr_hi =
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nir_iadd(&b, nir_channel(&b, params, 3),
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nir_bcsel(&b, addr_lo_overflow, nir_imm_int(&b, 1), nir_imm_int(&b, 0)));
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nir_ssa_def *triangle_fan_exec_vals[] = {
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triangle_fan_index_buf_addr_lo,
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triangle_fan_index_buf_addr_hi,
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nir_channel(&b, draw_info1, 2),
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triangle_count,
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nir_imm_int(&b, 1),
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nir_imm_int(&b, 1),
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};
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assert(sizeof(struct dzn_indirect_triangle_fan_rewrite_index_exec_params) == (ARRAY_SIZE(triangle_fan_exec_vals) * 4));
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nir_ssa_def *triangle_fan_exec_stride =
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nir_imm_int(&b, sizeof(struct dzn_indirect_triangle_fan_rewrite_index_exec_params));
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nir_ssa_def *triangle_fan_exec_offset =
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nir_imul(&b, triangle_fan_exec_stride, index);
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nir_store_ssbo(&b, nir_vec(&b, &triangle_fan_exec_vals[0], 4),
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triangle_fan_exec_buf_desc, triangle_fan_exec_offset,
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.write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 4);
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nir_store_ssbo(&b, nir_vec(&b, &triangle_fan_exec_vals[4], 2),
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triangle_fan_exec_buf_desc,
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nir_iadd_imm(&b, triangle_fan_exec_offset, 16),
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.write_mask = 0x3, .access = ACCESS_NON_READABLE, .align_mul = 4);
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nir_ssa_def *ibview_vals[] = {
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triangle_fan_index_buf_addr_lo,
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triangle_fan_index_buf_addr_hi,
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triangle_fan_index_buf_stride,
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nir_imm_int(&b, DXGI_FORMAT_R32_UINT),
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};
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nir_store_ssbo(&b, nir_vec(&b, ibview_vals, ARRAY_SIZE(ibview_vals)),
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exec_buf_desc, exec_offset,
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.write_mask = 0x3, .access = ACCESS_NON_READABLE, .align_mul = 4);
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exec_offset = nir_iadd_imm(&b, exec_offset, ARRAY_SIZE(ibview_vals) * 4);
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} else {
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exec_vals[2] = nir_channel(&b, draw_info1, 0);
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exec_vals[3] = nir_channel(&b, draw_info1, 1);
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exec_vals[4] = nir_channel(&b, draw_info1, 2);
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exec_vals[5] = nir_channel(&b, draw_info1, 3);
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exec_vals[6] = draw_info2;
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}
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nir_store_ssbo(&b, nir_vec(&b, exec_vals, 4),
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exec_buf_desc, exec_offset,
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.write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 4);
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nir_store_ssbo(&b, nir_vec(&b, &exec_vals[4], 3),
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exec_buf_desc, nir_iadd_imm(&b, exec_offset, 16),
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.write_mask = 7, .access = ACCESS_NON_READABLE, .align_mul = 4);
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return b.shader;
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}
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nir_shader *
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dzn_nir_triangle_fan_rewrite_index_shader(uint8_t old_index_size)
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{
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assert(old_index_size == 0 || old_index_size == 2 || old_index_size == 4);
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nir_builder b =
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nir_builder_init_simple_shader(MESA_SHADER_COMPUTE,
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dxil_get_nir_compiler_options(),
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"dzn_meta_triangle_rewrite_index(old_index_size=%d)",
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old_index_size);
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b.shader->info.internal = true;
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nir_ssa_def *params_desc =
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dzn_nir_create_bo_desc(&b, nir_var_mem_ubo, 0, 0, "params", 0);
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nir_ssa_def *new_index_buf_desc =
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dzn_nir_create_bo_desc(&b, nir_var_mem_ssbo, 0, 1,
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"new_index_buf", ACCESS_NON_READABLE);
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nir_ssa_def *old_index_buf_desc = NULL;
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if (old_index_size > 0) {
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old_index_buf_desc =
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dzn_nir_create_bo_desc(&b, nir_var_mem_ssbo, 0, 2,
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"old_index_buf", ACCESS_NON_WRITEABLE);
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}
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nir_ssa_def *params =
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nir_load_ubo(&b, sizeof(struct dzn_triangle_fan_rewrite_index_params) / 4, 32,
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params_desc, nir_imm_int(&b, 0),
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.align_mul = 4, .align_offset = 0, .range_base = 0, .range = ~0);
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nir_ssa_def *triangle = nir_channel(&b, nir_load_global_invocation_id(&b, 32), 0);
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nir_ssa_def *new_indices;
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if (old_index_size > 0) {
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nir_ssa_def *old_first_index = nir_channel(&b, params, 0);
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nir_ssa_def *old_index0_offset =
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nir_imul_imm(&b, old_first_index, old_index_size);
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nir_ssa_def *old_index1_offset =
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nir_imul_imm(&b, nir_iadd(&b, nir_iadd_imm(&b, triangle, 1), old_first_index),
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old_index_size);
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nir_ssa_def *old_index0 =
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nir_load_ssbo(&b, 1, 32, old_index_buf_desc,
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old_index_size == 2 ? nir_iand_imm(&b, old_index0_offset, ~3ULL) : old_index0_offset,
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.align_mul = 4);
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if (old_index_size == 2) {
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old_index0 =
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nir_bcsel(&b,
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nir_ieq_imm(&b, nir_iand_imm(&b, old_index0_offset, 0x2), 0),
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nir_iand_imm(&b, old_index0, 0xffff),
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nir_ushr_imm(&b, old_index0, 16));
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}
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nir_ssa_def *old_index12 =
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nir_load_ssbo(&b, 2, 32, old_index_buf_desc,
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old_index_size == 2 ? nir_iand_imm(&b, old_index1_offset, ~3ULL) : old_index1_offset,
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.align_mul = 4);
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if (old_index_size == 2) {
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nir_ssa_def *indices[] = {
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nir_iand_imm(&b, nir_channel(&b, old_index12, 0), 0xffff),
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nir_ushr_imm(&b, nir_channel(&b, old_index12, 0), 16),
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nir_iand_imm(&b, nir_channel(&b, old_index12, 1), 0xffff),
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};
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old_index12 =
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nir_bcsel(&b,
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nir_ieq_imm(&b, nir_iand_imm(&b, old_index1_offset, 0x2), 0),
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nir_vec2(&b, indices[0], indices[1]),
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nir_vec2(&b, indices[1], indices[2]));
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}
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/* TODO: VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT */
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new_indices =
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nir_vec3(&b, nir_channel(&b, old_index12, 0),
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nir_channel(&b, old_index12, 1), old_index0);
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} else {
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nir_ssa_def *first_vertex = nir_channel(&b, params, 0);
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new_indices =
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nir_vec3(&b,
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nir_iadd(&b, nir_iadd_imm(&b, triangle, 1), first_vertex),
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nir_iadd(&b, nir_iadd_imm(&b, triangle, 2), first_vertex),
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first_vertex);
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}
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nir_ssa_def *new_index_offset =
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nir_imul_imm(&b, triangle, 4 * 3);
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nir_store_ssbo(&b, new_indices, new_index_buf_desc,
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new_index_offset,
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.write_mask = 7, .access = ACCESS_NON_READABLE, .align_mul = 4);
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return b.shader;
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}
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nir_shader *
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dzn_nir_blit_vs(void)
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{
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nir_builder b =
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nir_builder_init_simple_shader(MESA_SHADER_VERTEX,
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dxil_get_nir_compiler_options(),
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"dzn_meta_blit_vs()");
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b.shader->info.internal = true;
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nir_ssa_def *params_desc =
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dzn_nir_create_bo_desc(&b, nir_var_mem_ubo, 0, 0, "params", 0);
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nir_variable *out_pos =
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nir_variable_create(b.shader, nir_var_shader_out, glsl_vec4_type(),
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"gl_Position");
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out_pos->data.location = VARYING_SLOT_POS;
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out_pos->data.driver_location = 0;
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nir_variable *out_coords =
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nir_variable_create(b.shader, nir_var_shader_out, glsl_vec_type(3),
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"coords");
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out_coords->data.location = VARYING_SLOT_TEX0;
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out_coords->data.driver_location = 1;
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nir_ssa_def *vertex = nir_load_vertex_id(&b);
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nir_ssa_def *base = nir_imul_imm(&b, vertex, 4 * sizeof(float));
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nir_ssa_def *coords =
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nir_load_ubo(&b, 4, 32, params_desc, base,
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.align_mul = 16, .align_offset = 0, .range_base = 0, .range = ~0);
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nir_ssa_def *pos =
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nir_vec4(&b, nir_channel(&b, coords, 0), nir_channel(&b, coords, 1),
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nir_imm_float(&b, 0.0), nir_imm_float(&b, 1.0));
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nir_ssa_def *z_coord =
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nir_load_ubo(&b, 1, 32, params_desc, nir_imm_int(&b, 4 * 4 * sizeof(float)),
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.align_mul = 64, .align_offset = 0, .range_base = 0, .range = ~0);
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coords = nir_vec3(&b, nir_channel(&b, coords, 2), nir_channel(&b, coords, 3), z_coord);
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nir_store_var(&b, out_pos, pos, 0xf);
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nir_store_var(&b, out_coords, coords, 0x7);
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return b.shader;
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}
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nir_shader *
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dzn_nir_blit_fs(const struct dzn_nir_blit_info *info)
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{
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bool ms = info->src_samples > 1;
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nir_alu_type nir_out_type =
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nir_get_nir_type_for_glsl_base_type(info->out_type);
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uint32_t coord_comps =
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glsl_get_sampler_dim_coordinate_components(info->sampler_dim) +
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info->src_is_array;
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nir_builder b =
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nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT,
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dxil_get_nir_compiler_options(),
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"dzn_meta_blit_fs()");
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b.shader->info.internal = true;
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const struct glsl_type *tex_type =
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glsl_texture_type(info->sampler_dim, info->src_is_array, info->out_type);
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nir_variable *tex_var =
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nir_variable_create(b.shader, nir_var_uniform, tex_type, "texture");
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nir_deref_instr *tex_deref = nir_build_deref_var(&b, tex_var);
|
||
|
||
nir_variable *pos_var =
|
||
nir_variable_create(b.shader, nir_var_shader_in,
|
||
glsl_vector_type(GLSL_TYPE_FLOAT, 4),
|
||
"gl_FragCoord");
|
||
pos_var->data.location = VARYING_SLOT_POS;
|
||
pos_var->data.driver_location = 0;
|
||
|
||
nir_variable *coord_var =
|
||
nir_variable_create(b.shader, nir_var_shader_in,
|
||
glsl_vector_type(GLSL_TYPE_FLOAT, 3),
|
||
"coord");
|
||
coord_var->data.location = VARYING_SLOT_TEX0;
|
||
coord_var->data.driver_location = 1;
|
||
nir_ssa_def *coord =
|
||
nir_channels(&b, nir_load_var(&b, coord_var), (1 << coord_comps) - 1);
|
||
|
||
uint32_t out_comps =
|
||
(info->loc == FRAG_RESULT_DEPTH || info->loc == FRAG_RESULT_STENCIL) ? 1 : 4;
|
||
nir_variable *out =
|
||
nir_variable_create(b.shader, nir_var_shader_out,
|
||
glsl_vector_type(info->out_type, out_comps),
|
||
"out");
|
||
out->data.location = info->loc;
|
||
|
||
nir_ssa_def *res = NULL;
|
||
|
||
if (info->resolve) {
|
||
/* When resolving a float type, we need to calculate the average of all
|
||
* samples. For integer resolve, Vulkan says that one sample should be
|
||
* chosen without telling which. Let's just pick the first one in that
|
||
* case.
|
||
*/
|
||
|
||
unsigned nsamples = info->out_type == GLSL_TYPE_FLOAT ?
|
||
info->src_samples : 1;
|
||
for (unsigned s = 0; s < nsamples; s++) {
|
||
nir_tex_instr *tex = nir_tex_instr_create(b.shader, 4);
|
||
|
||
tex->op = nir_texop_txf_ms;
|
||
tex->dest_type = nir_out_type;
|
||
tex->texture_index = 0;
|
||
tex->is_array = info->src_is_array;
|
||
tex->sampler_dim = info->sampler_dim;
|
||
|
||
tex->src[0].src_type = nir_tex_src_coord;
|
||
tex->src[0].src = nir_src_for_ssa(nir_f2i32(&b, coord));
|
||
tex->coord_components = coord_comps;
|
||
|
||
tex->src[1].src_type = nir_tex_src_ms_index;
|
||
tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, s));
|
||
|
||
tex->src[2].src_type = nir_tex_src_lod;
|
||
tex->src[2].src = nir_src_for_ssa(nir_imm_int(&b, 0));
|
||
|
||
tex->src[3].src_type = nir_tex_src_texture_deref;
|
||
tex->src[3].src = nir_src_for_ssa(&tex_deref->dest.ssa);
|
||
|
||
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, NULL);
|
||
|
||
nir_builder_instr_insert(&b, &tex->instr);
|
||
res = res ? nir_fadd(&b, res, &tex->dest.ssa) : &tex->dest.ssa;
|
||
}
|
||
|
||
if (nsamples > 1) {
|
||
unsigned type_sz = nir_alu_type_get_type_size(nir_out_type);
|
||
res = nir_fmul(&b, res, nir_imm_floatN_t(&b, 1.0f / nsamples, type_sz));
|
||
}
|
||
} else {
|
||
nir_tex_instr *tex =
|
||
nir_tex_instr_create(b.shader, ms ? 4 : 3);
|
||
|
||
tex->dest_type = nir_out_type;
|
||
tex->is_array = info->src_is_array;
|
||
tex->sampler_dim = info->sampler_dim;
|
||
|
||
if (ms) {
|
||
tex->op = nir_texop_txf_ms;
|
||
|
||
tex->src[0].src_type = nir_tex_src_coord;
|
||
tex->src[0].src = nir_src_for_ssa(nir_f2i32(&b, coord));
|
||
tex->coord_components = coord_comps;
|
||
|
||
tex->src[1].src_type = nir_tex_src_ms_index;
|
||
tex->src[1].src = nir_src_for_ssa(nir_load_sample_id(&b));
|
||
|
||
tex->src[2].src_type = nir_tex_src_lod;
|
||
tex->src[2].src = nir_src_for_ssa(nir_imm_int(&b, 0));
|
||
|
||
tex->src[3].src_type = nir_tex_src_texture_deref;
|
||
tex->src[3].src = nir_src_for_ssa(&tex_deref->dest.ssa);
|
||
} else {
|
||
nir_variable *sampler_var =
|
||
nir_variable_create(b.shader, nir_var_uniform, glsl_bare_sampler_type(), "sampler");
|
||
nir_deref_instr *sampler_deref = nir_build_deref_var(&b, sampler_var);
|
||
|
||
tex->op = nir_texop_tex;
|
||
tex->sampler_index = 0;
|
||
|
||
tex->src[0].src_type = nir_tex_src_coord;
|
||
tex->src[0].src = nir_src_for_ssa(coord);
|
||
tex->coord_components = coord_comps;
|
||
|
||
tex->src[1].src_type = nir_tex_src_texture_deref;
|
||
tex->src[1].src = nir_src_for_ssa(&tex_deref->dest.ssa);
|
||
|
||
tex->src[2].src_type = nir_tex_src_sampler_deref;
|
||
tex->src[2].src = nir_src_for_ssa(&sampler_deref->dest.ssa);
|
||
}
|
||
|
||
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, NULL);
|
||
nir_builder_instr_insert(&b, &tex->instr);
|
||
res = &tex->dest.ssa;
|
||
}
|
||
|
||
nir_store_var(&b, out, nir_channels(&b, res, (1 << out_comps) - 1), 0xf);
|
||
|
||
return b.shader;
|
||
}
|