270 lines
10 KiB
C
270 lines
10 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors: Marek Olšák <maraeo@gmail.com>
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*
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*/
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#include "r600_cs.h"
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/* 2xMSAA
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* There are two locations (4, 4), (-4, -4). */
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const uint32_t eg_sample_locs_2x[4] = {
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FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
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FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
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FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
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FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
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};
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const unsigned eg_max_dist_2x = 4;
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/* 4xMSAA
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* There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
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const uint32_t eg_sample_locs_4x[4] = {
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FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
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FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
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FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
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FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
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};
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const unsigned eg_max_dist_4x = 6;
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/* Cayman 8xMSAA */
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static const uint32_t cm_sample_locs_8x[] = {
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FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
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FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
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FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
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FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
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FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
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FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
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FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
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FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
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};
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static const unsigned cm_max_dist_8x = 8;
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/* Cayman 16xMSAA */
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static const uint32_t cm_sample_locs_16x[] = {
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FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
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FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
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FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
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FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
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FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
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FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
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FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
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FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
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FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
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FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
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FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
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FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
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FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
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FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
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FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
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FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
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};
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static const unsigned cm_max_dist_16x = 8;
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void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
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unsigned sample_index, float *out_value)
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{
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int offset, index;
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struct {
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int idx:4;
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} val;
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switch (sample_count) {
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case 1:
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default:
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out_value[0] = out_value[1] = 0.5;
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break;
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case 2:
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offset = 4 * (sample_index * 2);
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val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
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out_value[0] = (float)(val.idx + 8) / 16.0f;
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val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
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out_value[1] = (float)(val.idx + 8) / 16.0f;
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break;
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case 4:
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offset = 4 * (sample_index * 2);
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val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
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out_value[0] = (float)(val.idx + 8) / 16.0f;
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val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
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out_value[1] = (float)(val.idx + 8) / 16.0f;
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break;
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case 8:
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offset = 4 * (sample_index % 4 * 2);
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index = (sample_index / 4) * 4;
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val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
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out_value[0] = (float)(val.idx + 8) / 16.0f;
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val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
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out_value[1] = (float)(val.idx + 8) / 16.0f;
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break;
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case 16:
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offset = 4 * (sample_index % 4 * 2);
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index = (sample_index / 4) * 4;
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val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
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out_value[0] = (float)(val.idx + 8) / 16.0f;
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val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
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out_value[1] = (float)(val.idx + 8) / 16.0f;
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break;
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}
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}
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void cayman_init_msaa(struct pipe_context *ctx)
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{
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struct r600_common_context *rctx = (struct r600_common_context*)ctx;
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int i;
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cayman_get_sample_position(ctx, 1, 0, rctx->sample_locations_1x[0]);
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for (i = 0; i < 2; i++)
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cayman_get_sample_position(ctx, 2, i, rctx->sample_locations_2x[i]);
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for (i = 0; i < 4; i++)
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cayman_get_sample_position(ctx, 4, i, rctx->sample_locations_4x[i]);
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for (i = 0; i < 8; i++)
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cayman_get_sample_position(ctx, 8, i, rctx->sample_locations_8x[i]);
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for (i = 0; i < 16; i++)
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cayman_get_sample_position(ctx, 16, i, rctx->sample_locations_16x[i]);
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}
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void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
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{
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switch (nr_samples) {
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default:
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case 1:
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radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
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radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
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radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
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radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
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break;
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case 2:
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radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
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radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
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radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
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radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
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break;
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case 4:
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radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
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radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
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radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
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radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
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break;
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case 8:
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radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
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radeon_emit(cs, cm_sample_locs_8x[0]);
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radeon_emit(cs, cm_sample_locs_8x[4]);
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, cm_sample_locs_8x[1]);
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radeon_emit(cs, cm_sample_locs_8x[5]);
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, cm_sample_locs_8x[2]);
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radeon_emit(cs, cm_sample_locs_8x[6]);
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, cm_sample_locs_8x[3]);
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radeon_emit(cs, cm_sample_locs_8x[7]);
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break;
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case 16:
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radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
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radeon_emit(cs, cm_sample_locs_16x[0]);
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radeon_emit(cs, cm_sample_locs_16x[4]);
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radeon_emit(cs, cm_sample_locs_16x[8]);
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radeon_emit(cs, cm_sample_locs_16x[12]);
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radeon_emit(cs, cm_sample_locs_16x[1]);
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radeon_emit(cs, cm_sample_locs_16x[5]);
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radeon_emit(cs, cm_sample_locs_16x[9]);
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radeon_emit(cs, cm_sample_locs_16x[13]);
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radeon_emit(cs, cm_sample_locs_16x[2]);
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radeon_emit(cs, cm_sample_locs_16x[6]);
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radeon_emit(cs, cm_sample_locs_16x[10]);
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radeon_emit(cs, cm_sample_locs_16x[14]);
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radeon_emit(cs, cm_sample_locs_16x[3]);
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radeon_emit(cs, cm_sample_locs_16x[7]);
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radeon_emit(cs, cm_sample_locs_16x[11]);
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radeon_emit(cs, cm_sample_locs_16x[15]);
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break;
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}
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}
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void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
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int ps_iter_samples, int overrast_samples,
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unsigned sc_mode_cntl_1)
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{
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int setup_samples = nr_samples > 1 ? nr_samples :
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overrast_samples > 1 ? overrast_samples : 0;
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/* Required by OpenGL line rasterization.
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*
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* TODO: We should also enable perpendicular endcaps for AA lines,
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* but that requires implementing line stippling in the pixel
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* shader. SC can only do line stippling with axis-aligned
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* endcaps.
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*/
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unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
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if (setup_samples > 1) {
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/* indexed by log2(nr_samples) */
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unsigned max_dist[] = {
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0,
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eg_max_dist_2x,
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eg_max_dist_4x,
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cm_max_dist_8x,
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cm_max_dist_16x
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};
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unsigned log_samples = util_logbase2(setup_samples);
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unsigned log_ps_iter_samples =
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util_logbase2(util_next_power_of_two(ps_iter_samples));
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radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
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radeon_emit(cs, sc_line_cntl |
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S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
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radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
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S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
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S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
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if (nr_samples > 1) {
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radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
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S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
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S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
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S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
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S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
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S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
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S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
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radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
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EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
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sc_mode_cntl_1);
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} else if (overrast_samples > 1) {
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radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
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S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
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S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
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S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
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radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
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sc_mode_cntl_1);
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}
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} else {
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radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
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radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
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radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
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radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
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S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
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S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
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radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
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sc_mode_cntl_1);
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}
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}
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