266 lines
8.9 KiB
C
266 lines
8.9 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/**
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* This file contains helpers for writing commands to commands streams.
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*/
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#ifndef SI_BUILD_PM4_H
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#define SI_BUILD_PM4_H
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#include "si_pipe.h"
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#include "sid.h"
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static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg < SI_CONTEXT_REG_OFFSET);
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assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
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radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
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}
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static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_config_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= SI_CONTEXT_REG_OFFSET);
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assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
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radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
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}
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static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_context_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
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unsigned reg, unsigned idx,
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unsigned value)
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{
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assert(reg >= SI_CONTEXT_REG_OFFSET);
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assert(cs->current.cdw + 3 <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
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radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
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radeon_emit(cs, value);
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}
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static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
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assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
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radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
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}
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static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_sh_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
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{
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assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
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assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
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}
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static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
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{
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radeon_set_uconfig_reg_seq(cs, reg, 1);
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radeon_emit(cs, value);
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}
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static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
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struct si_screen *screen,
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unsigned reg, unsigned idx,
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unsigned value)
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{
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assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
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assert(cs->current.cdw + 3 <= cs->current.max_dw);
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assert(idx != 0);
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unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX;
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if (screen->info.chip_class < GFX9 ||
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(screen->info.chip_class == GFX9 && screen->info.me_fw_version < 26))
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opcode = PKT3_SET_UCONFIG_REG;
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radeon_emit(cs, PKT3(opcode, 1, 0));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
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radeon_emit(cs, value);
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}
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static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg,
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unsigned value, unsigned mask)
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{
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assert(reg >= SI_CONTEXT_REG_OFFSET);
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assert(cs->current.cdw + 4 <= cs->current.max_dw);
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radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
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radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
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radeon_emit(cs, mask);
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radeon_emit(cs, value);
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}
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/* Emit PKT3_CONTEXT_REG_RMW if the register value is different. */
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static inline void radeon_opt_set_context_reg_rmw(struct si_context *sctx, unsigned offset,
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enum si_tracked_reg reg, unsigned value,
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unsigned mask)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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assert((value & ~mask) == 0);
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value &= mask;
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if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
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sctx->tracked_regs.reg_value[reg] != value) {
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radeon_set_context_reg_rmw(cs, offset, value, mask);
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sctx->tracked_regs.reg_saved |= 0x1ull << reg;
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sctx->tracked_regs.reg_value[reg] = value;
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}
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}
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/* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
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static inline void radeon_opt_set_context_reg(struct si_context *sctx, unsigned offset,
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enum si_tracked_reg reg, unsigned value)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
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sctx->tracked_regs.reg_value[reg] != value) {
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radeon_set_context_reg(cs, offset, value);
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sctx->tracked_regs.reg_saved |= 0x1ull << reg;
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sctx->tracked_regs.reg_value[reg] = value;
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}
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}
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/**
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* Set 2 consecutive registers if any registers value is different.
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* @param offset starting register offset
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* @param value1 is written to first register
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* @param value2 is written to second register
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*/
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static inline void radeon_opt_set_context_reg2(struct si_context *sctx, unsigned offset,
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enum si_tracked_reg reg, unsigned value1,
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unsigned value2)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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if (((sctx->tracked_regs.reg_saved >> reg) & 0x3) != 0x3 ||
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sctx->tracked_regs.reg_value[reg] != value1 ||
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sctx->tracked_regs.reg_value[reg+1] != value2) {
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radeon_set_context_reg_seq(cs, offset, 2);
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radeon_emit(cs, value1);
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radeon_emit(cs, value2);
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sctx->tracked_regs.reg_value[reg] = value1;
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sctx->tracked_regs.reg_value[reg+1] = value2;
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sctx->tracked_regs.reg_saved |= 0x3ull << reg;
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}
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}
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/**
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* Set 3 consecutive registers if any registers value is different.
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*/
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static inline void radeon_opt_set_context_reg3(struct si_context *sctx, unsigned offset,
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enum si_tracked_reg reg, unsigned value1,
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unsigned value2, unsigned value3)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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if (((sctx->tracked_regs.reg_saved >> reg) & 0x7) != 0x7 ||
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sctx->tracked_regs.reg_value[reg] != value1 ||
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sctx->tracked_regs.reg_value[reg+1] != value2 ||
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sctx->tracked_regs.reg_value[reg+2] != value3) {
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radeon_set_context_reg_seq(cs, offset, 3);
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radeon_emit(cs, value1);
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radeon_emit(cs, value2);
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radeon_emit(cs, value3);
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sctx->tracked_regs.reg_value[reg] = value1;
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sctx->tracked_regs.reg_value[reg+1] = value2;
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sctx->tracked_regs.reg_value[reg+2] = value3;
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sctx->tracked_regs.reg_saved |= 0x7ull << reg;
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}
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}
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/**
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* Set 4 consecutive registers if any registers value is different.
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*/
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static inline void radeon_opt_set_context_reg4(struct si_context *sctx, unsigned offset,
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enum si_tracked_reg reg, unsigned value1,
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unsigned value2, unsigned value3,
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unsigned value4)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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if (((sctx->tracked_regs.reg_saved >> reg) & 0xf) != 0xf ||
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sctx->tracked_regs.reg_value[reg] != value1 ||
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sctx->tracked_regs.reg_value[reg+1] != value2 ||
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sctx->tracked_regs.reg_value[reg+2] != value3 ||
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sctx->tracked_regs.reg_value[reg+3] != value4) {
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radeon_set_context_reg_seq(cs, offset, 4);
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radeon_emit(cs, value1);
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radeon_emit(cs, value2);
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radeon_emit(cs, value3);
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radeon_emit(cs, value4);
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sctx->tracked_regs.reg_value[reg] = value1;
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sctx->tracked_regs.reg_value[reg+1] = value2;
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sctx->tracked_regs.reg_value[reg+2] = value3;
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sctx->tracked_regs.reg_value[reg+3] = value4;
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sctx->tracked_regs.reg_saved |= 0xfull << reg;
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}
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}
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/**
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* Set consecutive registers if any registers value is different.
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*/
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static inline void radeon_opt_set_context_regn(struct si_context *sctx, unsigned offset,
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unsigned *value, unsigned *saved_val,
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unsigned num)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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int i, j;
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for (i = 0; i < num; i++) {
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if (saved_val[i] != value[i]) {
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radeon_set_context_reg_seq(cs, offset, num);
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for (j = 0; j < num; j++)
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radeon_emit(cs, value[j]);
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memcpy(saved_val, value, sizeof(uint32_t) * num);
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break;
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}
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}
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}
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#endif
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