312 lines
9.5 KiB
C
312 lines
9.5 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef SI_SHADER_PRIVATE_H
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#define SI_SHADER_PRIVATE_H
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#include "si_shader.h"
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#include "gallivm/lp_bld_init.h"
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#include "gallivm/lp_bld_tgsi.h"
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#include "tgsi/tgsi_parse.h"
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#include "ac_llvm_util.h"
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#include "ac_llvm_build.h"
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#include <llvm-c/Core.h>
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#include <llvm-c/TargetMachine.h>
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struct pipe_debug_callback;
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struct ac_shader_binary;
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#define RADEON_LLVM_MAX_INPUT_SLOTS 32
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#define RADEON_LLVM_MAX_INPUTS 32 * 4
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#define RADEON_LLVM_MAX_OUTPUTS 32 * 4
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#define RADEON_LLVM_INITIAL_CF_DEPTH 4
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#define RADEON_LLVM_MAX_SYSTEM_VALUES 11
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#define RADEON_LLVM_MAX_ADDRS 16
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struct si_llvm_flow;
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struct si_shader_context {
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struct lp_build_tgsi_context bld_base;
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struct gallivm_state gallivm;
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struct ac_llvm_context ac;
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struct si_shader *shader;
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struct si_screen *screen;
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unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
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/* For clamping the non-constant index in resource indexing: */
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unsigned num_const_buffers;
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unsigned num_shader_buffers;
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unsigned num_images;
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unsigned num_samplers;
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/* Whether the prolog will be compiled separately. */
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bool separate_prolog;
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/** This function is responsible for initilizing the inputs array and will be
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* called once for each input declared in the TGSI shader.
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*/
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void (*load_input)(struct si_shader_context *,
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unsigned input_index,
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const struct tgsi_full_declaration *decl,
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LLVMValueRef out[4]);
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void (*load_system_value)(struct si_shader_context *,
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unsigned index,
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const struct tgsi_full_declaration *decl);
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void (*declare_memory_region)(struct si_shader_context *,
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const struct tgsi_full_declaration *decl);
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/** This array contains the input values for the shader. Typically these
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* values will be in the form of a target intrinsic that will inform the
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* backend how to load the actual inputs to the shader.
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*/
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struct tgsi_full_declaration input_decls[RADEON_LLVM_MAX_INPUT_SLOTS];
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LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
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LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
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LLVMValueRef addrs[RADEON_LLVM_MAX_ADDRS][TGSI_NUM_CHANNELS];
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/** This pointer is used to contain the temporary values.
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* The amount of temporary used in tgsi can't be bound to a max value and
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* thus we must allocate this array at runtime.
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*/
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LLVMValueRef *temps;
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unsigned temps_count;
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LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
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LLVMValueRef *imms;
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unsigned imms_num;
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struct si_llvm_flow *flow;
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unsigned flow_depth;
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unsigned flow_depth_max;
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struct tgsi_array_info *temp_arrays;
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LLVMValueRef *temp_array_allocas;
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LLVMValueRef undef_alloca;
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LLVMValueRef main_fn;
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LLVMTypeRef return_type;
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/* Parameter indices for LLVMGetParam. */
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int param_rw_buffers;
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int param_const_and_shader_buffers;
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int param_samplers_and_images;
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/* Common inputs for merged shaders. */
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int param_merged_wave_info;
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int param_merged_scratch_offset;
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/* API VS */
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int param_vertex_buffers;
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int param_base_vertex;
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int param_start_instance;
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int param_draw_id;
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int param_vertex_id;
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int param_rel_auto_id;
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int param_vs_prim_id;
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int param_instance_id;
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int param_vertex_index0;
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/* VS states and layout of LS outputs / TCS inputs at the end
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* [0] = clamp vertex color
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* [1] = indexed
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* [8:20] = stride between patches in DW = num_inputs * num_vertices * 4
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* max = 32*32*4 + 32*4
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* [24:31] = stride between vertices in DW = num_inputs * 4
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* max = 32*4
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*/
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int param_vs_state_bits;
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/* HW VS */
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int param_streamout_config;
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int param_streamout_write_index;
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int param_streamout_offset[4];
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/* API TCS & TES */
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/* Layout of TCS outputs in the offchip buffer
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* # 6 bits
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* [0:5] = the number of patches per threadgroup, max = NUM_PATCHES (40)
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* # 6 bits
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* [6:11] = the number of output vertices per patch, max = 32
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* # 20 bits
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* [12:31] = the offset of per patch attributes in the buffer in bytes.
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* max = NUM_PATCHES*32*32*16
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*/
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int param_tcs_offchip_layout;
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/* API TCS */
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/* Offsets where TCS outputs and TCS patch outputs live in LDS:
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* [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
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* [16:31] = TCS output patch0 offset for per-patch / 16
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* max = (NUM_PATCHES + 1) * 32*32
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*/
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int param_tcs_out_lds_offsets;
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/* Layout of TCS outputs / TES inputs:
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* [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
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* max = 32*32*4 + 32*4
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* [13:20] = stride between output vertices in DW = num_inputs * 4
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* max = 32*4
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* [26:31] = gl_PatchVerticesIn, max = 32
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*/
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int param_tcs_out_lds_layout;
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int param_tcs_offchip_addr_base64k;
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int param_tcs_factor_addr_base64k;
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int param_tcs_offchip_offset;
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int param_tcs_factor_offset;
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int param_tcs_patch_id;
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int param_tcs_rel_ids;
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/* API TES */
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int param_tes_u;
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int param_tes_v;
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int param_tes_rel_patch_id;
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int param_tes_patch_id;
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/* HW ES */
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int param_es2gs_offset;
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/* API GS */
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int param_gs2vs_offset;
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int param_gs_wave_id; /* GFX6 */
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int param_gs_vtx0_offset; /* in dwords (GFX6) */
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int param_gs_vtx1_offset; /* in dwords (GFX6) */
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int param_gs_prim_id;
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int param_gs_vtx2_offset; /* in dwords (GFX6) */
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int param_gs_vtx3_offset; /* in dwords (GFX6) */
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int param_gs_vtx4_offset; /* in dwords (GFX6) */
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int param_gs_vtx5_offset; /* in dwords (GFX6) */
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int param_gs_instance_id;
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int param_gs_vtx01_offset; /* in dwords (GFX9) */
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int param_gs_vtx23_offset; /* in dwords (GFX9) */
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int param_gs_vtx45_offset; /* in dwords (GFX9) */
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/* CS */
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int param_grid_size;
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int param_block_size;
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int param_block_id[3];
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int param_thread_id;
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LLVMTargetMachineRef tm;
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unsigned range_md_kind;
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unsigned fpmath_md_kind;
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LLVMValueRef fpmath_md_2p5_ulp;
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/* Preloaded descriptors. */
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LLVMValueRef esgs_ring;
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LLVMValueRef gsvs_ring[4];
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LLVMValueRef lds;
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LLVMValueRef gs_next_vertex[4];
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LLVMValueRef postponed_kill;
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LLVMValueRef return_value;
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LLVMTypeRef voidt;
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LLVMTypeRef i1;
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LLVMTypeRef i8;
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LLVMTypeRef i32;
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LLVMTypeRef i64;
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LLVMTypeRef i128;
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LLVMTypeRef f32;
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LLVMTypeRef v2i32;
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LLVMTypeRef v4i32;
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LLVMTypeRef v4f32;
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LLVMTypeRef v8i32;
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LLVMValueRef i32_0;
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LLVMValueRef i32_1;
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LLVMValueRef shared_memory;
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};
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static inline struct si_shader_context *
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si_shader_context(struct lp_build_tgsi_context *bld_base)
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{
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return (struct si_shader_context*)bld_base;
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}
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void si_llvm_add_attribute(LLVMValueRef F, const char *name, int value);
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LLVMTargetRef si_llvm_get_amdgpu_target(const char *triple);
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unsigned si_llvm_compile(LLVMModuleRef M, struct ac_shader_binary *binary,
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LLVMTargetMachineRef tm,
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struct pipe_debug_callback *debug);
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LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
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enum tgsi_opcode_type type);
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LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
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enum tgsi_opcode_type type, LLVMValueRef value);
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LLVMValueRef si_llvm_bound_index(struct si_shader_context *ctx,
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LLVMValueRef index,
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unsigned num);
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void si_llvm_context_init(struct si_shader_context *ctx,
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struct si_screen *sscreen,
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LLVMTargetMachineRef tm);
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void si_llvm_context_set_tgsi(struct si_shader_context *ctx,
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struct si_shader *shader);
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void si_llvm_create_func(struct si_shader_context *ctx,
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const char *name,
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LLVMTypeRef *return_types, unsigned num_return_elems,
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LLVMTypeRef *ParamTypes, unsigned ParamCount);
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void si_llvm_dispose(struct si_shader_context *ctx);
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void si_llvm_optimize_module(struct si_shader_context *ctx);
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LLVMValueRef si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
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enum tgsi_opcode_type type,
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LLVMValueRef ptr,
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LLVMValueRef ptr2);
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LLVMValueRef si_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
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const struct tgsi_full_src_register *reg,
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enum tgsi_opcode_type type,
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unsigned swizzle);
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void si_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
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const struct tgsi_full_instruction *inst,
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const struct tgsi_opcode_info *info,
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LLVMValueRef dst[4]);
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/* Combine these with & instead of |. */
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#define NOOP_WAITCNT 0xf7f
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#define LGKM_CNT 0x07f
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#define VM_CNT 0xf70
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void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16);
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LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
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const struct tgsi_ind_register *ind,
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int rel_index, unsigned num);
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LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements);
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void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
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void si_shader_context_init_mem(struct si_shader_context *ctx);
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#endif
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