Iago Toral Quiroga 6f504b5fc6 v3dv: fix incorrect render area setup ... Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4875 Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11158>		2021-06-07 11:25:22 +00:00
..
ci	v3dv: don't keep an open file descriptor for imported fences/semaphores	2021-06-02 09:58:47 +00:00
cle	intel: Rename gen_10 to ver_10	2021-04-20 20:06:34 +00:00
clif	v3dv: clif format dumping support	2020-10-13 21:21:26 +00:00
common	broadcom/common: move v3d_tiling to common	2021-06-04 13:00:40 +02:00
compiler	v3d: Use the ra_alloc_contig_reg_class() function to speed up RA.	2021-06-04 19:08:57 +00:00
drm-shim	vc4: add drm-shim	2021-01-28 16:14:06 +00:00
qpu	broadcom/qpu: rename from VC5 to V3D	2021-04-29 11:22:12 +02:00
simulator	v3d/simulator: use BFC/RFC registers to wait for bin/render to complete	2021-06-01 12:22:28 +02:00
vulkan	v3dv: fix incorrect render area setup	2021-06-07 11:25:22 +00:00
.editorconfig	…
Android.cle.mk	…
Android.genxml.mk	…
Android.mk	…
Makefile.sources	v3d: Add a lowering pass for line smoothing	2020-07-06 21:59:16 +00:00
meson.build	broadcom/common: move v3d_tiling to common	2021-06-04 13:00:40 +02:00