345 lines
11 KiB
C
345 lines
11 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Tom Stellard <thomas.stellard@amd.com>
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* Michel Dänzer <michel.daenzer@amd.com>
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* Christian König <christian.koenig@amd.com>
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*/
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/* How linking shader inputs and outputs between vertex, tessellation, and
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* geometry shaders works.
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*
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* Inputs and outputs between shaders are stored in a buffer. This buffer
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* lives in LDS (typical case for tessellation), but it can also live
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* in memory (ESGS). Each input or output has a fixed location within a vertex.
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* The highest used input or output determines the stride between vertices.
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*
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* Since GS and tessellation are only possible in the OpenGL core profile,
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* only these semantics are valid for per-vertex data:
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*
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* Name Location
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*
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* POSITION 0
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* PSIZE 1
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* CLIPDIST0..1 2..3
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* CULLDIST0..1 (not implemented)
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* GENERIC0..31 4..35
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*
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* For example, a shader only writing GENERIC0 has the output stride of 5.
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*
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* Only these semantics are valid for per-patch data:
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*
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* Name Location
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*
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* TESSOUTER 0
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* TESSINNER 1
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* PATCH0..29 2..31
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*
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* That's how independent shaders agree on input and output locations.
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* The si_shader_io_get_unique_index function assigns the locations.
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*
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* For tessellation, other required information for calculating the input and
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* output addresses like the vertex stride, the patch stride, and the offsets
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* where per-vertex and per-patch data start, is passed to the shader via
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* user data SGPRs. The offsets and strides are calculated at draw time and
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* aren't available at compile time.
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*/
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#ifndef SI_SHADER_H
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#define SI_SHADER_H
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#include <llvm-c/Core.h> /* LLVMModuleRef */
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#include "tgsi/tgsi_scan.h"
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#include "si_state.h"
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struct radeon_shader_binary;
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struct radeon_shader_reloc;
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#define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
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#define SI_SGPR_CONST_BUFFERS 2
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#define SI_SGPR_SAMPLER_STATES 4
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#define SI_SGPR_SAMPLER_VIEWS 6
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#define SI_SGPR_VERTEX_BUFFERS 8 /* VS only */
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#define SI_SGPR_BASE_VERTEX 10 /* VS only */
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#define SI_SGPR_START_INSTANCE 11 /* VS only */
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#define SI_SGPR_VS_STATE_BITS 12 /* VS(VS) only */
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#define SI_SGPR_LS_OUT_LAYOUT 12 /* VS(LS) only */
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#define SI_SGPR_TCS_OUT_OFFSETS 8 /* TCS & TES only */
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#define SI_SGPR_TCS_OUT_LAYOUT 9 /* TCS & TES only */
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#define SI_SGPR_TCS_IN_LAYOUT 10 /* TCS only */
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#define SI_SGPR_ALPHA_REF 8 /* PS only */
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#define SI_VS_NUM_USER_SGPR 13 /* API VS */
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#define SI_ES_NUM_USER_SGPR 12 /* API VS */
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#define SI_LS_NUM_USER_SGPR 13 /* API VS */
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#define SI_TCS_NUM_USER_SGPR 11
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#define SI_TES_NUM_USER_SGPR 10
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#define SI_GS_NUM_USER_SGPR 8
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#define SI_GSCOPY_NUM_USER_SGPR 4
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#define SI_PS_NUM_USER_SGPR 9
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/* LLVM function parameter indices */
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#define SI_PARAM_RW_BUFFERS 0
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#define SI_PARAM_CONST_BUFFERS 1
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#define SI_PARAM_SAMPLER_STATES 2
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#define SI_PARAM_SAMPLER_VIEWS 3
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/* VS only parameters */
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#define SI_PARAM_VERTEX_BUFFERS 4
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#define SI_PARAM_BASE_VERTEX 5
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#define SI_PARAM_START_INSTANCE 6
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/* [0] = clamp vertex color */
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#define SI_PARAM_VS_STATE_BITS 7
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/* the other VS parameters are assigned dynamically */
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/* Offsets where TCS outputs and TCS patch outputs live in LDS:
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* [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
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* [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
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*/
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#define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
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/* Layout of TCS outputs / TES inputs:
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* [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
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* [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
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* [26:31] = gl_PatchVerticesIn, max = 32
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*/
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#define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
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/* Layout of LS outputs / TCS inputs
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* [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
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* [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
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*/
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#define SI_PARAM_TCS_IN_LAYOUT 6 /* TCS only */
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#define SI_PARAM_LS_OUT_LAYOUT 7 /* same value as TCS_IN_LAYOUT, LS only */
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/* TCS only parameters. */
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#define SI_PARAM_TESS_FACTOR_OFFSET 7
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#define SI_PARAM_PATCH_ID 8
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#define SI_PARAM_REL_IDS 9
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/* GS only parameters */
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#define SI_PARAM_GS2VS_OFFSET 4
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#define SI_PARAM_GS_WAVE_ID 5
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#define SI_PARAM_VTX0_OFFSET 6
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#define SI_PARAM_VTX1_OFFSET 7
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#define SI_PARAM_PRIMITIVE_ID 8
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#define SI_PARAM_VTX2_OFFSET 9
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#define SI_PARAM_VTX3_OFFSET 10
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#define SI_PARAM_VTX4_OFFSET 11
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#define SI_PARAM_VTX5_OFFSET 12
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#define SI_PARAM_GS_INSTANCE_ID 13
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/* PS only parameters */
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#define SI_PARAM_ALPHA_REF 4
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#define SI_PARAM_PRIM_MASK 5
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#define SI_PARAM_PERSP_SAMPLE 6
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#define SI_PARAM_PERSP_CENTER 7
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#define SI_PARAM_PERSP_CENTROID 8
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#define SI_PARAM_PERSP_PULL_MODEL 9
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#define SI_PARAM_LINEAR_SAMPLE 10
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#define SI_PARAM_LINEAR_CENTER 11
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#define SI_PARAM_LINEAR_CENTROID 12
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#define SI_PARAM_LINE_STIPPLE_TEX 13
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#define SI_PARAM_POS_X_FLOAT 14
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#define SI_PARAM_POS_Y_FLOAT 15
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#define SI_PARAM_POS_Z_FLOAT 16
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#define SI_PARAM_POS_W_FLOAT 17
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#define SI_PARAM_FRONT_FACE 18
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#define SI_PARAM_ANCILLARY 19
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#define SI_PARAM_SAMPLE_COVERAGE 20
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#define SI_PARAM_POS_FIXED_PT 21
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#define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
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struct si_shader;
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/* A shader selector is a gallium CSO and contains shader variants and
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* binaries for one TGSI program. This can be shared by multiple contexts.
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*/
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struct si_shader_selector {
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pipe_mutex mutex;
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struct si_shader *first_variant; /* immutable after the first variant */
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struct si_shader *last_variant; /* mutable */
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struct tgsi_token *tokens;
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struct pipe_stream_output_info so;
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struct tgsi_shader_info info;
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/* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
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unsigned type;
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/* GS parameters. */
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unsigned esgs_itemsize;
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unsigned gs_input_verts_per_prim;
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unsigned gs_output_prim;
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unsigned gs_max_out_vertices;
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unsigned gs_num_invocations;
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unsigned max_gs_stream; /* count - 1 */
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unsigned gsvs_vertex_size;
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unsigned max_gsvs_emit_size;
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/* PS parameters. */
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unsigned db_shader_control;
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/* Set 0xf or 0x0 (4 bits) per each written output.
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* ANDed with spi_shader_col_format.
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*/
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unsigned colors_written_4bit;
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/* masks of "get_unique_index" bits */
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uint64_t outputs_written;
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uint32_t patch_outputs_written;
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};
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/* Valid shader configurations:
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*
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* API shaders VS | TCS | TES | GS |pass| PS
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* are compiled as: | | | |thru|
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* | | | | |
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* Only VS & PS: VS | -- | -- | -- | -- | PS
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* With GS: ES | -- | -- | GS | VS | PS
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* With Tessel.: LS | HS | VS | -- | -- | PS
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* With both: LS | HS | ES | GS | VS | PS
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*/
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union si_shader_key {
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struct {
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unsigned spi_shader_col_format;
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unsigned color_is_int8:8;
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unsigned last_cbuf:3;
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unsigned color_two_side:1;
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unsigned alpha_func:3;
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unsigned alpha_to_one:1;
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unsigned poly_stipple:1;
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unsigned poly_line_smoothing:1;
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unsigned clamp_color:1;
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unsigned force_persample_interp:1;
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} ps;
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struct {
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unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS];
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/* Mask of "get_unique_index" bits - which outputs are read
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* by the next stage (needed by ES).
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* This describes how outputs are laid out in memory. */
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unsigned as_es:1; /* export shader */
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unsigned as_ls:1; /* local shader */
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unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
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} vs;
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struct {
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unsigned prim_mode:3;
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} tcs; /* tessellation control shader */
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struct {
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/* Mask of "get_unique_index" bits - which outputs are read
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* by the next stage (needed by ES).
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* This describes how outputs are laid out in memory. */
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unsigned as_es:1; /* export shader */
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unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
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} tes; /* tessellation evaluation shader */
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};
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struct si_shader_config {
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unsigned num_sgprs;
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unsigned num_vgprs;
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unsigned lds_size;
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unsigned spi_ps_input_ena;
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unsigned float_mode;
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unsigned scratch_bytes_per_wave;
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unsigned rsrc1;
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unsigned rsrc2;
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};
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struct si_shader {
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struct si_shader_selector *selector;
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struct si_shader *next_variant;
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struct si_shader *gs_copy_shader;
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struct si_pm4_state *pm4;
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struct r600_resource *bo;
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struct r600_resource *scratch_bo;
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union si_shader_key key;
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struct radeon_shader_binary binary;
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struct si_shader_config config;
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unsigned vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
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bool uses_instanceid;
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unsigned nr_pos_exports;
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unsigned nr_param_exports;
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bool dx10_clamp_mode; /* convert NaNs to 0 */
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};
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static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
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{
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if (sctx->gs_shader.cso)
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return &sctx->gs_shader.cso->info;
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else if (sctx->tes_shader.cso)
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return &sctx->tes_shader.cso->info;
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else if (sctx->vs_shader.cso)
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return &sctx->vs_shader.cso->info;
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else
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return NULL;
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}
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static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
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{
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if (sctx->gs_shader.current)
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return sctx->gs_shader.current->gs_copy_shader;
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else if (sctx->tes_shader.current)
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return sctx->tes_shader.current;
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else
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return sctx->vs_shader.current;
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}
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static inline bool si_vs_exports_prim_id(struct si_shader *shader)
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{
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if (shader->selector->type == PIPE_SHADER_VERTEX)
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return shader->key.vs.export_prim_id;
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else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
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return shader->key.tes.export_prim_id;
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else
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return false;
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}
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/* radeonsi_shader.c */
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int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
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struct si_shader *shader,
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struct pipe_debug_callback *debug);
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void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
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int si_compile_llvm(struct si_screen *sscreen,
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struct radeon_shader_binary *binary,
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struct si_shader_config *conf,
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LLVMTargetMachineRef tm,
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LLVMModuleRef mod,
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struct pipe_debug_callback *debug,
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unsigned processor);
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void si_shader_destroy(struct si_shader *shader);
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unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
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int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
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void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
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struct pipe_debug_callback *debug, unsigned processor);
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void si_shader_apply_scratch_relocs(struct si_context *sctx,
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struct si_shader *shader,
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uint64_t scratch_va);
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void si_shader_binary_read_config(struct radeon_shader_binary *binary,
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struct si_shader_config *conf,
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unsigned symbol_offset);
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#endif
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