450 lines
17 KiB
C
450 lines
17 KiB
C
/*
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* Copyright © 2020 Advanced Micro Devices, Inc.
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* Copyright © 2022 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/* enhanced version of nir_inline_uniforms that can inline from any uniform buffer
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* see nir_inline_uniforms.c for more details
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*/
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#include "nir_builder.h"
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#include "nir_loop_analyze.h"
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#include "lvp_private.h"
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static bool
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src_only_uses_uniforms(const nir_src *src, int component,
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uint32_t *uni_offsets, uint8_t *num_offsets)
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{
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if (!src->is_ssa)
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return false;
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assert(component < src->ssa->num_components);
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nir_instr *instr = src->ssa->parent_instr;
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switch (instr->type) {
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case nir_instr_type_alu: {
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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/* Vector ops only need to check the corresponding component. */
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if (nir_op_is_vec(alu->op)) {
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nir_alu_src *alu_src = alu->src + component;
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return src_only_uses_uniforms(&alu_src->src, alu_src->swizzle[0],
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uni_offsets, num_offsets);
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}
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/* Return true if all sources return true. */
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for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
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nir_alu_src *alu_src = alu->src + i;
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int input_sizes = nir_op_infos[alu->op].input_sizes[i];
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if (input_sizes == 0) {
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/* For ops which has no input size, each component of dest is
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* only determined by the same component of srcs.
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*/
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if (!src_only_uses_uniforms(&alu_src->src, alu_src->swizzle[component],
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uni_offsets, num_offsets))
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return false;
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} else {
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/* For ops which has input size, all components of dest are
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* determined by all components of srcs (except vec ops).
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*/
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for (unsigned j = 0; j < input_sizes; j++) {
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if (!src_only_uses_uniforms(&alu_src->src, alu_src->swizzle[j],
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uni_offsets, num_offsets))
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return false;
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}
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}
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}
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return true;
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}
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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/* Return true if the intrinsic loads with a constant offset. */
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if (intr->intrinsic == nir_intrinsic_load_ubo &&
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nir_src_is_const(intr->src[0]) &&
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nir_src_is_const(intr->src[1]) &&
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/* TODO: Can't handle other bit sizes for now. */
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intr->dest.ssa.bit_size == 32) {
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uint32_t offset = nir_src_as_uint(intr->src[1]) + component * 4;
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/* Already recorded by other one */
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uint32_t ubo = nir_src_as_uint(intr->src[0]);
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for (int i = 0; uni_offsets && i < num_offsets[ubo]; i++) {
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if (uni_offsets[ubo * PIPE_MAX_CONSTANT_BUFFERS + i] == offset)
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return true;
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}
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/* Exceed uniform number limit */
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if (num_offsets && num_offsets[ubo] == MAX_INLINABLE_UNIFORMS)
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return false;
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/* Record the uniform offset. */
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if (uni_offsets)
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uni_offsets[ubo * MAX_INLINABLE_UNIFORMS + num_offsets[ubo]++] = offset;
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return true;
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}
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return false;
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}
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case nir_instr_type_load_const:
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/* Always return true for constants. */
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return true;
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default:
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return false;
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}
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}
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static bool
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is_induction_variable(const nir_src *src, int component, nir_loop_info *info,
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uint32_t *uni_offsets, uint8_t *num_offsets)
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{
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if (!src->is_ssa)
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return false;
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assert(component < src->ssa->num_components);
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/* Return true for induction variable (ie. i in for loop) */
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for (int i = 0; i < info->num_induction_vars; i++) {
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nir_loop_induction_variable *var = info->induction_vars + i;
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if (var->def == src->ssa) {
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/* Induction variable should have constant initial value (ie. i = 0),
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* constant update value (ie. i++) and constant end condition
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* (ie. i < 10), so that we know the exact loop count for unrolling
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* the loop.
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*
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* Add uniforms need to be inlined for this induction variable's
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* initial and update value to be constant, for example:
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*
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* for (i = init; i < count; i += step)
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*
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* We collect uniform "init" and "step" here.
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*/
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if (var->init_src) {
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if (!src_only_uses_uniforms(var->init_src, component,
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uni_offsets, num_offsets))
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return false;
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}
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if (var->update_src) {
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nir_alu_src *alu_src = var->update_src;
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if (!src_only_uses_uniforms(&alu_src->src,
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alu_src->swizzle[component],
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uni_offsets, num_offsets))
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return false;
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}
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return true;
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}
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}
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return false;
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}
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static void
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add_inlinable_uniforms(const nir_src *cond, nir_loop_info *info,
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uint32_t *uni_offsets, uint8_t *num_offsets)
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{
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uint8_t new_num[PIPE_MAX_CONSTANT_BUFFERS];
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memcpy(new_num, num_offsets, sizeof(new_num));
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/* If condition SSA is always scalar, so component is 0. */
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unsigned component = 0;
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/* Allow induction variable which means a loop terminator. */
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if (info) {
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nir_ssa_scalar cond_scalar = {cond->ssa, 0};
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/* Limit terminator condition to loop unroll support case which is a simple
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* comparison (ie. "i < count" is supported, but "i + 1 < count" is not).
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*/
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if (nir_is_supported_terminator_condition(cond_scalar)) {
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nir_alu_instr *alu = nir_instr_as_alu(cond->ssa->parent_instr);
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/* One side of comparison is induction variable, the other side is
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* only uniform.
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*/
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for (int i = 0; i < 2; i++) {
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if (is_induction_variable(&alu->src[i].src, alu->src[i].swizzle[0],
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info, uni_offsets, new_num)) {
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cond = &alu->src[1 - i].src;
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component = alu->src[1 - i].swizzle[0];
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break;
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}
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}
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}
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}
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/* Only update uniform number when all uniforms in the expression
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* can be inlined. Partially inlines uniforms can't lower if/loop.
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*
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* For example, uniform can be inlined for a shader is limited to 4,
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* and we have already added 3 uniforms, then want to deal with
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*
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* if (uniform0 + uniform1 == 10)
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*
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* only uniform0 can be inlined due to we exceed the 4 limit. But
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* unless both uniform0 and uniform1 are inlined, can we eliminate
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* the if statement.
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*
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* This is even possible when we deal with loop if the induction
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* variable init and update also contains uniform like
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*
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* for (i = uniform0; i < uniform1; i+= uniform2)
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*
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* unless uniform0, uniform1 and uniform2 can be inlined at once,
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* can the loop be unrolled.
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*/
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if (src_only_uses_uniforms(cond, component, uni_offsets, new_num))
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memcpy(num_offsets, new_num, sizeof(new_num));
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}
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static bool
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is_src_uniform_load(nir_src src)
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{
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if (nir_src_bit_size(src) != 32 || nir_src_num_components(src) != 1 || nir_src_is_const(src))
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return false;
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return src_only_uses_uniforms(&src, 0, NULL, NULL);
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}
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static void
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process_node(nir_cf_node *node, nir_loop_info *info,
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uint32_t *uni_offsets, uint8_t *num_offsets,
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struct set *stores)
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{
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switch (node->type) {
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case nir_cf_node_if: {
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nir_if *if_node = nir_cf_node_as_if(node);
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const nir_src *cond = &if_node->condition;
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add_inlinable_uniforms(cond, info, uni_offsets, num_offsets);
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/* Do not pass loop info down so only alow induction variable
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* in loop terminator "if":
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*
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* for (i = 0; true; i++)
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* if (i == count)
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* if (i == num)
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* <no break>
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* break
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*
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* so "num" won't be inlined due to the "if" is not a
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* terminator.
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*/
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info = NULL;
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foreach_list_typed(nir_cf_node, nested_node, node, &if_node->then_list)
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process_node(nested_node, info, uni_offsets, num_offsets, stores);
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foreach_list_typed(nir_cf_node, nested_node, node, &if_node->else_list)
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process_node(nested_node, info, uni_offsets, num_offsets, stores);
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break;
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}
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case nir_cf_node_loop: {
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nir_loop *loop = nir_cf_node_as_loop(node);
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/* Replace loop info, no nested loop info currently:
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*
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* for (i = 0; i < count0; i++)
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* for (j = 0; j < count1; j++)
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* if (i == num)
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*
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* so "num" won't be inlined due to "i" is an induction
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* variable of upper loop.
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*/
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info = loop->info;
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foreach_list_typed(nir_cf_node, nested_node, node, &loop->body) {
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bool is_terminator = false;
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list_for_each_entry(nir_loop_terminator, terminator,
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&info->loop_terminator_list,
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loop_terminator_link) {
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if (nested_node == &terminator->nif->cf_node) {
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is_terminator = true;
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break;
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}
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}
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/* Allow induction variables for terminator "if" only:
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*
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* for (i = 0; i < count; i++)
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* if (i == num)
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* <no break>
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*
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* so "num" won't be inlined due to the "if" is not a
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* terminator.
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*/
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nir_loop_info *use_info = is_terminator ? info : NULL;
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process_node(nested_node, use_info, uni_offsets, num_offsets, stores);
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}
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break;
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}
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case nir_cf_node_block: {
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nir_block *block = nir_cf_node_as_block(node);
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nir_foreach_instr(instr, block) {
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if (instr->type == nir_instr_type_intrinsic) {
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic == nir_intrinsic_store_deref && is_src_uniform_load(intr->src[1]))
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_mesa_set_add(stores, &intr->src[1]);
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}
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}
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break;
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}
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default:
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break;
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}
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}
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bool
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lvp_find_inlinable_uniforms(struct lvp_pipeline *pipeline, nir_shader *shader)
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{
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bool ret = false;
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struct set *stores = _mesa_set_create(shader, _mesa_hash_pointer, _mesa_key_pointer_equal);
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nir_foreach_function(function, shader) {
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if (function->impl) {
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nir_metadata_require(function->impl, nir_metadata_loop_analysis, nir_var_all);
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foreach_list_typed(nir_cf_node, node, node, &function->impl->body)
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process_node(node, NULL, (uint32_t*)pipeline->inlines[shader->info.stage].uniform_offsets, pipeline->inlines[shader->info.stage].count, stores);
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}
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}
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const unsigned threshold = 5;
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set_foreach(stores, entry) {
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const nir_src *src = entry->key;
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unsigned counter = 0;
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list_for_each_entry(nir_src, rsrc, &src->ssa->uses, use_link) {
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counter++;
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if (counter >= threshold)
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break;
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}
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if (counter >= threshold) {
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uint8_t new_num[PIPE_MAX_CONSTANT_BUFFERS];
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memcpy(new_num, pipeline->inlines[shader->info.stage].count, sizeof(new_num));
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if (src_only_uses_uniforms(src, 0, (uint32_t*)pipeline->inlines[shader->info.stage].uniform_offsets, new_num)) {
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ret = true;
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memcpy(pipeline->inlines[shader->info.stage].count, new_num, sizeof(new_num));
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}
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}
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}
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for (unsigned i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
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if (pipeline->inlines[shader->info.stage].count[i]) {
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pipeline->inlines[shader->info.stage].can_inline |= BITFIELD_BIT(i);
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break;
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}
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}
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return ret;
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}
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void
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lvp_inline_uniforms(nir_shader *shader, const struct lvp_pipeline *pipeline, const uint32_t *uniform_values, uint32_t ubo)
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{
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if (!pipeline->inlines[shader->info.stage].can_inline)
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return;
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nir_foreach_function(function, shader) {
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if (function->impl) {
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nir_builder b;
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nir_builder_init(&b, function->impl);
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nir_foreach_block(block, function->impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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/* Only replace loads with constant offsets. */
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if (intr->intrinsic == nir_intrinsic_load_ubo &&
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nir_src_is_const(intr->src[0]) &&
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nir_src_as_uint(intr->src[0]) == ubo &&
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nir_src_is_const(intr->src[1]) &&
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/* TODO: Can't handle other bit sizes for now. */
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intr->dest.ssa.bit_size == 32) {
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int num_components = intr->dest.ssa.num_components;
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uint32_t offset = nir_src_as_uint(intr->src[1]);
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const unsigned num_uniforms = pipeline->inlines[shader->info.stage].count[ubo];
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const unsigned *uniform_dw_offsets = pipeline->inlines[shader->info.stage].uniform_offsets[ubo];
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if (num_components == 1) {
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/* Just replace the uniform load to constant load. */
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for (unsigned i = 0; i < num_uniforms; i++) {
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if (offset == uniform_dw_offsets[i]) {
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b.cursor = nir_before_instr(&intr->instr);
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nir_ssa_def *def = nir_imm_int(&b, uniform_values[i]);
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nir_ssa_def_rewrite_uses(&intr->dest.ssa, def);
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nir_instr_remove(&intr->instr);
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break;
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}
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}
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} else {
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/* Lower vector uniform load to scalar and replace each
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* found component load with constant load.
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*/
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uint32_t max_offset = offset + num_components;
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nir_ssa_def *components[NIR_MAX_VEC_COMPONENTS] = {0};
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bool found = false;
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b.cursor = nir_before_instr(&intr->instr);
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/* Find component to replace. */
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for (unsigned i = 0; i < num_uniforms; i++) {
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uint32_t uni_offset = uniform_dw_offsets[i];
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if (uni_offset >= offset && uni_offset < max_offset) {
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int index = uni_offset - offset;
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components[index] = nir_imm_int(&b, uniform_values[i]);
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found = true;
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}
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}
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if (!found)
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continue;
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/* Create per-component uniform load. */
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for (unsigned i = 0; i < num_components; i++) {
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if (!components[i]) {
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uint32_t scalar_offset = (offset + i) * 4;
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components[i] = nir_load_ubo(&b, 1, intr->dest.ssa.bit_size,
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intr->src[0].ssa,
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nir_imm_int(&b, scalar_offset));
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nir_intrinsic_instr *load =
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nir_instr_as_intrinsic(components[i]->parent_instr);
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nir_intrinsic_set_align(load, NIR_ALIGN_MUL_MAX, scalar_offset);
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nir_intrinsic_set_range_base(load, scalar_offset);
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nir_intrinsic_set_range(load, 4);
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}
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}
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/* Replace the original uniform load. */
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nir_ssa_def_rewrite_uses(&intr->dest.ssa,
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nir_vec(&b, components, num_components));
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nir_instr_remove(&intr->instr);
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}
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}
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}
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}
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nir_metadata_preserve(function->impl, nir_metadata_block_index |
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nir_metadata_dominance);
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}
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}
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}
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