1205 lines
36 KiB
C
1205 lines
36 KiB
C
/*
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* Copyright (C) 2008 Nicolai Haehnle.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/**
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* @file
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*
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* Shareable transformations that transform "special" ALU instructions
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* into ALU instructions that are supported by hardware.
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*
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*/
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#include "radeon_program_alu.h"
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#include "radeon_compiler.h"
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#include "radeon_compiler_util.h"
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static struct rc_instruction *emit1(
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struct radeon_compiler * c, struct rc_instruction * after,
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rc_opcode Opcode, struct rc_sub_instruction * base,
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struct rc_dst_register DstReg, struct rc_src_register SrcReg)
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{
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struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
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if (base) {
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memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
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}
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fpi->U.I.Opcode = Opcode;
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fpi->U.I.DstReg = DstReg;
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fpi->U.I.SrcReg[0] = SrcReg;
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return fpi;
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}
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static struct rc_instruction *emit2(
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struct radeon_compiler * c, struct rc_instruction * after,
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rc_opcode Opcode, struct rc_sub_instruction * base,
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struct rc_dst_register DstReg,
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struct rc_src_register SrcReg0, struct rc_src_register SrcReg1)
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{
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struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
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if (base) {
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memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
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}
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fpi->U.I.Opcode = Opcode;
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fpi->U.I.DstReg = DstReg;
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fpi->U.I.SrcReg[0] = SrcReg0;
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fpi->U.I.SrcReg[1] = SrcReg1;
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return fpi;
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}
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static struct rc_instruction *emit3(
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struct radeon_compiler * c, struct rc_instruction * after,
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rc_opcode Opcode, struct rc_sub_instruction * base,
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struct rc_dst_register DstReg,
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struct rc_src_register SrcReg0, struct rc_src_register SrcReg1,
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struct rc_src_register SrcReg2)
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{
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struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
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if (base) {
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memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
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}
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fpi->U.I.Opcode = Opcode;
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fpi->U.I.DstReg = DstReg;
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fpi->U.I.SrcReg[0] = SrcReg0;
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fpi->U.I.SrcReg[1] = SrcReg1;
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fpi->U.I.SrcReg[2] = SrcReg2;
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return fpi;
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}
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static struct rc_dst_register dstregtmpmask(int index, int mask)
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{
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struct rc_dst_register dst = {0, 0, 0};
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dst.File = RC_FILE_TEMPORARY;
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dst.Index = index;
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dst.WriteMask = mask;
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return dst;
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}
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static const struct rc_src_register builtin_zero = {
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.File = RC_FILE_NONE,
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.Index = 0,
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.Swizzle = RC_SWIZZLE_0000
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};
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static const struct rc_src_register builtin_one = {
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.File = RC_FILE_NONE,
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.Index = 0,
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.Swizzle = RC_SWIZZLE_1111
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};
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static const struct rc_src_register builtin_half = {
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.File = RC_FILE_NONE,
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.Index = 0,
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.Swizzle = RC_SWIZZLE_HHHH
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};
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static const struct rc_src_register srcreg_undefined = {
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.File = RC_FILE_NONE,
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.Index = 0,
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.Swizzle = RC_SWIZZLE_XYZW
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};
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static struct rc_src_register srcreg(int file, int index)
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{
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struct rc_src_register src = srcreg_undefined;
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src.File = file;
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src.Index = index;
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return src;
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}
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static struct rc_src_register srcregswz(int file, int index, int swz)
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{
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struct rc_src_register src = srcreg_undefined;
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src.File = file;
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src.Index = index;
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src.Swizzle = swz;
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return src;
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}
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static struct rc_src_register absolute(struct rc_src_register reg)
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{
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struct rc_src_register newreg = reg;
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newreg.Abs = 1;
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newreg.Negate = RC_MASK_NONE;
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return newreg;
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}
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static struct rc_src_register negate(struct rc_src_register reg)
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{
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struct rc_src_register newreg = reg;
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newreg.Negate = newreg.Negate ^ RC_MASK_XYZW;
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return newreg;
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}
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static struct rc_src_register swizzle(struct rc_src_register reg,
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rc_swizzle x, rc_swizzle y, rc_swizzle z, rc_swizzle w)
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{
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struct rc_src_register swizzled = reg;
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swizzled.Swizzle = combine_swizzles4(reg.Swizzle, x, y, z, w);
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return swizzled;
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}
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static struct rc_src_register swizzle_smear(struct rc_src_register reg,
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rc_swizzle x)
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{
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return swizzle(reg, x, x, x, x);
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}
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static struct rc_src_register swizzle_xxxx(struct rc_src_register reg)
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{
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return swizzle_smear(reg, RC_SWIZZLE_X);
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}
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static struct rc_src_register swizzle_yyyy(struct rc_src_register reg)
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{
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return swizzle_smear(reg, RC_SWIZZLE_Y);
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}
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static struct rc_src_register swizzle_zzzz(struct rc_src_register reg)
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{
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return swizzle_smear(reg, RC_SWIZZLE_Z);
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}
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static struct rc_src_register swizzle_wwww(struct rc_src_register reg)
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{
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return swizzle_smear(reg, RC_SWIZZLE_W);
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}
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static int is_dst_safe_to_reuse(struct rc_instruction *inst)
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{
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const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode);
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unsigned i;
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assert(info->HasDstReg);
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if (inst->U.I.DstReg.File != RC_FILE_TEMPORARY)
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return 0;
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for (i = 0; i < info->NumSrcRegs; i++) {
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if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY &&
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inst->U.I.SrcReg[i].Index == inst->U.I.DstReg.Index)
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return 0;
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}
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return 1;
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}
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static struct rc_dst_register try_to_reuse_dst(struct radeon_compiler *c,
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struct rc_instruction *inst)
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{
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unsigned tmp;
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if (is_dst_safe_to_reuse(inst))
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tmp = inst->U.I.DstReg.Index;
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else
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tmp = rc_find_free_temporary(c);
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return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask);
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}
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static void transform_CEIL(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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/* Assuming:
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* ceil(x) = -floor(-x)
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*
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* After inlining floor:
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* ceil(x) = -(-x-frac(-x))
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*
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* After simplification:
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* ceil(x) = x+frac(-x)
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*/
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struct rc_dst_register dst = try_to_reuse_dst(c, inst);
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emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dst, negate(inst->U.I.SrcReg[0]));
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emit2(c, inst->Prev, RC_OPCODE_ADD, &inst->U.I, inst->U.I.DstReg,
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inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index));
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rc_remove_instruction(inst);
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}
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static void transform_DP2(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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struct rc_src_register src0 = inst->U.I.SrcReg[0];
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struct rc_src_register src1 = inst->U.I.SrcReg[1];
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src0.Negate &= ~(RC_MASK_Z | RC_MASK_W);
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src0.Swizzle &= ~(63 << (3 * 2));
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src0.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
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src1.Negate &= ~(RC_MASK_Z | RC_MASK_W);
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src1.Swizzle &= ~(63 << (3 * 2));
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src1.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
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emit2(c, inst->Prev, RC_OPCODE_DP3, &inst->U.I, inst->U.I.DstReg, src0, src1);
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rc_remove_instruction(inst);
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}
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/**
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* [1, src0.y*src1.y, src0.z, src1.w]
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* So basically MUL with lotsa swizzling.
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*/
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static void transform_DST(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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emit2(c, inst->Prev, RC_OPCODE_MUL, &inst->U.I, inst->U.I.DstReg,
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swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE),
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swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_ONE, RC_SWIZZLE_W));
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rc_remove_instruction(inst);
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}
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static void transform_FLR(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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struct rc_dst_register dst = try_to_reuse_dst(c, inst);
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emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dst, inst->U.I.SrcReg[0]);
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emit2(c, inst->Prev, RC_OPCODE_ADD, &inst->U.I, inst->U.I.DstReg,
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inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
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rc_remove_instruction(inst);
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}
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static void transform_TRUNC(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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/* Definition of trunc:
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* trunc(x) = (abs(x) - fract(abs(x))) * sgn(x)
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*
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* The multiplication by sgn(x) can be simplified using CMP:
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* y * sgn(x) = (x < 0 ? -y : y)
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*/
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struct rc_dst_register dst = try_to_reuse_dst(c, inst);
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emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dst, absolute(inst->U.I.SrcReg[0]));
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emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, absolute(inst->U.I.SrcReg[0]),
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negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
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emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg, inst->U.I.SrcReg[0],
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negate(srcreg(RC_FILE_TEMPORARY, dst.Index)), srcreg(RC_FILE_TEMPORARY, dst.Index));
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rc_remove_instruction(inst);
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}
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/**
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* Definition of LIT (from ARB_fragment_program):
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*
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* tmp = VectorLoad(op0);
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* if (tmp.x < 0) tmp.x = 0;
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* if (tmp.y < 0) tmp.y = 0;
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* if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon);
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* else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon;
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* result.x = 1.0;
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* result.y = tmp.x;
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* result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0;
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* result.w = 1.0;
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*
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* The longest path of computation is the one leading to result.z,
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* consisting of 5 operations. This implementation of LIT takes
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* 5 slots, if the subsequent optimization passes are clever enough
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* to pair instructions correctly.
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*/
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static void transform_LIT(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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unsigned int constant;
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unsigned int constant_swizzle;
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unsigned int temp;
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struct rc_src_register srctemp;
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constant = rc_constants_add_immediate_scalar(&c->Program.Constants, -127.999999, &constant_swizzle);
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if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
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struct rc_instruction * inst_mov;
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inst_mov = emit1(c, inst,
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RC_OPCODE_MOV, NULL, inst->U.I.DstReg,
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srcreg(RC_FILE_TEMPORARY, rc_find_free_temporary(c)));
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inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst->U.I.DstReg.Index = inst_mov->U.I.SrcReg[0].Index;
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inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
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}
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temp = inst->U.I.DstReg.Index;
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srctemp = srcreg(RC_FILE_TEMPORARY, temp);
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/* tmp.x = max(0.0, Src.x); */
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/* tmp.y = max(0.0, Src.y); */
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/* tmp.w = clamp(Src.z, -128+eps, 128-eps); */
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emit2(c, inst->Prev, RC_OPCODE_MAX, NULL,
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dstregtmpmask(temp, RC_MASK_XYW),
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inst->U.I.SrcReg[0],
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swizzle(srcreg(RC_FILE_CONSTANT, constant),
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RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, constant_swizzle&3));
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emit2(c, inst->Prev, RC_OPCODE_MIN, NULL,
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dstregtmpmask(temp, RC_MASK_Z),
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swizzle_wwww(srctemp),
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negate(srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle)));
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/* tmp.w = Pow(tmp.y, tmp.w) */
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emit1(c, inst->Prev, RC_OPCODE_LG2, NULL,
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dstregtmpmask(temp, RC_MASK_W),
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swizzle_yyyy(srctemp));
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emit2(c, inst->Prev, RC_OPCODE_MUL, NULL,
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dstregtmpmask(temp, RC_MASK_W),
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swizzle_wwww(srctemp),
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swizzle_zzzz(srctemp));
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emit1(c, inst->Prev, RC_OPCODE_EX2, NULL,
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dstregtmpmask(temp, RC_MASK_W),
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swizzle_wwww(srctemp));
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/* tmp.z = (tmp.x > 0) ? tmp.w : 0.0 */
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emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I,
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dstregtmpmask(temp, RC_MASK_Z),
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negate(swizzle_xxxx(srctemp)),
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swizzle_wwww(srctemp),
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builtin_zero);
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/* tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 */
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emit1(c, inst->Prev, RC_OPCODE_MOV, &inst->U.I,
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dstregtmpmask(temp, RC_MASK_XYW),
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swizzle(srctemp, RC_SWIZZLE_ONE, RC_SWIZZLE_X, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE));
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rc_remove_instruction(inst);
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}
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static void transform_LRP(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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struct rc_dst_register dst = try_to_reuse_dst(c, inst);
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emit3(c, inst->Prev, RC_OPCODE_ADD, NULL,
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dst,
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negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[2], inst->U.I.SrcReg[2]);
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emit3(c, inst->Prev, RC_OPCODE_MAD, &inst->U.I,
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inst->U.I.DstReg,
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inst->U.I.SrcReg[0], inst->U.I.SrcReg[1], srcreg(RC_FILE_TEMPORARY, dst.Index));
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rc_remove_instruction(inst);
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}
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static void transform_POW(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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struct rc_dst_register tempdst = try_to_reuse_dst(c, inst);
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struct rc_src_register tempsrc = srcreg(RC_FILE_TEMPORARY, tempdst.Index);
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tempdst.WriteMask = RC_MASK_W;
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tempsrc.Swizzle = RC_SWIZZLE_WWWW;
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emit1(c, inst->Prev, RC_OPCODE_LG2, NULL, tempdst, swizzle_xxxx(inst->U.I.SrcReg[0]));
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emit2(c, inst->Prev, RC_OPCODE_MUL, NULL, tempdst, tempsrc, swizzle_xxxx(inst->U.I.SrcReg[1]));
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emit1(c, inst->Prev, RC_OPCODE_EX2, &inst->U.I, inst->U.I.DstReg, tempsrc);
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rc_remove_instruction(inst);
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}
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/* dst = ROUND(src) :
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* add = src + .5
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* frac = FRC(add)
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* dst = add - frac
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*
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* According to the GLSL spec, the implementor can decide which way to round
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* when the fraction is .5. We round down for .5.
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*
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*/
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static void transform_ROUND(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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unsigned int mask = inst->U.I.DstReg.WriteMask;
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unsigned int frac_index, add_index;
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struct rc_dst_register frac_dst, add_dst;
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struct rc_src_register frac_src, add_src;
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/* add = src + .5 */
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add_index = rc_find_free_temporary(c);
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add_dst = dstregtmpmask(add_index, mask);
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emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, add_dst, inst->U.I.SrcReg[0],
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builtin_half);
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add_src = srcreg(RC_FILE_TEMPORARY, add_dst.Index);
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|
|
/* frac = FRC(add) */
|
|
frac_index = rc_find_free_temporary(c);
|
|
frac_dst = dstregtmpmask(frac_index, mask);
|
|
emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, frac_dst, add_src);
|
|
frac_src = srcreg(RC_FILE_TEMPORARY, frac_dst.Index);
|
|
|
|
/* dst = add - frac */
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, inst->U.I.DstReg,
|
|
add_src, negate(frac_src));
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_RSQ(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
inst->U.I.SrcReg[0] = absolute(inst->U.I.SrcReg[0]);
|
|
}
|
|
|
|
static void transform_SEQ(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
|
|
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
|
|
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
|
|
negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_zero, builtin_one);
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_SGE(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
|
|
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
|
|
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_SGT(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
|
|
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
|
|
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_SLE(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
|
|
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
|
|
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_SLT(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
|
|
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
|
|
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_SNE(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
|
|
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
|
|
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
|
|
negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_one, builtin_zero);
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_SSG(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
/* result = sign(x)
|
|
*
|
|
* CMP tmp0, -x, 1, 0
|
|
* CMP tmp1, x, 1, 0
|
|
* ADD result, tmp0, -tmp1;
|
|
*/
|
|
struct rc_dst_register dst0;
|
|
unsigned tmp1;
|
|
|
|
/* 0 < x */
|
|
dst0 = try_to_reuse_dst(c, inst);
|
|
emit3(c, inst->Prev, RC_OPCODE_CMP, NULL,
|
|
dst0,
|
|
negate(inst->U.I.SrcReg[0]),
|
|
builtin_one,
|
|
builtin_zero);
|
|
|
|
/* x < 0 */
|
|
tmp1 = rc_find_free_temporary(c);
|
|
emit3(c, inst->Prev, RC_OPCODE_CMP, NULL,
|
|
dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask),
|
|
inst->U.I.SrcReg[0],
|
|
builtin_one,
|
|
builtin_zero);
|
|
|
|
/* Either both are zero, or one of them is one and the other is zero. */
|
|
/* result = tmp0 - tmp1 */
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL,
|
|
inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, dst0.Index),
|
|
negate(srcreg(RC_FILE_TEMPORARY, tmp1)));
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_SUB(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
inst->U.I.Opcode = RC_OPCODE_ADD;
|
|
inst->U.I.SrcReg[1] = negate(inst->U.I.SrcReg[1]);
|
|
}
|
|
|
|
/**
|
|
* Can be used as a transformation for @ref radeonClauseLocalTransform,
|
|
* no userData necessary.
|
|
*
|
|
* Eliminates the following ALU instructions:
|
|
* CEIL, DST, FLR, LIT, LRP, POW, SEQ, SGE, SGT, SLE, SLT, SNE, SUB
|
|
* using:
|
|
* MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP
|
|
*
|
|
* Transforms RSQ to Radeon's native RSQ by explicitly setting
|
|
* absolute value.
|
|
*
|
|
* @note should be applicable to R300 and R500 fragment programs.
|
|
*/
|
|
int radeonTransformALU(
|
|
struct radeon_compiler * c,
|
|
struct rc_instruction* inst,
|
|
void* unused)
|
|
{
|
|
switch(inst->U.I.Opcode) {
|
|
case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
|
|
case RC_OPCODE_DP2: transform_DP2(c, inst); return 1;
|
|
case RC_OPCODE_DST: transform_DST(c, inst); return 1;
|
|
case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
|
|
case RC_OPCODE_LIT: transform_LIT(c, inst); return 1;
|
|
case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;
|
|
case RC_OPCODE_POW: transform_POW(c, inst); return 1;
|
|
case RC_OPCODE_ROUND: transform_ROUND(c, inst); return 1;
|
|
case RC_OPCODE_RSQ: transform_RSQ(c, inst); return 1;
|
|
case RC_OPCODE_SEQ: transform_SEQ(c, inst); return 1;
|
|
case RC_OPCODE_SGE: transform_SGE(c, inst); return 1;
|
|
case RC_OPCODE_SGT: transform_SGT(c, inst); return 1;
|
|
case RC_OPCODE_SLE: transform_SLE(c, inst); return 1;
|
|
case RC_OPCODE_SLT: transform_SLT(c, inst); return 1;
|
|
case RC_OPCODE_SNE: transform_SNE(c, inst); return 1;
|
|
case RC_OPCODE_SSG: transform_SSG(c, inst); return 1;
|
|
case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
|
|
case RC_OPCODE_TRUNC: transform_TRUNC(c, inst); return 1;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void transform_r300_vertex_CMP(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
/* There is no decent CMP available, so let's rig one up.
|
|
* CMP is defined as dst = src0 < 0.0 ? src1 : src2
|
|
* The following sequence consumes zero to two temps and two extra slots
|
|
* (the second temp and the second slot is consumed by transform_LRP),
|
|
* but should be equivalent:
|
|
*
|
|
* SLT tmp0, src0, 0.0
|
|
* LRP dst, tmp0, src1, src2
|
|
*
|
|
* Yes, I know, I'm a mad scientist. ~ C. & M. */
|
|
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
|
|
|
|
/* SLT tmp0, src0, 0.0 */
|
|
emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
|
|
dst,
|
|
inst->U.I.SrcReg[0], builtin_zero);
|
|
|
|
/* LRP dst, tmp0, src1, src2 */
|
|
transform_LRP(c,
|
|
emit3(c, inst->Prev, RC_OPCODE_LRP, NULL,
|
|
inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[1], inst->U.I.SrcReg[2]));
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_r300_vertex_DP2(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_instruction *next_inst = inst->Next;
|
|
transform_DP2(c, inst);
|
|
next_inst->Prev->U.I.Opcode = RC_OPCODE_DP4;
|
|
}
|
|
|
|
static void transform_r300_vertex_DP3(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_src_register src0 = inst->U.I.SrcReg[0];
|
|
struct rc_src_register src1 = inst->U.I.SrcReg[1];
|
|
src0.Negate &= ~RC_MASK_W;
|
|
src0.Swizzle &= ~(7 << (3 * 3));
|
|
src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
|
|
src1.Negate &= ~RC_MASK_W;
|
|
src1.Swizzle &= ~(7 << (3 * 3));
|
|
src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
|
|
emit2(c, inst->Prev, RC_OPCODE_DP4, &inst->U.I, inst->U.I.DstReg, src0, src1);
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_r300_vertex_fix_LIT(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
|
|
unsigned constant_swizzle;
|
|
int constant = rc_constants_add_immediate_scalar(&c->Program.Constants,
|
|
0.0000000000000000001,
|
|
&constant_swizzle);
|
|
|
|
/* MOV dst, src */
|
|
dst.WriteMask = RC_MASK_XYZW;
|
|
emit1(c, inst->Prev, RC_OPCODE_MOV, NULL,
|
|
dst,
|
|
inst->U.I.SrcReg[0]);
|
|
|
|
/* MAX dst.y, src, 0.00...001 */
|
|
emit2(c, inst->Prev, RC_OPCODE_MAX, NULL,
|
|
dstregtmpmask(dst.Index, RC_MASK_Y),
|
|
srcreg(RC_FILE_TEMPORARY, dst.Index),
|
|
srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
|
|
|
|
inst->U.I.SrcReg[0] = srcreg(RC_FILE_TEMPORARY, dst.Index);
|
|
}
|
|
|
|
static void transform_r300_vertex_SEQ(struct radeon_compiler *c,
|
|
struct rc_instruction *inst)
|
|
{
|
|
/* x = y <==> x >= y && y >= x */
|
|
int tmp = rc_find_free_temporary(c);
|
|
|
|
/* x <= y */
|
|
emit2(c, inst->Prev, RC_OPCODE_SGE, NULL,
|
|
dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask),
|
|
inst->U.I.SrcReg[0],
|
|
inst->U.I.SrcReg[1]);
|
|
|
|
/* y <= x */
|
|
emit2(c, inst->Prev, RC_OPCODE_SGE, NULL,
|
|
inst->U.I.DstReg,
|
|
inst->U.I.SrcReg[1],
|
|
inst->U.I.SrcReg[0]);
|
|
|
|
/* x && y = x * y */
|
|
emit2(c, inst->Prev, RC_OPCODE_MUL, NULL,
|
|
inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, tmp),
|
|
srcreg(inst->U.I.DstReg.File, inst->U.I.DstReg.Index));
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_r300_vertex_SNE(struct radeon_compiler *c,
|
|
struct rc_instruction *inst)
|
|
{
|
|
/* x != y <==> x < y || y < x */
|
|
int tmp = rc_find_free_temporary(c);
|
|
|
|
/* x < y */
|
|
emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
|
|
dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask),
|
|
inst->U.I.SrcReg[0],
|
|
inst->U.I.SrcReg[1]);
|
|
|
|
/* y < x */
|
|
emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
|
|
inst->U.I.DstReg,
|
|
inst->U.I.SrcReg[1],
|
|
inst->U.I.SrcReg[0]);
|
|
|
|
/* x || y = max(x, y) */
|
|
emit2(c, inst->Prev, RC_OPCODE_MAX, NULL,
|
|
inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, tmp),
|
|
srcreg(inst->U.I.DstReg.File, inst->U.I.DstReg.Index));
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_r300_vertex_SGT(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
/* x > y <==> -x < -y */
|
|
inst->U.I.Opcode = RC_OPCODE_SLT;
|
|
inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
|
|
inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
|
|
}
|
|
|
|
static void transform_r300_vertex_SLE(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
/* x <= y <==> -x >= -y */
|
|
inst->U.I.Opcode = RC_OPCODE_SGE;
|
|
inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
|
|
inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
|
|
}
|
|
|
|
static void transform_r300_vertex_SSG(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
/* result = sign(x)
|
|
*
|
|
* SLT tmp0, 0, x;
|
|
* SLT tmp1, x, 0;
|
|
* ADD result, tmp0, -tmp1;
|
|
*/
|
|
struct rc_dst_register dst0;
|
|
unsigned tmp1;
|
|
|
|
/* 0 < x */
|
|
dst0 = try_to_reuse_dst(c, inst);
|
|
emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
|
|
dst0,
|
|
builtin_zero,
|
|
inst->U.I.SrcReg[0]);
|
|
|
|
/* x < 0 */
|
|
tmp1 = rc_find_free_temporary(c);
|
|
emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
|
|
dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask),
|
|
inst->U.I.SrcReg[0],
|
|
builtin_zero);
|
|
|
|
/* Either both are zero, or one of them is one and the other is zero. */
|
|
/* result = tmp0 - tmp1 */
|
|
emit2(c, inst->Prev, RC_OPCODE_ADD, NULL,
|
|
inst->U.I.DstReg,
|
|
srcreg(RC_FILE_TEMPORARY, dst0.Index),
|
|
negate(srcreg(RC_FILE_TEMPORARY, tmp1)));
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
static void transform_vertex_TRUNC(struct radeon_compiler* c,
|
|
struct rc_instruction* inst)
|
|
{
|
|
struct rc_instruction *next = inst->Next;
|
|
|
|
/* next->Prev is removed after each transformation and replaced
|
|
* by a new instruction. */
|
|
transform_TRUNC(c, next->Prev);
|
|
transform_r300_vertex_CMP(c, next->Prev);
|
|
}
|
|
|
|
/**
|
|
* For use with rc_local_transform, this transforms non-native ALU
|
|
* instructions of the r300 up to r500 vertex engine.
|
|
*/
|
|
int r300_transform_vertex_alu(
|
|
struct radeon_compiler * c,
|
|
struct rc_instruction* inst,
|
|
void* unused)
|
|
{
|
|
switch(inst->U.I.Opcode) {
|
|
case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
|
|
case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
|
|
case RC_OPCODE_DP2: transform_r300_vertex_DP2(c, inst); return 1;
|
|
case RC_OPCODE_DP3: transform_r300_vertex_DP3(c, inst); return 1;
|
|
case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
|
|
case RC_OPCODE_LIT: transform_r300_vertex_fix_LIT(c, inst); return 1;
|
|
case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;
|
|
case RC_OPCODE_SEQ:
|
|
if (!c->is_r500) {
|
|
transform_r300_vertex_SEQ(c, inst);
|
|
return 1;
|
|
}
|
|
return 0;
|
|
case RC_OPCODE_SGT: transform_r300_vertex_SGT(c, inst); return 1;
|
|
case RC_OPCODE_SLE: transform_r300_vertex_SLE(c, inst); return 1;
|
|
case RC_OPCODE_SNE:
|
|
if (!c->is_r500) {
|
|
transform_r300_vertex_SNE(c, inst);
|
|
return 1;
|
|
}
|
|
return 0;
|
|
case RC_OPCODE_SSG: transform_r300_vertex_SSG(c, inst); return 1;
|
|
case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
|
|
case RC_OPCODE_TRUNC: transform_vertex_TRUNC(c, inst); return 1;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void sincos_constants(struct radeon_compiler* c, unsigned int *constants)
|
|
{
|
|
static const float SinCosConsts[2][4] = {
|
|
{
|
|
1.273239545, /* 4/PI */
|
|
-0.405284735, /* -4/(PI*PI) */
|
|
3.141592654, /* PI */
|
|
0.2225 /* weight */
|
|
},
|
|
{
|
|
0.75,
|
|
0.5,
|
|
0.159154943, /* 1/(2*PI) */
|
|
6.283185307 /* 2*PI */
|
|
}
|
|
};
|
|
int i;
|
|
|
|
for(i = 0; i < 2; ++i)
|
|
constants[i] = rc_constants_add_immediate_vec4(&c->Program.Constants, SinCosConsts[i]);
|
|
}
|
|
|
|
/**
|
|
* Approximate sin(x), where x is clamped to (-pi/2, pi/2).
|
|
*
|
|
* MUL tmp.xy, src, { 4/PI, -4/(PI^2) }
|
|
* MAD tmp.x, tmp.y, |src|, tmp.x
|
|
* MAD tmp.y, tmp.x, |tmp.x|, -tmp.x
|
|
* MAD dest, tmp.y, weight, tmp.x
|
|
*/
|
|
static void sin_approx(
|
|
struct radeon_compiler* c, struct rc_instruction * inst,
|
|
struct rc_dst_register dst, struct rc_src_register src, const unsigned int* constants)
|
|
{
|
|
unsigned int tempreg = rc_find_free_temporary(c);
|
|
|
|
emit2(c, inst->Prev, RC_OPCODE_MUL, NULL, dstregtmpmask(tempreg, RC_MASK_XY),
|
|
swizzle_xxxx(src),
|
|
srcreg(RC_FILE_CONSTANT, constants[0]));
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_X),
|
|
swizzle_yyyy(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
absolute(swizzle_xxxx(src)),
|
|
swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg)));
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_Y),
|
|
swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
absolute(swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg))),
|
|
negate(swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg))));
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dst,
|
|
swizzle_yyyy(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
swizzle_wwww(srcreg(RC_FILE_CONSTANT, constants[0])),
|
|
swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg)));
|
|
}
|
|
|
|
/**
|
|
* Translate the trigonometric functions COS and SIN
|
|
* using only the basic instructions
|
|
* MOV, ADD, MUL, MAD, FRC
|
|
*/
|
|
int r300_transform_trig_simple(struct radeon_compiler* c,
|
|
struct rc_instruction* inst,
|
|
void* unused)
|
|
{
|
|
unsigned int constants[2];
|
|
unsigned int tempreg;
|
|
|
|
if (inst->U.I.Opcode != RC_OPCODE_COS &&
|
|
inst->U.I.Opcode != RC_OPCODE_SIN)
|
|
return 0;
|
|
|
|
tempreg = rc_find_free_temporary(c);
|
|
|
|
sincos_constants(c, constants);
|
|
|
|
if (inst->U.I.Opcode == RC_OPCODE_COS) {
|
|
/* MAD tmp.x, src, 1/(2*PI), 0.75 */
|
|
/* FRC tmp.x, tmp.x */
|
|
/* MAD tmp.z, tmp.x, 2*PI, -PI */
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_W),
|
|
swizzle_xxxx(inst->U.I.SrcReg[0]),
|
|
swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[1])),
|
|
swizzle_xxxx(srcreg(RC_FILE_CONSTANT, constants[1])));
|
|
emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(tempreg, RC_MASK_W),
|
|
swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)));
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_W),
|
|
swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
swizzle_wwww(srcreg(RC_FILE_CONSTANT, constants[1])),
|
|
negate(swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[0]))));
|
|
|
|
sin_approx(c, inst, inst->U.I.DstReg,
|
|
swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
constants);
|
|
} else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_W),
|
|
swizzle_xxxx(inst->U.I.SrcReg[0]),
|
|
swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[1])),
|
|
swizzle_yyyy(srcreg(RC_FILE_CONSTANT, constants[1])));
|
|
emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(tempreg, RC_MASK_W),
|
|
swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)));
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_W),
|
|
swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
swizzle_wwww(srcreg(RC_FILE_CONSTANT, constants[1])),
|
|
negate(swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[0]))));
|
|
|
|
sin_approx(c, inst, inst->U.I.DstReg,
|
|
swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
constants);
|
|
} else {
|
|
struct rc_dst_register dst;
|
|
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_XY),
|
|
swizzle_xxxx(inst->U.I.SrcReg[0]),
|
|
swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[1])),
|
|
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_W));
|
|
emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(tempreg, RC_MASK_XY),
|
|
srcreg(RC_FILE_TEMPORARY, tempreg));
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_XY),
|
|
srcreg(RC_FILE_TEMPORARY, tempreg),
|
|
swizzle_wwww(srcreg(RC_FILE_CONSTANT, constants[1])),
|
|
negate(swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[0]))));
|
|
|
|
dst = inst->U.I.DstReg;
|
|
|
|
dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_X;
|
|
sin_approx(c, inst, dst,
|
|
swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
constants);
|
|
|
|
dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_Y;
|
|
sin_approx(c, inst, dst,
|
|
swizzle_yyyy(srcreg(RC_FILE_TEMPORARY, tempreg)),
|
|
constants);
|
|
}
|
|
|
|
rc_remove_instruction(inst);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void r300_transform_SIN_COS(struct radeon_compiler *c,
|
|
struct rc_instruction *inst,
|
|
unsigned srctmp)
|
|
{
|
|
if (inst->U.I.Opcode == RC_OPCODE_COS) {
|
|
emit1(c, inst->Prev, RC_OPCODE_COS, &inst->U.I, inst->U.I.DstReg,
|
|
srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
|
|
} else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
|
|
emit1(c, inst->Prev, RC_OPCODE_SIN, &inst->U.I,
|
|
inst->U.I.DstReg, srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
|
|
}
|
|
|
|
rc_remove_instruction(inst);
|
|
}
|
|
|
|
|
|
/**
|
|
* Transform the trigonometric functions COS and SIN
|
|
* to include pre-scaling by 1/(2*PI) and taking the fractional
|
|
* part, so that the input to COS and SIN is always in the range [0,1).
|
|
*
|
|
* @warning This transformation implicitly changes the semantics of SIN and COS!
|
|
*/
|
|
int radeonTransformTrigScale(struct radeon_compiler* c,
|
|
struct rc_instruction* inst,
|
|
void* unused)
|
|
{
|
|
static const float RCP_2PI = 0.15915494309189535;
|
|
unsigned int temp;
|
|
unsigned int constant;
|
|
unsigned int constant_swizzle;
|
|
|
|
if (inst->U.I.Opcode != RC_OPCODE_COS &&
|
|
inst->U.I.Opcode != RC_OPCODE_SIN)
|
|
return 0;
|
|
|
|
temp = rc_find_free_temporary(c);
|
|
constant = rc_constants_add_immediate_scalar(&c->Program.Constants, RCP_2PI, &constant_swizzle);
|
|
|
|
emit2(c, inst->Prev, RC_OPCODE_MUL, NULL, dstregtmpmask(temp, RC_MASK_W),
|
|
swizzle_xxxx(inst->U.I.SrcReg[0]),
|
|
srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
|
|
emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(temp, RC_MASK_W),
|
|
srcreg(RC_FILE_TEMPORARY, temp));
|
|
|
|
r300_transform_SIN_COS(c, inst, temp);
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* Transform the trigonometric functions COS and SIN
|
|
* so that the input to COS and SIN is always in the range [-PI, PI].
|
|
*/
|
|
int r300_transform_trig_scale_vertex(struct radeon_compiler *c,
|
|
struct rc_instruction *inst,
|
|
void *unused)
|
|
{
|
|
static const float cons[4] = {0.15915494309189535, 0.5, 6.28318530717959, -3.14159265358979};
|
|
unsigned int temp;
|
|
unsigned int constant;
|
|
|
|
if (inst->U.I.Opcode != RC_OPCODE_COS &&
|
|
inst->U.I.Opcode != RC_OPCODE_SIN)
|
|
return 0;
|
|
|
|
/* Repeat x in the range [-PI, PI]:
|
|
*
|
|
* repeat(x) = frac(x / 2PI + 0.5) * 2PI - PI
|
|
*/
|
|
|
|
temp = rc_find_free_temporary(c);
|
|
constant = rc_constants_add_immediate_vec4(&c->Program.Constants, cons);
|
|
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(temp, RC_MASK_W),
|
|
swizzle_xxxx(inst->U.I.SrcReg[0]),
|
|
srcregswz(RC_FILE_CONSTANT, constant, RC_SWIZZLE_XXXX),
|
|
srcregswz(RC_FILE_CONSTANT, constant, RC_SWIZZLE_YYYY));
|
|
emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(temp, RC_MASK_W),
|
|
srcreg(RC_FILE_TEMPORARY, temp));
|
|
emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(temp, RC_MASK_W),
|
|
srcreg(RC_FILE_TEMPORARY, temp),
|
|
srcregswz(RC_FILE_CONSTANT, constant, RC_SWIZZLE_ZZZZ),
|
|
srcregswz(RC_FILE_CONSTANT, constant, RC_SWIZZLE_WWWW));
|
|
|
|
r300_transform_SIN_COS(c, inst, temp);
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* Replaces DDX/DDY instructions with MOV 0 to avoid using dummy shaders on r300/r400.
|
|
*
|
|
* @warning This explicitly changes the form of DDX and DDY!
|
|
*/
|
|
|
|
int radeonStubDeriv(struct radeon_compiler* c,
|
|
struct rc_instruction* inst,
|
|
void* unused)
|
|
{
|
|
if (inst->U.I.Opcode != RC_OPCODE_DDX && inst->U.I.Opcode != RC_OPCODE_DDY)
|
|
return 0;
|
|
|
|
inst->U.I.Opcode = RC_OPCODE_MOV;
|
|
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* Rewrite DDX/DDY instructions to properly work with r5xx shaders.
|
|
* The r5xx MDH/MDV instruction provides per-quad partial derivatives.
|
|
* It takes the form A*B+C. A and C are set by setting src0. B should be -1.
|
|
*
|
|
* @warning This explicitly changes the form of DDX and DDY!
|
|
*/
|
|
|
|
int radeonTransformDeriv(struct radeon_compiler* c,
|
|
struct rc_instruction* inst,
|
|
void* unused)
|
|
{
|
|
if (inst->U.I.Opcode != RC_OPCODE_DDX && inst->U.I.Opcode != RC_OPCODE_DDY)
|
|
return 0;
|
|
|
|
inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_1111;
|
|
inst->U.I.SrcReg[1].Negate = RC_MASK_XYZW;
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* IF Temp[0].x -> IF Temp[0].x
|
|
* ... -> ...
|
|
* KILL -> KIL -abs(Temp[0].x)
|
|
* ... -> ...
|
|
* ENDIF -> ENDIF
|
|
*
|
|
* === OR ===
|
|
*
|
|
* IF Temp[0].x -> IF Temp[0].x
|
|
* ... -> ...
|
|
* ELSE -> ELSE
|
|
* ... -> ...
|
|
* KILL -> KIL -abs(Temp[0].x)
|
|
* ... -> ...
|
|
* ENDIF -> ENDIF
|
|
*
|
|
* === OR ===
|
|
*
|
|
* KILL -> KIL -none.1111
|
|
*
|
|
* This needs to be done in its own pass, because it might modify the
|
|
* instructions before and after KILL.
|
|
*/
|
|
void rc_transform_KILL(struct radeon_compiler * c, void *user)
|
|
{
|
|
struct rc_instruction * inst;
|
|
for (inst = c->Program.Instructions.Next;
|
|
inst != &c->Program.Instructions; inst = inst->Next) {
|
|
struct rc_instruction * if_inst;
|
|
unsigned in_if = 0;
|
|
|
|
if (inst->U.I.Opcode != RC_OPCODE_KILP)
|
|
continue;
|
|
|
|
for (if_inst = inst->Prev; if_inst != &c->Program.Instructions;
|
|
if_inst = if_inst->Prev) {
|
|
|
|
if (if_inst->U.I.Opcode == RC_OPCODE_IF) {
|
|
in_if = 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
inst->U.I.Opcode = RC_OPCODE_KIL;
|
|
|
|
if (!in_if) {
|
|
inst->U.I.SrcReg[0] = negate(builtin_one);
|
|
} else {
|
|
/* This should work even if the KILP is inside the ELSE
|
|
* block, because -0.0 is considered negative. */
|
|
inst->U.I.SrcReg[0] =
|
|
negate(absolute(if_inst->U.I.SrcReg[0]));
|
|
}
|
|
}
|
|
}
|
|
|
|
int rc_force_output_alpha_to_one(struct radeon_compiler *c,
|
|
struct rc_instruction *inst, void *data)
|
|
{
|
|
struct r300_fragment_program_compiler *fragc = (struct r300_fragment_program_compiler*)c;
|
|
const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode);
|
|
unsigned tmp;
|
|
|
|
if (!info->HasDstReg || inst->U.I.DstReg.File != RC_FILE_OUTPUT ||
|
|
inst->U.I.DstReg.Index == fragc->OutputDepth)
|
|
return 1;
|
|
|
|
tmp = rc_find_free_temporary(c);
|
|
|
|
/* Insert MOV after inst, set alpha to 1. */
|
|
emit1(c, inst, RC_OPCODE_MOV, NULL, inst->U.I.DstReg,
|
|
srcregswz(RC_FILE_TEMPORARY, tmp, RC_SWIZZLE_XYZ1));
|
|
|
|
/* Re-route the destination of inst to the source of mov. */
|
|
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
|
|
inst->U.I.DstReg.Index = tmp;
|
|
|
|
/* Move the saturate output modifier to the MOV instruction
|
|
* (for better copy propagation). */
|
|
inst->Next->U.I.SaturateMode = inst->U.I.SaturateMode;
|
|
inst->U.I.SaturateMode = RC_SATURATE_NONE;
|
|
return 1;
|
|
}
|