1359 lines
37 KiB
C
1359 lines
37 KiB
C
/*
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* Copyright (C) 2009 Nicolai Haehnle.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "radeon_program_pair.h"
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#include <stdio.h>
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#include "radeon_compiler.h"
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#include "radeon_compiler_util.h"
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#include "radeon_dataflow.h"
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#include "radeon_list.h"
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#include "radeon_variable.h"
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#include "util/u_debug.h"
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#define VERBOSE 0
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#define DBG(...) do { if (VERBOSE) fprintf(stderr, __VA_ARGS__); } while(0)
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struct schedule_instruction {
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struct rc_instruction * Instruction;
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/** Next instruction in the linked list of ready instructions. */
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struct schedule_instruction *NextReady;
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/** Values that this instruction reads and writes */
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struct reg_value * WriteValues[4];
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struct reg_value * ReadValues[12];
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unsigned int NumWriteValues:3;
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unsigned int NumReadValues:4;
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/**
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* Number of (read and write) dependencies that must be resolved before
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* this instruction can be scheduled.
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*/
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unsigned int NumDependencies:5;
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/** List of all readers (see rc_get_readers() for the definition of
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* "all readers"), even those outside the basic block this instruction
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* lives in. */
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struct rc_reader_data GlobalReaders;
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/** If the scheduler has paired an RGB and an Alpha instruction together,
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* PairedInst references the alpha instruction's dependency information.
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*/
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struct schedule_instruction * PairedInst;
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/** This scheduler uses the value of Score to determine which
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* instruction to schedule. Instructions with a higher value of Score
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* will be scheduled first. */
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int Score;
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/** The number of components that read from a TEX instruction. */
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unsigned TexReadCount;
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/** For TEX instructions a list of readers */
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struct rc_list * TexReaders;
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};
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/**
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* Used to keep track of which instructions read a value.
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*/
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struct reg_value_reader {
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struct schedule_instruction *Reader;
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struct reg_value_reader *Next;
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};
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/**
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* Used to keep track which values are stored in each component of a
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* RC_FILE_TEMPORARY.
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*/
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struct reg_value {
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struct schedule_instruction * Writer;
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/**
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* Unordered linked list of instructions that read from this value.
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* When this value becomes available, we increase all readers'
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* dependency count.
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*/
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struct reg_value_reader *Readers;
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/**
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* Number of readers of this value. This is decremented each time
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* a reader of the value is committed.
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* When the reader count reaches zero, the dependency count
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* of the instruction writing \ref Next is decremented.
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*/
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unsigned int NumReaders;
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struct reg_value *Next; /**< Pointer to the next value to be written to the same register */
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};
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struct register_state {
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struct reg_value * Values[4];
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};
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struct remap_reg {
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struct rc_instruction * Inst;
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unsigned int OldIndex:(RC_REGISTER_INDEX_BITS+1);
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unsigned int OldSwizzle:3;
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unsigned int NewIndex:(RC_REGISTER_INDEX_BITS+1);
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unsigned int NewSwizzle:3;
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unsigned int OnlyTexReads:1;
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struct remap_reg * Next;
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};
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struct schedule_state {
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struct radeon_compiler * C;
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struct schedule_instruction * Current;
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/** Array of the previous writers of Current's destination register
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* indexed by channel. */
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struct schedule_instruction * PrevWriter[4];
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struct register_state Temporary[RC_REGISTER_MAX_INDEX];
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/**
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* Linked lists of instructions that can be scheduled right now,
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* based on which ALU/TEX resources they require.
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*/
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/*@{*/
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struct schedule_instruction *ReadyFullALU;
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struct schedule_instruction *ReadyRGB;
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struct schedule_instruction *ReadyAlpha;
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struct schedule_instruction *ReadyTEX;
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/*@}*/
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struct rc_list *PendingTEX;
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void (*CalcScore)(struct schedule_instruction *);
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long max_tex_group;
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unsigned PrevBlockHasTex:1;
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unsigned TEXCount;
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unsigned Opt:1;
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};
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static struct reg_value ** get_reg_valuep(struct schedule_state * s,
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rc_register_file file, unsigned int index, unsigned int chan)
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{
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if (file != RC_FILE_TEMPORARY)
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return NULL;
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if (index >= RC_REGISTER_MAX_INDEX) {
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rc_error(s->C, "%s: index %i out of bounds\n", __FUNCTION__, index);
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return NULL;
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}
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return &s->Temporary[index].Values[chan];
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}
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static unsigned get_tex_read_count(struct schedule_instruction * sinst)
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{
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unsigned tex_read_count = sinst->TexReadCount;
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if (sinst->PairedInst) {
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tex_read_count += sinst->PairedInst->TexReadCount;
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}
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return tex_read_count;
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}
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#if VERBOSE
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static void print_list(struct schedule_instruction * sinst)
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{
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struct schedule_instruction * ptr;
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for (ptr = sinst; ptr; ptr=ptr->NextReady) {
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unsigned tex_read_count = get_tex_read_count(ptr);
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unsigned score = sinst->Score;
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fprintf(stderr,"%u (%d) [%u],", ptr->Instruction->IP, score,
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tex_read_count);
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}
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fprintf(stderr, "\n");
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}
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#endif
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static void remove_inst_from_list(struct schedule_instruction ** list,
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struct schedule_instruction * inst)
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{
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struct schedule_instruction * prev = NULL;
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struct schedule_instruction * list_ptr;
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for (list_ptr = *list; list_ptr; prev = list_ptr,
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list_ptr = list_ptr->NextReady) {
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if (list_ptr == inst) {
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if (prev) {
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prev->NextReady = inst->NextReady;
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} else {
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*list = inst->NextReady;
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}
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inst->NextReady = NULL;
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break;
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}
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}
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}
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static void add_inst_to_list(struct schedule_instruction ** list, struct schedule_instruction * inst)
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{
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inst->NextReady = *list;
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*list = inst;
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}
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static void add_inst_to_list_score(struct schedule_instruction ** list,
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struct schedule_instruction * inst)
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{
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struct schedule_instruction * temp;
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struct schedule_instruction * prev;
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if (!*list) {
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*list = inst;
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return;
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}
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temp = *list;
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prev = NULL;
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while(temp && inst->Score <= temp->Score) {
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prev = temp;
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temp = temp->NextReady;
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}
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if (!prev) {
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inst->NextReady = temp;
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*list = inst;
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} else {
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prev->NextReady = inst;
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inst->NextReady = temp;
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}
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}
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static void instruction_ready(struct schedule_state * s, struct schedule_instruction * sinst)
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{
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DBG("%i is now ready\n", sinst->Instruction->IP);
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/* Adding Ready TEX instructions to the end of the "Ready List" helps
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* us emit TEX instructions in blocks without losing our place. */
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if (sinst->Instruction->Type == RC_INSTRUCTION_NORMAL)
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add_inst_to_list_score(&s->ReadyTEX, sinst);
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else if (sinst->Instruction->U.P.Alpha.Opcode == RC_OPCODE_NOP)
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add_inst_to_list_score(&s->ReadyRGB, sinst);
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else if (sinst->Instruction->U.P.RGB.Opcode == RC_OPCODE_NOP)
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add_inst_to_list_score(&s->ReadyAlpha, sinst);
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else
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add_inst_to_list_score(&s->ReadyFullALU, sinst);
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}
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static void decrease_dependencies(struct schedule_state * s, struct schedule_instruction * sinst)
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{
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assert(sinst->NumDependencies > 0);
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sinst->NumDependencies--;
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if (!sinst->NumDependencies)
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instruction_ready(s, sinst);
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}
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/* These functions provide different heuristics for scheduling instructions.
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* The default is calc_score_readers. */
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#if 0
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static void calc_score_zero(struct schedule_instruction * sinst)
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{
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sinst->Score = 0;
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}
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static void calc_score_deps(struct schedule_instruction * sinst)
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{
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int i;
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sinst->Score = 0;
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for (i = 0; i < sinst->NumWriteValues; i++) {
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struct reg_value * v = sinst->WriteValues[i];
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if (v->NumReaders) {
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struct reg_value_reader * r;
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for (r = v->Readers; r; r = r->Next) {
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if (r->Reader->NumDependencies == 1) {
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sinst->Score += 100;
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}
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sinst->Score += r->Reader->NumDependencies;
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}
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}
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}
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}
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#endif
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#define NO_OUTPUT_SCORE (1 << 24)
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static void score_no_output(struct schedule_instruction * sinst)
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{
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assert(sinst->Instruction->Type != RC_INSTRUCTION_NORMAL);
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if (!sinst->Instruction->U.P.RGB.OutputWriteMask &&
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!sinst->Instruction->U.P.Alpha.OutputWriteMask) {
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if (sinst->PairedInst) {
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if (!sinst->PairedInst->Instruction->U.P.
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RGB.OutputWriteMask
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&& !sinst->PairedInst->Instruction->U.P.
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Alpha.OutputWriteMask) {
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sinst->Score |= NO_OUTPUT_SCORE;
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}
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} else {
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sinst->Score |= NO_OUTPUT_SCORE;
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}
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}
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}
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#define PAIRED_SCORE (1 << 16)
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static void calc_score_r300(struct schedule_instruction * sinst)
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{
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unsigned src_idx;
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if (sinst->Instruction->Type == RC_INSTRUCTION_NORMAL) {
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sinst->Score = 0;
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return;
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}
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score_no_output(sinst);
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if (sinst->PairedInst) {
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sinst->Score |= PAIRED_SCORE;
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return;
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}
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for (src_idx = 0; src_idx < 4; src_idx++) {
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sinst->Score += sinst->Instruction->U.P.RGB.Src[src_idx].Used +
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sinst->Instruction->U.P.Alpha.Src[src_idx].Used;
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}
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}
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#define NO_READ_TEX_SCORE (1 << 16)
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static void calc_score_readers(struct schedule_instruction * sinst)
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{
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if (sinst->Instruction->Type == RC_INSTRUCTION_NORMAL) {
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sinst->Score = 0;
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} else {
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sinst->Score = sinst->NumReadValues;
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if (sinst->PairedInst) {
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sinst->Score += sinst->PairedInst->NumReadValues;
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}
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if (get_tex_read_count(sinst) == 0) {
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sinst->Score |= NO_READ_TEX_SCORE;
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}
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score_no_output(sinst);
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}
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}
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/**
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* This function decreases the dependencies of the next instruction that
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* wants to write to each of sinst's read values.
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*/
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static void commit_update_reads(struct schedule_state * s,
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struct schedule_instruction * sinst){
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unsigned int i;
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for(i = 0; i < sinst->NumReadValues; ++i) {
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struct reg_value * v = sinst->ReadValues[i];
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assert(v->NumReaders > 0);
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v->NumReaders--;
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if (!v->NumReaders) {
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if (v->Next) {
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decrease_dependencies(s, v->Next->Writer);
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}
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}
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}
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if (sinst->PairedInst) {
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commit_update_reads(s, sinst->PairedInst);
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}
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}
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static void commit_update_writes(struct schedule_state * s,
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struct schedule_instruction * sinst){
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unsigned int i;
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for(i = 0; i < sinst->NumWriteValues; ++i) {
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struct reg_value * v = sinst->WriteValues[i];
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if (v->NumReaders) {
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for(struct reg_value_reader * r = v->Readers; r; r = r->Next) {
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decrease_dependencies(s, r->Reader);
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}
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} else {
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/* This happens in instruction sequences of the type
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* OP r.x, ...;
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* OP r.x, r.x, ...;
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* See also the subtlety in how instructions that both
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* read and write the same register are scanned.
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*/
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if (v->Next)
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decrease_dependencies(s, v->Next->Writer);
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}
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}
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if (sinst->PairedInst) {
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commit_update_writes(s, sinst->PairedInst);
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}
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}
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static void notify_sem_wait(struct schedule_state *s)
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{
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struct rc_list * pend_ptr;
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for (pend_ptr = s->PendingTEX; pend_ptr; pend_ptr = pend_ptr->Next) {
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struct rc_list * read_ptr;
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struct schedule_instruction * pending = pend_ptr->Item;
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for (read_ptr = pending->TexReaders; read_ptr;
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read_ptr = read_ptr->Next) {
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struct schedule_instruction * reader = read_ptr->Item;
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reader->TexReadCount--;
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}
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}
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s->PendingTEX = NULL;
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}
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static void commit_alu_instruction(struct schedule_state * s, struct schedule_instruction * sinst)
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{
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DBG("%i: commit score = %d\n", sinst->Instruction->IP, sinst->Score);
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commit_update_reads(s, sinst);
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commit_update_writes(s, sinst);
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if (get_tex_read_count(sinst) > 0) {
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sinst->Instruction->U.P.SemWait = 1;
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notify_sem_wait(s);
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}
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}
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/**
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* Emit all ready texture instructions in a single block.
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*
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* Emit as a single block to (hopefully) sample many textures in parallel,
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* and to avoid hardware indirections on R300.
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*/
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static void emit_all_tex(struct schedule_state * s, struct rc_instruction * before)
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{
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struct schedule_instruction *readytex;
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struct rc_instruction * inst_begin;
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assert(s->ReadyTEX);
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notify_sem_wait(s);
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/* Node marker for R300 */
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inst_begin = rc_insert_new_instruction(s->C, before->Prev);
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inst_begin->U.I.Opcode = RC_OPCODE_BEGIN_TEX;
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/* Link texture instructions back in */
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readytex = s->ReadyTEX;
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while(readytex) {
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rc_insert_instruction(before->Prev, readytex->Instruction);
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DBG("%i: commit TEX reads\n", readytex->Instruction->IP);
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/* All of the TEX instructions in the same TEX block have
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* their source registers read from before any of the
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* instructions in that block write to their destination
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* registers. This means that when we commit a TEX
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* instruction, any other TEX instruction that wants to write
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* to one of the committed instruction's source register can be
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* marked as ready and should be emitted in the same TEX
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* block. This prevents the following sequence from being
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* emitted in two different TEX blocks:
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* 0: TEX temp[0].xyz, temp[1].xy__, 2D[0];
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* 1: TEX temp[1].xyz, temp[2].xy__, 2D[0];
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*/
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commit_update_reads(s, readytex);
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readytex = readytex->NextReady;
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}
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readytex = s->ReadyTEX;
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s->ReadyTEX = NULL;
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while(readytex){
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DBG("%i: commit TEX writes\n", readytex->Instruction->IP);
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commit_update_writes(s, readytex);
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/* Set semaphore bits for last TEX instruction in the block */
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if (!readytex->NextReady) {
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readytex->Instruction->U.I.TexSemAcquire = 1;
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readytex->Instruction->U.I.TexSemWait = 1;
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}
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rc_list_add(&s->PendingTEX, rc_list(&s->C->Pool, readytex));
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readytex = readytex->NextReady;
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}
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}
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/* This is a helper function for destructive_merge_instructions(). It helps
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* merge presubtract sources from two instructions and makes sure the
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* presubtract sources end up in the correct spot. This function assumes that
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* dst_full is an rgb instruction, meaning that it has a vector instruction(rgb)
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* but no scalar instruction (alpha).
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* @return 0 if merging the presubtract sources fails.
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* @retrun 1 if merging the presubtract sources succeeds.
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*/
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static int merge_presub_sources(
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struct rc_pair_instruction * dst_full,
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struct rc_pair_sub_instruction src,
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unsigned int type)
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{
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unsigned int srcp_src, srcp_regs, is_rgb, is_alpha;
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struct rc_pair_sub_instruction * dst_sub;
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const struct rc_opcode_info * info;
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assert(dst_full->Alpha.Opcode == RC_OPCODE_NOP);
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switch(type) {
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case RC_SOURCE_RGB:
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is_rgb = 1;
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is_alpha = 0;
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dst_sub = &dst_full->RGB;
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break;
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case RC_SOURCE_ALPHA:
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is_rgb = 0;
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is_alpha = 1;
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dst_sub = &dst_full->Alpha;
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break;
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default:
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assert(0);
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return 0;
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}
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info = rc_get_opcode_info(dst_full->RGB.Opcode);
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|
|
if (dst_sub->Src[RC_PAIR_PRESUB_SRC].Used)
|
|
return 0;
|
|
|
|
srcp_regs = rc_presubtract_src_reg_count(
|
|
src.Src[RC_PAIR_PRESUB_SRC].Index);
|
|
for(srcp_src = 0; srcp_src < srcp_regs; srcp_src++) {
|
|
unsigned int arg;
|
|
int free_source;
|
|
unsigned int one_way = 0;
|
|
struct rc_pair_instruction_source srcp = src.Src[srcp_src];
|
|
struct rc_pair_instruction_source temp;
|
|
|
|
free_source = rc_pair_alloc_source(dst_full, is_rgb, is_alpha,
|
|
srcp.File, srcp.Index);
|
|
|
|
/* If free_source < 0 then there are no free source
|
|
* slots. */
|
|
if (free_source < 0)
|
|
return 0;
|
|
|
|
temp = dst_sub->Src[srcp_src];
|
|
dst_sub->Src[srcp_src] = dst_sub->Src[free_source];
|
|
|
|
/* srcp needs src0 and src1 to be the same */
|
|
if (free_source < srcp_src) {
|
|
if (!temp.Used)
|
|
continue;
|
|
free_source = rc_pair_alloc_source(dst_full, is_rgb,
|
|
is_alpha, temp.File, temp.Index);
|
|
if (free_source < 0)
|
|
return 0;
|
|
one_way = 1;
|
|
} else {
|
|
dst_sub->Src[free_source] = temp;
|
|
}
|
|
|
|
/* If free_source == srcp_src, then the presubtract
|
|
* source is already in the correct place. */
|
|
if (free_source == srcp_src)
|
|
continue;
|
|
|
|
/* Shuffle the sources, so we can put the
|
|
* presubtract source in the correct place. */
|
|
for(arg = 0; arg < info->NumSrcRegs; arg++) {
|
|
/*If this arg does not read from an rgb source,
|
|
* do nothing. */
|
|
if (!(rc_source_type_swz(dst_full->RGB.Arg[arg].Swizzle)
|
|
& type)) {
|
|
continue;
|
|
}
|
|
|
|
if (dst_full->RGB.Arg[arg].Source == srcp_src)
|
|
dst_full->RGB.Arg[arg].Source = free_source;
|
|
/* We need to do this just in case register
|
|
* is one of the sources already, but in the
|
|
* wrong spot. */
|
|
else if(dst_full->RGB.Arg[arg].Source == free_source
|
|
&& !one_way) {
|
|
dst_full->RGB.Arg[arg].Source = srcp_src;
|
|
}
|
|
}
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
|
|
/* This function assumes that rgb.Alpha and alpha.RGB are unused */
|
|
static int destructive_merge_instructions(
|
|
struct rc_pair_instruction * rgb,
|
|
struct rc_pair_instruction * alpha)
|
|
{
|
|
const struct rc_opcode_info * opcode;
|
|
|
|
assert(rgb->Alpha.Opcode == RC_OPCODE_NOP);
|
|
assert(alpha->RGB.Opcode == RC_OPCODE_NOP);
|
|
|
|
/* Presubtract registers need to be merged first so that registers
|
|
* needed by the presubtract operation can be placed in src0 and/or
|
|
* src1. */
|
|
|
|
/* Merge the rgb presubtract registers. */
|
|
if (alpha->RGB.Src[RC_PAIR_PRESUB_SRC].Used) {
|
|
if (!merge_presub_sources(rgb, alpha->RGB, RC_SOURCE_RGB)) {
|
|
return 0;
|
|
}
|
|
}
|
|
/* Merge the alpha presubtract registers */
|
|
if (alpha->Alpha.Src[RC_PAIR_PRESUB_SRC].Used) {
|
|
if(!merge_presub_sources(rgb, alpha->Alpha, RC_SOURCE_ALPHA)){
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* Copy alpha args into rgb */
|
|
opcode = rc_get_opcode_info(alpha->Alpha.Opcode);
|
|
|
|
for(unsigned int arg = 0; arg < opcode->NumSrcRegs; ++arg) {
|
|
unsigned int srcrgb = 0;
|
|
unsigned int srcalpha = 0;
|
|
unsigned int oldsrc = alpha->Alpha.Arg[arg].Source;
|
|
rc_register_file file = 0;
|
|
unsigned int index = 0;
|
|
int source;
|
|
|
|
if (GET_SWZ(alpha->Alpha.Arg[arg].Swizzle, 0) < 3) {
|
|
srcrgb = 1;
|
|
file = alpha->RGB.Src[oldsrc].File;
|
|
index = alpha->RGB.Src[oldsrc].Index;
|
|
} else if (GET_SWZ(alpha->Alpha.Arg[arg].Swizzle, 0) < 4) {
|
|
srcalpha = 1;
|
|
file = alpha->Alpha.Src[oldsrc].File;
|
|
index = alpha->Alpha.Src[oldsrc].Index;
|
|
}
|
|
|
|
source = rc_pair_alloc_source(rgb, srcrgb, srcalpha, file, index);
|
|
if (source < 0)
|
|
return 0;
|
|
|
|
rgb->Alpha.Arg[arg].Source = source;
|
|
rgb->Alpha.Arg[arg].Swizzle = alpha->Alpha.Arg[arg].Swizzle;
|
|
rgb->Alpha.Arg[arg].Abs = alpha->Alpha.Arg[arg].Abs;
|
|
rgb->Alpha.Arg[arg].Negate = alpha->Alpha.Arg[arg].Negate;
|
|
}
|
|
|
|
/* Copy alpha opcode into rgb */
|
|
rgb->Alpha.Opcode = alpha->Alpha.Opcode;
|
|
rgb->Alpha.DestIndex = alpha->Alpha.DestIndex;
|
|
rgb->Alpha.WriteMask = alpha->Alpha.WriteMask;
|
|
rgb->Alpha.OutputWriteMask = alpha->Alpha.OutputWriteMask;
|
|
rgb->Alpha.DepthWriteMask = alpha->Alpha.DepthWriteMask;
|
|
rgb->Alpha.Saturate = alpha->Alpha.Saturate;
|
|
rgb->Alpha.Omod = alpha->Alpha.Omod;
|
|
|
|
/* Merge ALU result writing */
|
|
if (alpha->WriteALUResult) {
|
|
if (rgb->WriteALUResult)
|
|
return 0;
|
|
|
|
rgb->WriteALUResult = alpha->WriteALUResult;
|
|
rgb->ALUResultCompare = alpha->ALUResultCompare;
|
|
}
|
|
|
|
/* Copy SemWait */
|
|
rgb->SemWait |= alpha->SemWait;
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* Try to merge the given instructions into the rgb instructions.
|
|
*
|
|
* Return true on success; on failure, return false, and keep
|
|
* the instructions untouched.
|
|
*/
|
|
static int merge_instructions(struct rc_pair_instruction * rgb, struct rc_pair_instruction * alpha)
|
|
{
|
|
struct rc_pair_instruction backup;
|
|
|
|
/*Instructions can't write output registers and ALU result at the
|
|
* same time. */
|
|
if ((rgb->WriteALUResult && alpha->Alpha.OutputWriteMask)
|
|
|| (rgb->RGB.OutputWriteMask && alpha->WriteALUResult)) {
|
|
return 0;
|
|
}
|
|
|
|
/* Writing output registers in the middle of shaders is slow, so
|
|
* we don't want to pair output writes with temp writes. */
|
|
if ((rgb->RGB.OutputWriteMask && !alpha->Alpha.OutputWriteMask)
|
|
|| (!rgb->RGB.OutputWriteMask && alpha->Alpha.OutputWriteMask)) {
|
|
return 0;
|
|
}
|
|
|
|
memcpy(&backup, rgb, sizeof(struct rc_pair_instruction));
|
|
|
|
if (destructive_merge_instructions(rgb, alpha))
|
|
return 1;
|
|
|
|
memcpy(rgb, &backup, sizeof(struct rc_pair_instruction));
|
|
return 0;
|
|
}
|
|
|
|
static void presub_nop(struct rc_instruction * emitted) {
|
|
int prev_rgb_index, prev_alpha_index, i, num_src;
|
|
|
|
/* We don't need a nop if the previous instruction is a TEX. */
|
|
if (emitted->Prev->Type != RC_INSTRUCTION_PAIR) {
|
|
return;
|
|
}
|
|
if (emitted->Prev->U.P.RGB.WriteMask)
|
|
prev_rgb_index = emitted->Prev->U.P.RGB.DestIndex;
|
|
else
|
|
prev_rgb_index = -1;
|
|
if (emitted->Prev->U.P.Alpha.WriteMask)
|
|
prev_alpha_index = emitted->Prev->U.P.Alpha.DestIndex;
|
|
else
|
|
prev_alpha_index = 1;
|
|
|
|
/* Check the previous rgb instruction */
|
|
if (emitted->U.P.RGB.Src[RC_PAIR_PRESUB_SRC].Used) {
|
|
num_src = rc_presubtract_src_reg_count(
|
|
emitted->U.P.RGB.Src[RC_PAIR_PRESUB_SRC].Index);
|
|
for (i = 0; i < num_src; i++) {
|
|
unsigned int index = emitted->U.P.RGB.Src[i].Index;
|
|
if (emitted->U.P.RGB.Src[i].File == RC_FILE_TEMPORARY
|
|
&& (index == prev_rgb_index
|
|
|| index == prev_alpha_index)) {
|
|
emitted->Prev->U.P.Nop = 1;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Check the previous alpha instruction. */
|
|
if (!emitted->U.P.Alpha.Src[RC_PAIR_PRESUB_SRC].Used)
|
|
return;
|
|
|
|
num_src = rc_presubtract_src_reg_count(
|
|
emitted->U.P.Alpha.Src[RC_PAIR_PRESUB_SRC].Index);
|
|
for (i = 0; i < num_src; i++) {
|
|
unsigned int index = emitted->U.P.Alpha.Src[i].Index;
|
|
if(emitted->U.P.Alpha.Src[i].File == RC_FILE_TEMPORARY
|
|
&& (index == prev_rgb_index || index == prev_alpha_index)) {
|
|
emitted->Prev->U.P.Nop = 1;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void rgb_to_alpha_remap (
|
|
struct rc_instruction * inst,
|
|
struct rc_pair_instruction_arg * arg,
|
|
rc_register_file old_file,
|
|
rc_swizzle old_swz,
|
|
unsigned int new_index)
|
|
{
|
|
int new_src_index;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
if (get_swz(arg->Swizzle, i) == old_swz) {
|
|
SET_SWZ(arg->Swizzle, i, RC_SWIZZLE_W);
|
|
}
|
|
}
|
|
new_src_index = rc_pair_alloc_source(&inst->U.P, 0, 1,
|
|
old_file, new_index);
|
|
/* This conversion is not possible, we must have made a mistake in
|
|
* is_rgb_to_alpha_possible. */
|
|
if (new_src_index < 0) {
|
|
assert(0);
|
|
return;
|
|
}
|
|
|
|
arg->Source = new_src_index;
|
|
}
|
|
|
|
static int can_remap(unsigned int opcode)
|
|
{
|
|
switch(opcode) {
|
|
case RC_OPCODE_DDX:
|
|
case RC_OPCODE_DDY:
|
|
return 0;
|
|
default:
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
static int can_convert_opcode_to_alpha(unsigned int opcode)
|
|
{
|
|
switch(opcode) {
|
|
case RC_OPCODE_DDX:
|
|
case RC_OPCODE_DDY:
|
|
case RC_OPCODE_DP2:
|
|
case RC_OPCODE_DP3:
|
|
case RC_OPCODE_DP4:
|
|
return 0;
|
|
default:
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
static void is_rgb_to_alpha_possible(
|
|
void * userdata,
|
|
struct rc_instruction * inst,
|
|
struct rc_pair_instruction_arg * arg,
|
|
struct rc_pair_instruction_source * src)
|
|
{
|
|
unsigned int read_chan = RC_SWIZZLE_UNUSED;
|
|
unsigned int alpha_sources = 0;
|
|
unsigned int i;
|
|
struct rc_reader_data * reader_data = userdata;
|
|
|
|
if (!can_remap(inst->U.P.RGB.Opcode)
|
|
|| !can_remap(inst->U.P.Alpha.Opcode)) {
|
|
reader_data->Abort = 1;
|
|
return;
|
|
}
|
|
|
|
if (!src)
|
|
return;
|
|
|
|
/* XXX There are some cases where we can still do the conversion if
|
|
* a reader reads from a presubtract source, but for now we'll prevent
|
|
* it. */
|
|
if (arg->Source == RC_PAIR_PRESUB_SRC) {
|
|
reader_data->Abort = 1;
|
|
return;
|
|
}
|
|
|
|
/* Make sure the source only reads the register component that we
|
|
* are going to be convering from. It is OK if the instruction uses
|
|
* this component more than once.
|
|
* XXX If the index we will be converting to is the same as the
|
|
* current index, then it is OK to read from more than one component.
|
|
*/
|
|
for (i = 0; i < 3; i++) {
|
|
rc_swizzle swz = get_swz(arg->Swizzle, i);
|
|
switch(swz) {
|
|
case RC_SWIZZLE_X:
|
|
case RC_SWIZZLE_Y:
|
|
case RC_SWIZZLE_Z:
|
|
case RC_SWIZZLE_W:
|
|
if (read_chan == RC_SWIZZLE_UNUSED) {
|
|
read_chan = swz;
|
|
} else if (read_chan != swz) {
|
|
reader_data->Abort = 1;
|
|
return;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Make sure there are enough alpha sources.
|
|
* XXX If we know what register all the readers are going
|
|
* to be remapped to, then in some situations we can still do
|
|
* the substitution, even if all 3 alpha sources are being used.*/
|
|
for (i = 0; i < 3; i++) {
|
|
if (inst->U.P.Alpha.Src[i].Used) {
|
|
alpha_sources++;
|
|
}
|
|
}
|
|
if (alpha_sources > 2) {
|
|
reader_data->Abort = 1;
|
|
return;
|
|
}
|
|
}
|
|
|
|
static int convert_rgb_to_alpha(
|
|
struct schedule_state * s,
|
|
struct schedule_instruction * sched_inst)
|
|
{
|
|
struct rc_pair_instruction * pair_inst = &sched_inst->Instruction->U.P;
|
|
unsigned int old_mask = pair_inst->RGB.WriteMask;
|
|
unsigned int old_swz = rc_mask_to_swizzle(old_mask);
|
|
const struct rc_opcode_info * info =
|
|
rc_get_opcode_info(pair_inst->RGB.Opcode);
|
|
int new_index = -1;
|
|
unsigned int i;
|
|
|
|
if (sched_inst->GlobalReaders.Abort)
|
|
return 0;
|
|
|
|
if (!pair_inst->RGB.WriteMask)
|
|
return 0;
|
|
|
|
if (!can_convert_opcode_to_alpha(pair_inst->RGB.Opcode)
|
|
|| !can_convert_opcode_to_alpha(pair_inst->Alpha.Opcode)) {
|
|
return 0;
|
|
}
|
|
|
|
assert(sched_inst->NumWriteValues == 1);
|
|
|
|
if (!sched_inst->WriteValues[0]) {
|
|
assert(0);
|
|
return 0;
|
|
}
|
|
|
|
/* We start at the old index, because if we can reuse the same
|
|
* register and just change the swizzle then it is more likely we
|
|
* will be able to convert all the readers. */
|
|
for (i = pair_inst->RGB.DestIndex; i < RC_REGISTER_MAX_INDEX; i++) {
|
|
struct reg_value ** new_regvalp = get_reg_valuep(
|
|
s, RC_FILE_TEMPORARY, i, 3);
|
|
if (!*new_regvalp) {
|
|
struct reg_value ** old_regvalp =
|
|
get_reg_valuep(s,
|
|
RC_FILE_TEMPORARY,
|
|
pair_inst->RGB.DestIndex,
|
|
rc_mask_to_swizzle(old_mask));
|
|
new_index = i;
|
|
*new_regvalp = *old_regvalp;
|
|
*old_regvalp = NULL;
|
|
new_regvalp = get_reg_valuep(s, RC_FILE_TEMPORARY, i, 3);
|
|
break;
|
|
}
|
|
}
|
|
if (new_index < 0) {
|
|
return 0;
|
|
}
|
|
|
|
/* If we are converting a full instruction with RC_OPCODE_REPL_ALPHA
|
|
* as the RGB opcode, then the Alpha instruction will already contain
|
|
* the correct opcode and instruction args, so we do not want to
|
|
* overwrite them.
|
|
*/
|
|
if (pair_inst->RGB.Opcode != RC_OPCODE_REPL_ALPHA) {
|
|
pair_inst->Alpha.Opcode = pair_inst->RGB.Opcode;
|
|
memcpy(pair_inst->Alpha.Arg, pair_inst->RGB.Arg,
|
|
sizeof(pair_inst->Alpha.Arg));
|
|
}
|
|
pair_inst->Alpha.DestIndex = new_index;
|
|
pair_inst->Alpha.WriteMask = RC_MASK_W;
|
|
pair_inst->Alpha.Target = pair_inst->RGB.Target;
|
|
pair_inst->Alpha.OutputWriteMask = pair_inst->RGB.OutputWriteMask;
|
|
pair_inst->Alpha.DepthWriteMask = pair_inst->RGB.DepthWriteMask;
|
|
pair_inst->Alpha.Saturate = pair_inst->RGB.Saturate;
|
|
pair_inst->Alpha.Omod = pair_inst->RGB.Omod;
|
|
/* Move the swizzles into the first chan */
|
|
for (i = 0; i < info->NumSrcRegs; i++) {
|
|
unsigned int j;
|
|
for (j = 0; j < 3; j++) {
|
|
unsigned int swz = get_swz(pair_inst->Alpha.Arg[i].Swizzle, j);
|
|
if (swz != RC_SWIZZLE_UNUSED) {
|
|
pair_inst->Alpha.Arg[i].Swizzle =
|
|
rc_init_swizzle(swz, 1);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
pair_inst->RGB.Opcode = RC_OPCODE_NOP;
|
|
pair_inst->RGB.DestIndex = 0;
|
|
pair_inst->RGB.WriteMask = 0;
|
|
pair_inst->RGB.Target = 0;
|
|
pair_inst->RGB.OutputWriteMask = 0;
|
|
pair_inst->RGB.DepthWriteMask = 0;
|
|
pair_inst->RGB.Saturate = 0;
|
|
memset(pair_inst->RGB.Arg, 0, sizeof(pair_inst->RGB.Arg));
|
|
|
|
for(i = 0; i < sched_inst->GlobalReaders.ReaderCount; i++) {
|
|
struct rc_reader reader = sched_inst->GlobalReaders.Readers[i];
|
|
rgb_to_alpha_remap(reader.Inst, reader.U.P.Arg,
|
|
RC_FILE_TEMPORARY, old_swz, new_index);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static void try_convert_and_pair(
|
|
struct schedule_state *s,
|
|
struct schedule_instruction ** inst_list)
|
|
{
|
|
struct schedule_instruction * list_ptr = *inst_list;
|
|
while (list_ptr && *inst_list && (*inst_list)->NextReady) {
|
|
int paired = 0;
|
|
if (list_ptr->Instruction->U.P.Alpha.Opcode != RC_OPCODE_NOP
|
|
&& list_ptr->Instruction->U.P.RGB.Opcode
|
|
!= RC_OPCODE_REPL_ALPHA) {
|
|
goto next;
|
|
}
|
|
if (list_ptr->NumWriteValues == 1
|
|
&& convert_rgb_to_alpha(s, list_ptr)) {
|
|
|
|
struct schedule_instruction * pair_ptr;
|
|
remove_inst_from_list(inst_list, list_ptr);
|
|
add_inst_to_list_score(&s->ReadyAlpha, list_ptr);
|
|
|
|
for (pair_ptr = s->ReadyRGB; pair_ptr;
|
|
pair_ptr = pair_ptr->NextReady) {
|
|
if (merge_instructions(&pair_ptr->Instruction->U.P,
|
|
&list_ptr->Instruction->U.P)) {
|
|
remove_inst_from_list(&s->ReadyAlpha, list_ptr);
|
|
remove_inst_from_list(&s->ReadyRGB, pair_ptr);
|
|
pair_ptr->PairedInst = list_ptr;
|
|
|
|
add_inst_to_list(&s->ReadyFullALU, pair_ptr);
|
|
list_ptr = *inst_list;
|
|
paired = 1;
|
|
break;
|
|
}
|
|
|
|
}
|
|
}
|
|
if (!paired) {
|
|
next:
|
|
list_ptr = list_ptr->NextReady;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* This function attempts to merge RGB and Alpha instructions together.
|
|
*/
|
|
static void pair_instructions(struct schedule_state * s)
|
|
{
|
|
struct schedule_instruction *rgb_ptr;
|
|
struct schedule_instruction *alpha_ptr;
|
|
|
|
/* Some pairings might fail because they require too
|
|
* many source slots; try all possible pairings if necessary */
|
|
rgb_ptr = s->ReadyRGB;
|
|
while(rgb_ptr) {
|
|
struct schedule_instruction * rgb_next = rgb_ptr->NextReady;
|
|
alpha_ptr = s->ReadyAlpha;
|
|
while(alpha_ptr) {
|
|
struct schedule_instruction * alpha_next = alpha_ptr->NextReady;
|
|
if (merge_instructions(&rgb_ptr->Instruction->U.P, &alpha_ptr->Instruction->U.P)) {
|
|
/* Remove RGB and Alpha from their ready lists.
|
|
*/
|
|
remove_inst_from_list(&s->ReadyRGB, rgb_ptr);
|
|
remove_inst_from_list(&s->ReadyAlpha, alpha_ptr);
|
|
rgb_ptr->PairedInst = alpha_ptr;
|
|
add_inst_to_list(&s->ReadyFullALU, rgb_ptr);
|
|
break;
|
|
}
|
|
alpha_ptr = alpha_next;
|
|
}
|
|
rgb_ptr = rgb_next;
|
|
}
|
|
|
|
if (!s->Opt) {
|
|
return;
|
|
}
|
|
|
|
/* Full instructions that have RC_OPCODE_REPL_ALPHA in the RGB
|
|
* slot can be converted into Alpha instructions. */
|
|
try_convert_and_pair(s, &s->ReadyFullALU);
|
|
|
|
/* Try to convert some of the RGB instructions to Alpha and
|
|
* try to pair it with another RGB. */
|
|
try_convert_and_pair(s, &s->ReadyRGB);
|
|
}
|
|
|
|
static void update_max_score(
|
|
struct schedule_state * s,
|
|
struct schedule_instruction ** list,
|
|
int * max_score,
|
|
struct schedule_instruction ** max_inst_out,
|
|
struct schedule_instruction *** list_out)
|
|
{
|
|
struct schedule_instruction * list_ptr;
|
|
for (list_ptr = *list; list_ptr; list_ptr = list_ptr->NextReady) {
|
|
int score;
|
|
s->CalcScore(list_ptr);
|
|
score = list_ptr->Score;
|
|
if (!*max_inst_out || score > *max_score) {
|
|
*max_score = score;
|
|
*max_inst_out = list_ptr;
|
|
*list_out = list;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void emit_instruction(
|
|
struct schedule_state * s,
|
|
struct rc_instruction * before)
|
|
{
|
|
int max_score = -1;
|
|
struct schedule_instruction * max_inst = NULL;
|
|
struct schedule_instruction ** max_list = NULL;
|
|
unsigned tex_count = 0;
|
|
struct schedule_instruction * tex_ptr;
|
|
|
|
pair_instructions(s);
|
|
#if VERBOSE
|
|
fprintf(stderr, "Full:\n");
|
|
print_list(s->ReadyFullALU);
|
|
fprintf(stderr, "RGB:\n");
|
|
print_list(s->ReadyRGB);
|
|
fprintf(stderr, "Alpha:\n");
|
|
print_list(s->ReadyAlpha);
|
|
fprintf(stderr, "TEX:\n");
|
|
print_list(s->ReadyTEX);
|
|
#endif
|
|
|
|
for (tex_ptr = s->ReadyTEX; tex_ptr; tex_ptr = tex_ptr->NextReady) {
|
|
if (tex_ptr->Instruction->U.I.Opcode == RC_OPCODE_KIL) {
|
|
emit_all_tex(s, before);
|
|
return;
|
|
}
|
|
tex_count++;
|
|
}
|
|
update_max_score(s, &s->ReadyFullALU, &max_score, &max_inst, &max_list);
|
|
update_max_score(s, &s->ReadyRGB, &max_score, &max_inst, &max_list);
|
|
update_max_score(s, &s->ReadyAlpha, &max_score, &max_inst, &max_list);
|
|
|
|
if (tex_count >= s->max_tex_group || max_score == -1
|
|
|| (s->TEXCount > 0 && tex_count == s->TEXCount)
|
|
|| (!s->C->is_r500 && tex_count > 0 && max_score == -1)) {
|
|
emit_all_tex(s, before);
|
|
} else {
|
|
|
|
|
|
remove_inst_from_list(max_list, max_inst);
|
|
rc_insert_instruction(before->Prev, max_inst->Instruction);
|
|
commit_alu_instruction(s, max_inst);
|
|
|
|
presub_nop(before->Prev);
|
|
}
|
|
}
|
|
|
|
static void add_tex_reader(
|
|
struct schedule_state * s,
|
|
struct schedule_instruction * writer,
|
|
struct schedule_instruction * reader)
|
|
{
|
|
if (!writer || writer->Instruction->Type != RC_INSTRUCTION_NORMAL) {
|
|
/*Not a TEX instructions */
|
|
return;
|
|
}
|
|
reader->TexReadCount++;
|
|
rc_list_add(&writer->TexReaders, rc_list(&s->C->Pool, reader));
|
|
}
|
|
|
|
static void scan_read(void * data, struct rc_instruction * inst,
|
|
rc_register_file file, unsigned int index, unsigned int chan)
|
|
{
|
|
struct schedule_state * s = data;
|
|
struct reg_value ** v = get_reg_valuep(s, file, index, chan);
|
|
struct reg_value_reader * reader;
|
|
|
|
if (!v)
|
|
return;
|
|
|
|
if (*v && (*v)->Writer == s->Current) {
|
|
/* The instruction reads and writes to a register component.
|
|
* In this case, we only want to increment dependencies by one.
|
|
* Why?
|
|
* Because each instruction depends on the writers of its source
|
|
* registers _and_ the most recent writer of its destination
|
|
* register. In this case, the current instruction (s->Current)
|
|
* has a dependency that both writes to one of its source
|
|
* registers and was the most recent writer to its destination
|
|
* register. We have already marked this dependency in
|
|
* scan_write(), so we don't need to do it again.
|
|
*/
|
|
|
|
/* We need to make sure we are adding s->Current to the
|
|
* previous writer's list of TexReaders, if the previous writer
|
|
* was a TEX instruction.
|
|
*/
|
|
add_tex_reader(s, s->PrevWriter[chan], s->Current);
|
|
|
|
return;
|
|
}
|
|
|
|
DBG("%i: read %i[%i] chan %i\n", s->Current->Instruction->IP, file, index, chan);
|
|
|
|
reader = memory_pool_malloc(&s->C->Pool, sizeof(*reader));
|
|
reader->Reader = s->Current;
|
|
if (!*v) {
|
|
/* In this situation, the instruction reads from a register
|
|
* that hasn't been written to or read from in the current
|
|
* block. */
|
|
*v = memory_pool_malloc(&s->C->Pool, sizeof(struct reg_value));
|
|
memset(*v, 0, sizeof(struct reg_value));
|
|
(*v)->Readers = reader;
|
|
} else {
|
|
reader->Next = (*v)->Readers;
|
|
(*v)->Readers = reader;
|
|
/* Only update the current instruction's dependencies if the
|
|
* register it reads from has been written to in this block. */
|
|
if ((*v)->Writer) {
|
|
add_tex_reader(s, (*v)->Writer, s->Current);
|
|
s->Current->NumDependencies++;
|
|
}
|
|
}
|
|
(*v)->NumReaders++;
|
|
|
|
if (s->Current->NumReadValues >= 12) {
|
|
rc_error(s->C, "%s: NumReadValues overflow\n", __FUNCTION__);
|
|
} else {
|
|
s->Current->ReadValues[s->Current->NumReadValues++] = *v;
|
|
}
|
|
}
|
|
|
|
static void scan_write(void * data, struct rc_instruction * inst,
|
|
rc_register_file file, unsigned int index, unsigned int chan)
|
|
{
|
|
struct schedule_state * s = data;
|
|
struct reg_value ** pv = get_reg_valuep(s, file, index, chan);
|
|
struct reg_value * newv;
|
|
|
|
if (!pv)
|
|
return;
|
|
|
|
DBG("%i: write %i[%i] chan %i\n", s->Current->Instruction->IP, file, index, chan);
|
|
|
|
newv = memory_pool_malloc(&s->C->Pool, sizeof(*newv));
|
|
memset(newv, 0, sizeof(*newv));
|
|
|
|
newv->Writer = s->Current;
|
|
|
|
if (*pv) {
|
|
(*pv)->Next = newv;
|
|
s->Current->NumDependencies++;
|
|
/* Keep track of the previous writer to s->Current's destination
|
|
* register */
|
|
s->PrevWriter[chan] = (*pv)->Writer;
|
|
}
|
|
|
|
*pv = newv;
|
|
|
|
if (s->Current->NumWriteValues >= 4) {
|
|
rc_error(s->C, "%s: NumWriteValues overflow\n", __FUNCTION__);
|
|
} else {
|
|
s->Current->WriteValues[s->Current->NumWriteValues++] = newv;
|
|
}
|
|
}
|
|
|
|
static void is_rgb_to_alpha_possible_normal(
|
|
void * userdata,
|
|
struct rc_instruction * inst,
|
|
struct rc_src_register * src)
|
|
{
|
|
struct rc_reader_data * reader_data = userdata;
|
|
reader_data->Abort = 1;
|
|
|
|
}
|
|
|
|
static void schedule_block(struct schedule_state * s,
|
|
struct rc_instruction * begin, struct rc_instruction * end)
|
|
{
|
|
unsigned int ip;
|
|
|
|
/* Scan instructions for data dependencies */
|
|
ip = 0;
|
|
for(struct rc_instruction * inst = begin; inst != end; inst = inst->Next) {
|
|
s->Current = memory_pool_malloc(&s->C->Pool, sizeof(*s->Current));
|
|
memset(s->Current, 0, sizeof(struct schedule_instruction));
|
|
|
|
if (inst->Type == RC_INSTRUCTION_NORMAL) {
|
|
const struct rc_opcode_info * info =
|
|
rc_get_opcode_info(inst->U.I.Opcode);
|
|
if (info->HasTexture) {
|
|
s->TEXCount++;
|
|
}
|
|
}
|
|
|
|
/* XXX: This causes SemWait to be set for all instructions in
|
|
* a block if the previous block contained a TEX instruction.
|
|
* We can do better here, but it will take a lot of work. */
|
|
if (s->PrevBlockHasTex) {
|
|
s->Current->TexReadCount = 1;
|
|
}
|
|
|
|
s->Current->Instruction = inst;
|
|
inst->IP = ip++;
|
|
|
|
DBG("%i: Scanning\n", inst->IP);
|
|
|
|
/* The order of things here is subtle and maybe slightly
|
|
* counter-intuitive, to account for the case where an
|
|
* instruction writes to the same register as it reads
|
|
* from. */
|
|
rc_for_all_writes_chan(inst, &scan_write, s);
|
|
rc_for_all_reads_chan(inst, &scan_read, s);
|
|
|
|
DBG("%i: Has %i dependencies\n", inst->IP, s->Current->NumDependencies);
|
|
|
|
if (!s->Current->NumDependencies) {
|
|
instruction_ready(s, s->Current);
|
|
}
|
|
|
|
/* Get global readers for possible RGB->Alpha conversion. */
|
|
s->Current->GlobalReaders.ExitOnAbort = 1;
|
|
rc_get_readers(s->C, inst, &s->Current->GlobalReaders,
|
|
is_rgb_to_alpha_possible_normal,
|
|
is_rgb_to_alpha_possible, NULL);
|
|
}
|
|
|
|
/* Temporarily unlink all instructions */
|
|
begin->Prev->Next = end;
|
|
end->Prev = begin->Prev;
|
|
|
|
/* Schedule instructions back */
|
|
while(!s->C->Error &&
|
|
(s->ReadyTEX || s->ReadyRGB || s->ReadyAlpha || s->ReadyFullALU)) {
|
|
emit_instruction(s, end);
|
|
}
|
|
}
|
|
|
|
static int is_controlflow(struct rc_instruction * inst)
|
|
{
|
|
if (inst->Type == RC_INSTRUCTION_NORMAL) {
|
|
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
|
|
return opcode->IsFlowControl;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void rc_pair_schedule(struct radeon_compiler *cc, void *user)
|
|
{
|
|
struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc;
|
|
struct schedule_state s;
|
|
struct rc_instruction * inst = c->Base.Program.Instructions.Next;
|
|
unsigned int * opt = user;
|
|
|
|
memset(&s, 0, sizeof(s));
|
|
s.Opt = *opt;
|
|
s.C = &c->Base;
|
|
if (s.C->is_r500) {
|
|
s.CalcScore = calc_score_readers;
|
|
} else {
|
|
s.CalcScore = calc_score_r300;
|
|
}
|
|
s.max_tex_group = debug_get_num_option("RADEON_TEX_GROUP", 8);
|
|
while(inst != &c->Base.Program.Instructions) {
|
|
struct rc_instruction * first;
|
|
|
|
if (is_controlflow(inst)) {
|
|
inst = inst->Next;
|
|
continue;
|
|
}
|
|
|
|
first = inst;
|
|
|
|
while(inst != &c->Base.Program.Instructions && !is_controlflow(inst))
|
|
inst = inst->Next;
|
|
|
|
DBG("Schedule one block\n");
|
|
memset(s.Temporary, 0, sizeof(s.Temporary));
|
|
s.TEXCount = 0;
|
|
schedule_block(&s, first, inst);
|
|
if (s.PendingTEX) {
|
|
s.PrevBlockHasTex = 1;
|
|
}
|
|
}
|
|
}
|