401 lines
12 KiB
C
401 lines
12 KiB
C
#include "pipe/p_defines.h"
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#include "pipe/p_screen.h"
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#include "pipe/p_state.h"
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#include "util/u_memory.h"
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#include "util/u_inlines.h"
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#include "util/format/u_format.h"
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#include "util/format/u_format_s3tc.h"
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#include "util/u_string.h"
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#include "os/os_mman.h"
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#include "util/os_time.h"
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#include <stdio.h>
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#include <errno.h>
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#include <stdlib.h>
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#include <nouveau_drm.h>
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#include <xf86drm.h>
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#include "nouveau_winsys.h"
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#include "nouveau_screen.h"
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#include "nouveau_context.h"
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#include "nouveau_fence.h"
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#include "nouveau_mm.h"
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#include "nouveau_buffer.h"
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#include <compiler/glsl_types.h>
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/* XXX this should go away */
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#include "frontend/drm_driver.h"
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/* Even though GPUs might allow addresses with more bits, some engines do not.
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* Stick with 40 for compatibility.
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*/
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#define NV_GENERIC_VM_LIMIT_SHIFT 39
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int nouveau_mesa_debug = 0;
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static const char *
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nouveau_screen_get_name(struct pipe_screen *pscreen)
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{
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struct nouveau_screen *screen = nouveau_screen(pscreen);
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return screen->chipset_name;
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}
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static const char *
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nouveau_screen_get_vendor(struct pipe_screen *pscreen)
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{
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return "nouveau";
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}
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static const char *
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nouveau_screen_get_device_vendor(struct pipe_screen *pscreen)
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{
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return "NVIDIA";
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}
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static uint64_t
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nouveau_screen_get_timestamp(struct pipe_screen *pscreen)
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{
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int64_t cpu_time = os_time_get() * 1000;
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/* getparam of PTIMER_TIME takes about x10 as long (several usecs) */
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return cpu_time + nouveau_screen(pscreen)->cpu_gpu_time_delta;
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}
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static struct disk_cache *
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nouveau_screen_get_disk_shader_cache(struct pipe_screen *pscreen)
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{
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return nouveau_screen(pscreen)->disk_shader_cache;
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}
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static void
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nouveau_screen_fence_ref(struct pipe_screen *pscreen,
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struct pipe_fence_handle **ptr,
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struct pipe_fence_handle *pfence)
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{
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nouveau_fence_ref(nouveau_fence(pfence), (struct nouveau_fence **)ptr);
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}
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static bool
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nouveau_screen_fence_finish(struct pipe_screen *screen,
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struct pipe_context *ctx,
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struct pipe_fence_handle *pfence,
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uint64_t timeout)
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{
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if (!timeout)
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return nouveau_fence_signalled(nouveau_fence(pfence));
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return nouveau_fence_wait(nouveau_fence(pfence), NULL);
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}
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struct nouveau_bo *
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nouveau_screen_bo_from_handle(struct pipe_screen *pscreen,
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struct winsys_handle *whandle,
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unsigned *out_stride)
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{
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struct nouveau_device *dev = nouveau_screen(pscreen)->device;
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struct nouveau_bo *bo = NULL;
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int ret;
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if (whandle->offset != 0) {
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debug_printf("%s: attempt to import unsupported winsys offset %d\n",
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__FUNCTION__, whandle->offset);
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return NULL;
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}
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if (whandle->type != WINSYS_HANDLE_TYPE_SHARED &&
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whandle->type != WINSYS_HANDLE_TYPE_FD) {
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debug_printf("%s: attempt to import unsupported handle type %d\n",
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__FUNCTION__, whandle->type);
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return NULL;
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}
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if (whandle->type == WINSYS_HANDLE_TYPE_SHARED)
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ret = nouveau_bo_name_ref(dev, whandle->handle, &bo);
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else
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ret = nouveau_bo_prime_handle_ref(dev, whandle->handle, &bo);
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if (ret) {
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debug_printf("%s: ref name 0x%08x failed with %d\n",
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__FUNCTION__, whandle->handle, ret);
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return NULL;
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}
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*out_stride = whandle->stride;
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return bo;
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}
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bool
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nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
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struct nouveau_bo *bo,
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unsigned stride,
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struct winsys_handle *whandle)
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{
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whandle->stride = stride;
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if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
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return nouveau_bo_name_get(bo, &whandle->handle) == 0;
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} else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
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whandle->handle = bo->handle;
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return true;
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} else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
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return nouveau_bo_set_prime(bo, (int *)&whandle->handle) == 0;
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} else {
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return false;
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}
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}
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static void
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nouveau_disk_cache_create(struct nouveau_screen *screen)
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{
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struct mesa_sha1 ctx;
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unsigned char sha1[20];
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char cache_id[20 * 2 + 1];
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uint64_t driver_flags = 0;
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_mesa_sha1_init(&ctx);
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if (!disk_cache_get_function_identifier(nouveau_disk_cache_create,
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&ctx))
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return;
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_mesa_sha1_final(&ctx, sha1);
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disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
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if (screen->prefer_nir)
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driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_NIR;
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else
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driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_TGSI;
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screen->disk_shader_cache =
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disk_cache_create(nouveau_screen_get_name(&screen->base),
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cache_id, driver_flags);
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}
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static void*
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reserve_vma(uintptr_t start, uint64_t reserved_size)
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{
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void *reserved = os_mmap((void*)start, reserved_size, PROT_NONE,
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MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
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if (reserved == MAP_FAILED)
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return NULL;
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return reserved;
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}
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int
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nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev)
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{
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struct pipe_screen *pscreen = &screen->base;
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struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 };
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struct nvc0_fifo nvc0_data = { };
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uint64_t time;
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int size, ret;
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void *data;
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union nouveau_bo_config mm_config;
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char *nv_dbg = getenv("NOUVEAU_MESA_DEBUG");
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if (nv_dbg)
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nouveau_mesa_debug = atoi(nv_dbg);
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if (dev->chipset < 0x140)
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screen->prefer_nir = debug_get_bool_option("NV50_PROG_USE_NIR", false);
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else
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screen->prefer_nir = true;
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screen->force_enable_cl = debug_get_bool_option("NOUVEAU_ENABLE_CL", false);
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if (screen->force_enable_cl)
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glsl_type_singleton_init_or_ref();
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/* These must be set before any failure is possible, as the cleanup
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* paths assume they're responsible for deleting them.
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*/
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screen->drm = nouveau_drm(&dev->object);
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screen->device = dev;
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/*
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* this is initialized to 1 in nouveau_drm_screen_create after screen
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* is fully constructed and added to the global screen list.
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*/
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screen->refcount = -1;
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if (dev->chipset < 0xc0) {
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data = &nv04_data;
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size = sizeof(nv04_data);
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} else {
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data = &nvc0_data;
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size = sizeof(nvc0_data);
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}
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bool enable_svm = debug_get_bool_option("NOUVEAU_SVM", false);
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screen->has_svm = false;
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/* we only care about HMM with OpenCL enabled */
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if (dev->chipset > 0x130 && screen->force_enable_cl && enable_svm) {
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/* Before being able to enable SVM we need to carve out some memory for
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* driver bo allocations. Let's just base the size on the available VRAM.
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*
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* 40 bit is the biggest we care about and for 32 bit systems we don't
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* want to allocate all of the available memory either.
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*
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* Also we align the size we want to reserve to the next POT to make use
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* of hugepages.
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*/
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const int vram_shift = util_logbase2_ceil64(dev->vram_size);
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const int limit_bit =
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MIN2(sizeof(void*) * 8 - 1, NV_GENERIC_VM_LIMIT_SHIFT);
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screen->svm_cutout_size =
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BITFIELD64_BIT(MIN2(sizeof(void*) == 4 ? 26 : NV_GENERIC_VM_LIMIT_SHIFT, vram_shift));
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size_t start = screen->svm_cutout_size;
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do {
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screen->svm_cutout = reserve_vma(start, screen->svm_cutout_size);
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if (!screen->svm_cutout) {
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start += screen->svm_cutout_size;
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continue;
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}
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struct drm_nouveau_svm_init svm_args = {
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.unmanaged_addr = (uintptr_t)screen->svm_cutout,
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.unmanaged_size = screen->svm_cutout_size,
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};
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ret = drmCommandWrite(screen->drm->fd, DRM_NOUVEAU_SVM_INIT,
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&svm_args, sizeof(svm_args));
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screen->has_svm = !ret;
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if (!screen->has_svm)
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os_munmap(screen->svm_cutout, screen->svm_cutout_size);
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break;
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} while ((start + screen->svm_cutout_size) < BITFIELD64_MASK(limit_bit));
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}
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switch (dev->chipset) {
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case 0x0ea: /* TK1, GK20A */
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case 0x12b: /* TX1, GM20B */
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case 0x13b: /* TX2, GP10B */
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screen->tegra_sector_layout = true;
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break;
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default:
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/* Xavier's GPU and everything else */
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screen->tegra_sector_layout = false;
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break;
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}
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/*
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* Set default VRAM domain if not overridden
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*/
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if (!screen->vram_domain) {
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if (dev->vram_size > 0)
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screen->vram_domain = NOUVEAU_BO_VRAM;
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else
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screen->vram_domain = NOUVEAU_BO_GART;
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}
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ret = nouveau_object_new(&dev->object, 0, NOUVEAU_FIFO_CHANNEL_CLASS,
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data, size, &screen->channel);
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if (ret)
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goto err;
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ret = nouveau_client_new(screen->device, &screen->client);
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if (ret)
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goto err;
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ret = nouveau_pushbuf_new(screen->client, screen->channel,
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4, 512 * 1024, 1,
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&screen->pushbuf);
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if (ret)
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goto err;
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/* getting CPU time first appears to be more accurate */
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screen->cpu_gpu_time_delta = os_time_get();
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ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_PTIMER_TIME, &time);
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if (!ret)
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screen->cpu_gpu_time_delta = time - screen->cpu_gpu_time_delta * 1000;
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snprintf(screen->chipset_name, sizeof(screen->chipset_name), "NV%02X", dev->chipset);
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pscreen->get_name = nouveau_screen_get_name;
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pscreen->get_vendor = nouveau_screen_get_vendor;
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pscreen->get_device_vendor = nouveau_screen_get_device_vendor;
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pscreen->get_disk_shader_cache = nouveau_screen_get_disk_shader_cache;
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pscreen->get_timestamp = nouveau_screen_get_timestamp;
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pscreen->fence_reference = nouveau_screen_fence_ref;
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pscreen->fence_finish = nouveau_screen_fence_finish;
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nouveau_disk_cache_create(screen);
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screen->transfer_pushbuf_threshold = 192;
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screen->lowmem_bindings = PIPE_BIND_GLOBAL; /* gallium limit */
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screen->vidmem_bindings =
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PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL |
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PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
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PIPE_BIND_CURSOR |
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PIPE_BIND_SAMPLER_VIEW |
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PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE |
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PIPE_BIND_COMPUTE_RESOURCE |
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PIPE_BIND_GLOBAL;
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screen->sysmem_bindings =
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PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_STREAM_OUTPUT |
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PIPE_BIND_COMMAND_ARGS_BUFFER;
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memset(&mm_config, 0, sizeof(mm_config));
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screen->mm_GART = nouveau_mm_create(dev,
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NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
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&mm_config);
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screen->mm_VRAM = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
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return 0;
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err:
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if (screen->svm_cutout)
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os_munmap(screen->svm_cutout, screen->svm_cutout_size);
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return ret;
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}
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void
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nouveau_screen_fini(struct nouveau_screen *screen)
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{
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int fd = screen->drm->fd;
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if (screen->force_enable_cl)
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glsl_type_singleton_decref();
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if (screen->has_svm)
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os_munmap(screen->svm_cutout, screen->svm_cutout_size);
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nouveau_mm_destroy(screen->mm_GART);
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nouveau_mm_destroy(screen->mm_VRAM);
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nouveau_pushbuf_del(&screen->pushbuf);
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nouveau_client_del(&screen->client);
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nouveau_object_del(&screen->channel);
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nouveau_device_del(&screen->device);
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nouveau_drm_del(&screen->drm);
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close(fd);
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disk_cache_destroy(screen->disk_shader_cache);
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}
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static void
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nouveau_set_debug_callback(struct pipe_context *pipe,
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const struct pipe_debug_callback *cb)
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{
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struct nouveau_context *context = nouveau_context(pipe);
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if (cb)
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context->debug = *cb;
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else
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memset(&context->debug, 0, sizeof(context->debug));
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}
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void
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nouveau_context_init(struct nouveau_context *context)
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{
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context->pipe.set_debug_callback = nouveau_set_debug_callback;
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}
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