929 lines
36 KiB
C
929 lines
36 KiB
C
/*
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* Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Gareth Hughes <gareth@valinux.com>
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* Keith Whitwell <keithw@vmware.com>
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*/
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#include "main/errors.h"
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#include "main/glheader.h"
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#include "main/api_arrayelt.h"
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#include "swrast/swrast.h"
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#include "vbo/vbo.h"
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#include "tnl/t_pipeline.h"
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#include "swrast_setup/swrast_setup.h"
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#include "radeon_context.h"
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#include "radeon_mipmap_tree.h"
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#include "radeon_ioctl.h"
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#include "radeon_state.h"
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#include "radeon_queryobj.h"
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#include "../r200/r200_reg.h"
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#include "util/driconf.h"
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/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
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* 1.3 cmdbuffers allow all previous state to be updated as well as
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* the tcl scalar and vector areas.
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*/
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static struct {
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int start;
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int len;
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const char *name;
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} packet[RADEON_MAX_STATE_PACKETS] = {
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{RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
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{RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
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{RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
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{RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
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{RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
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{RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
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{RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
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{RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
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{RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
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{RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
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{RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
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{RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
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{RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
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{RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
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{RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
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{RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
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{RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
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{RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
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{RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
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{RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
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{RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
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"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
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{R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
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{R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
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{R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
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{R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
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{R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
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{R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
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{R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
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{R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
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{R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
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{R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
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{R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
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{R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
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{R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
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{R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
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{R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
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{R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
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{R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
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{R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
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{R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
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{R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
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{R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
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{R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
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{R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
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{R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
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{R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
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{R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
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{R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
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{R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
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{R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
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"R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
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{R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
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{R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
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{R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
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{R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
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{R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
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{R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
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{R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
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{R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
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{R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
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{R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
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{R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
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"R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
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{R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
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{R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
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{R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
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{R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
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{R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
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{R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
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{R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
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{R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
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{R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
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{R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
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{R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
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{R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
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{RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
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{RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
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{RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
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{R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
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{R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
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{RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
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{RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
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{RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
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{RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
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{RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
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{RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
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{R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
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{R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
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{R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
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{R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
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{R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
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{R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
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{R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
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{R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
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{R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
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{R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
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{R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
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};
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/* =============================================================
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* State initialization
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*/
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static int cmdpkt( r100ContextPtr rmesa, int id )
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{
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return CP_PACKET0(packet[id].start, packet[id].len - 1);
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}
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static int cmdvec( int offset, int stride, int count )
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{
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drm_radeon_cmd_header_t h;
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h.i = 0;
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h.vectors.cmd_type = RADEON_CMD_VECTORS;
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h.vectors.offset = offset;
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h.vectors.stride = stride;
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h.vectors.count = count;
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return h.i;
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}
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static int cmdscl( int offset, int stride, int count )
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{
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drm_radeon_cmd_header_t h;
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h.i = 0;
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h.scalars.cmd_type = RADEON_CMD_SCALARS;
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h.scalars.offset = offset;
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h.scalars.stride = stride;
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h.scalars.count = count;
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return h.i;
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}
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#define CHECK( NM, FLAG, ADD ) \
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static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \
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{ \
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return FLAG ? atom->cmd_size + (ADD) : 0; \
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}
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#define TCL_CHECK( NM, FLAG, ADD ) \
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static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \
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{ \
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r100ContextPtr rmesa = R100_CONTEXT(ctx); \
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return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
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}
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CHECK( always, GL_TRUE, 0 )
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CHECK( always_add2, GL_TRUE, 2 )
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CHECK( always_add4, GL_TRUE, 4 )
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CHECK( tex0_mm, GL_TRUE, 3 )
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CHECK( tex1_mm, GL_TRUE, 3 )
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/* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
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CHECK( tex2_mm, GL_TRUE, 3 )
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CHECK( cube0_mm, (ctx->Texture.Unit[0]._Current && ctx->Texture.Unit[0]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE )
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CHECK( cube1_mm, (ctx->Texture.Unit[1]._Current && ctx->Texture.Unit[1]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE )
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CHECK( cube2_mm, (ctx->Texture.Unit[2]._Current && ctx->Texture.Unit[2]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE )
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CHECK( fog_add4, ctx->Fog.Enabled, 4 )
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TCL_CHECK( tcl_add4, GL_TRUE, 4 )
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TCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._Current, 4 )
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TCL_CHECK( tcl_tex1_add4, ctx->Texture.Unit[1]._Current, 4 )
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TCL_CHECK( tcl_tex2_add4, ctx->Texture.Unit[2]._Current, 4 )
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TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 )
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TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 )
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TCL_CHECK( tcl_eyespace_or_lighting_add4, ctx->_NeedEyeCoords || ctx->Light.Enabled, 4 )
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TCL_CHECK( tcl_lit0_add6, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 6 )
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TCL_CHECK( tcl_lit1_add6, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 6 )
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TCL_CHECK( tcl_lit2_add6, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 6 )
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TCL_CHECK( tcl_lit3_add6, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 6 )
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TCL_CHECK( tcl_lit4_add6, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 6 )
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TCL_CHECK( tcl_lit5_add6, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 6 )
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TCL_CHECK( tcl_lit6_add6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 6 )
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TCL_CHECK( tcl_lit7_add6, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 6 )
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TCL_CHECK( tcl_ucp0_add4, (ctx->Transform.ClipPlanesEnabled & 0x1), 4 )
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TCL_CHECK( tcl_ucp1_add4, (ctx->Transform.ClipPlanesEnabled & 0x2), 4 )
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TCL_CHECK( tcl_ucp2_add4, (ctx->Transform.ClipPlanesEnabled & 0x4), 4 )
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TCL_CHECK( tcl_ucp3_add4, (ctx->Transform.ClipPlanesEnabled & 0x8), 4 )
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TCL_CHECK( tcl_ucp4_add4, (ctx->Transform.ClipPlanesEnabled & 0x10), 4 )
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TCL_CHECK( tcl_ucp5_add4, (ctx->Transform.ClipPlanesEnabled & 0x20), 4 )
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TCL_CHECK( tcl_eyespace_or_fog_add4, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 4 )
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CHECK( txr0, (ctx->Texture.Unit[0]._Current && ctx->Texture.Unit[0]._Current->Target == GL_TEXTURE_RECTANGLE), 0 )
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CHECK( txr1, (ctx->Texture.Unit[1]._Current && ctx->Texture.Unit[1]._Current->Target == GL_TEXTURE_RECTANGLE), 0 )
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CHECK( txr2, (ctx->Texture.Unit[2]._Current && ctx->Texture.Unit[2]._Current->Target == GL_TEXTURE_RECTANGLE), 0 )
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#define OUT_VEC(hdr, data) do { \
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drm_radeon_cmd_header_t h; \
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h.i = hdr; \
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OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
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OUT_BATCH(0); \
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OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
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OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
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OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
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OUT_BATCH_TABLE((data), h.vectors.count); \
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} while(0)
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#define OUT_SCL(hdr, data) do { \
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drm_radeon_cmd_header_t h; \
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h.i = hdr; \
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OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
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OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
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OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
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OUT_BATCH_TABLE((data), h.scalars.count); \
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} while(0)
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static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
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{
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r100ContextPtr r100 = R100_CONTEXT(ctx);
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BATCH_LOCALS(&r100->radeon);
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uint32_t dwords = atom->check(ctx, atom);
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BEGIN_BATCH(dwords);
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OUT_SCL(atom->cmd[0], atom->cmd+1);
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END_BATCH();
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}
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static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
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{
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r100ContextPtr r100 = R100_CONTEXT(ctx);
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BATCH_LOCALS(&r100->radeon);
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uint32_t dwords = atom->check(ctx, atom);
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BEGIN_BATCH(dwords);
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OUT_VEC(atom->cmd[0], atom->cmd+1);
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END_BATCH();
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}
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static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
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{
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r100ContextPtr r100 = R100_CONTEXT(ctx);
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BATCH_LOCALS(&r100->radeon);
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uint32_t dwords = atom->check(ctx, atom);
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BEGIN_BATCH(dwords);
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OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
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OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
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END_BATCH();
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}
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static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom)
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{
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r100ContextPtr r100 = R100_CONTEXT(ctx);
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struct radeon_renderbuffer *rrb, *drb;
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uint32_t dwords;
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rrb = radeon_get_colorbuffer(&r100->radeon);
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if (!rrb || !rrb->bo) {
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return 0;
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}
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drb = radeon_get_depthbuffer(&r100->radeon);
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dwords = 10;
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if (drb)
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dwords += 6;
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if (rrb)
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dwords += 8;
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return dwords;
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}
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static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
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{
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r100ContextPtr r100 = R100_CONTEXT(ctx);
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BATCH_LOCALS(&r100->radeon);
|
|
struct radeon_renderbuffer *rrb, *drb;
|
|
uint32_t cbpitch = 0;
|
|
uint32_t zbpitch = 0;
|
|
uint32_t dwords = atom->check(ctx, atom);
|
|
uint32_t depth_fmt;
|
|
|
|
rrb = radeon_get_colorbuffer(&r100->radeon);
|
|
if (!rrb || !rrb->bo) {
|
|
fprintf(stderr, "no rrb\n");
|
|
return;
|
|
}
|
|
|
|
atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
|
|
if (rrb->cpp == 4)
|
|
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
|
|
else switch (rrb->base.Base.Format) {
|
|
case MESA_FORMAT_B5G6R5_UNORM:
|
|
case MESA_FORMAT_R5G6B5_UNORM:
|
|
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
|
|
break;
|
|
case MESA_FORMAT_B4G4R4A4_UNORM:
|
|
case MESA_FORMAT_A4R4G4B4_UNORM:
|
|
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
|
|
break;
|
|
case MESA_FORMAT_B5G5R5A1_UNORM:
|
|
case MESA_FORMAT_A1R5G5B5_UNORM:
|
|
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
|
|
break;
|
|
default:
|
|
_mesa_problem(ctx, "unexpected format in ctx_emit_cs()");
|
|
}
|
|
|
|
cbpitch = (rrb->pitch / rrb->cpp);
|
|
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
|
|
cbpitch |= R200_COLOR_TILE_ENABLE;
|
|
if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
|
|
cbpitch |= RADEON_COLOR_MICROTILE_ENABLE;
|
|
|
|
drb = radeon_get_depthbuffer(&r100->radeon);
|
|
if (drb) {
|
|
zbpitch = (drb->pitch / drb->cpp);
|
|
if (drb->cpp == 4)
|
|
depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
|
|
else
|
|
depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
|
|
atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
|
|
atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
|
|
|
|
}
|
|
|
|
BEGIN_BATCH(dwords);
|
|
|
|
/* In the CS case we need to split this up */
|
|
OUT_BATCH(CP_PACKET0(packet[0].start, 3));
|
|
OUT_BATCH_TABLE((atom->cmd + 1), 4);
|
|
|
|
if (drb) {
|
|
OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
|
|
OUT_BATCH_RELOC(drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
|
|
|
|
OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
|
|
OUT_BATCH(zbpitch);
|
|
}
|
|
|
|
OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
|
|
OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
|
|
OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
|
|
OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
|
|
OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
|
|
|
|
if (rrb) {
|
|
OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
|
|
OUT_BATCH_RELOC(rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
|
|
|
|
OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
|
|
OUT_BATCH_RELOC(rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
|
|
}
|
|
|
|
// if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
|
|
// OUT_BATCH_TABLE((atom->cmd + 14), 4);
|
|
// }
|
|
|
|
END_BATCH();
|
|
BEGIN_BATCH(4);
|
|
OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
|
|
if (rrb) {
|
|
OUT_BATCH(((rrb->base.Base.Width - 1) << RADEON_RE_WIDTH_SHIFT) |
|
|
((rrb->base.Base.Height - 1) << RADEON_RE_HEIGHT_SHIFT));
|
|
} else {
|
|
OUT_BATCH(0);
|
|
}
|
|
END_BATCH();
|
|
}
|
|
|
|
static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
|
|
{
|
|
r100ContextPtr r100 = R100_CONTEXT(ctx);
|
|
BATCH_LOCALS(&r100->radeon);
|
|
uint32_t dwords = atom->check(ctx, atom);
|
|
int i = atom->idx, j;
|
|
radeonTexObj *t = r100->state.texture.unit[i].texobj;
|
|
radeon_mipmap_level *lvl;
|
|
uint32_t base_reg;
|
|
|
|
if (!ctx->Texture.Unit[i]._Current ||
|
|
ctx->Texture.Unit[i]._Current->Target != GL_TEXTURE_CUBE_MAP)
|
|
return;
|
|
|
|
if (!t)
|
|
return;
|
|
|
|
if (!t->mt)
|
|
return;
|
|
|
|
switch(i) {
|
|
case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
|
|
case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
|
|
default:
|
|
case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
|
|
}
|
|
BEGIN_BATCH(dwords);
|
|
OUT_BATCH_TABLE(atom->cmd, 2);
|
|
lvl = &t->mt->levels[0];
|
|
for (j = 0; j < 5; j++) {
|
|
OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
|
|
OUT_BATCH_RELOC(t->mt->bo, lvl->faces[j].offset,
|
|
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
|
|
}
|
|
END_BATCH();
|
|
}
|
|
|
|
static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
|
|
{
|
|
r100ContextPtr r100 = R100_CONTEXT(ctx);
|
|
BATCH_LOCALS(&r100->radeon);
|
|
uint32_t dwords = atom->cmd_size;
|
|
int i = atom->idx;
|
|
radeonTexObj *t = r100->state.texture.unit[i].texobj;
|
|
radeon_mipmap_level *lvl;
|
|
int hastexture = 1;
|
|
|
|
if (!t)
|
|
hastexture = 0;
|
|
else {
|
|
if (!t->mt && !t->bo)
|
|
hastexture = 0;
|
|
}
|
|
dwords += 1;
|
|
if (hastexture)
|
|
dwords += 2;
|
|
else
|
|
dwords -= 2;
|
|
BEGIN_BATCH(dwords);
|
|
|
|
OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1));
|
|
OUT_BATCH_TABLE((atom->cmd + 1), 2);
|
|
|
|
if (hastexture) {
|
|
OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0));
|
|
if (t->mt && !t->image_override) {
|
|
if (ctx->Texture.Unit[i]._Current &&
|
|
ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
|
|
lvl = &t->mt->levels[t->minLod];
|
|
OUT_BATCH_RELOC(t->mt->bo, lvl->faces[5].offset,
|
|
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
|
|
} else {
|
|
OUT_BATCH_RELOC(t->mt->bo,
|
|
get_base_teximage_offset(t) | t->tile_bits,
|
|
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
|
|
}
|
|
} else {
|
|
if (t->bo)
|
|
OUT_BATCH_RELOC(t->bo, t->tile_bits,
|
|
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
|
|
}
|
|
}
|
|
|
|
OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1));
|
|
OUT_BATCH_TABLE((atom->cmd+4), 2);
|
|
OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0));
|
|
OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR]));
|
|
END_BATCH();
|
|
}
|
|
|
|
/* Initialize the context's hardware state.
|
|
*/
|
|
void radeonInitState( r100ContextPtr rmesa )
|
|
{
|
|
struct gl_context *ctx = &rmesa->radeon.glCtx;
|
|
GLuint i;
|
|
|
|
rmesa->radeon.Fallback = 0;
|
|
|
|
|
|
rmesa->radeon.hw.max_state_size = 0;
|
|
|
|
#define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
|
|
do { \
|
|
rmesa->hw.ATOM.cmd_size = SZ; \
|
|
rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \
|
|
rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \
|
|
rmesa->hw.ATOM.name = NM; \
|
|
rmesa->hw.ATOM.is_tcl = FLAG; \
|
|
rmesa->hw.ATOM.check = check_##CHK; \
|
|
rmesa->hw.ATOM.dirty = GL_TRUE; \
|
|
rmesa->hw.ATOM.idx = IDX; \
|
|
rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
|
|
} while (0)
|
|
|
|
#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
|
|
ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
|
|
|
|
/* Allocate state buffers:
|
|
*/
|
|
ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE, "CTX/context", 0 );
|
|
rmesa->hw.ctx.emit = ctx_emit_cs;
|
|
rmesa->hw.ctx.check = check_always_ctx;
|
|
ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
|
|
ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
|
|
ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
|
|
ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
|
|
ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
|
|
ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
|
|
ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
|
|
ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
|
|
ALLOC_STATE( grd, always_add2, GRD_STATE_SIZE, "GRD/guard-band", 1 );
|
|
ALLOC_STATE( fog, fog_add4, FOG_STATE_SIZE, "FOG/fog", 1 );
|
|
ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 1 );
|
|
ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
|
|
ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
|
|
ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
|
|
ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2);
|
|
ALLOC_STATE( mat[0], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 1 );
|
|
ALLOC_STATE( mat[1], tcl_eyespace_or_fog_add4, MAT_STATE_SIZE, "MAT/modelview", 1 );
|
|
ALLOC_STATE( mat[2], tcl_eyespace_or_lighting_add4, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
|
|
ALLOC_STATE( mat[3], tcl_tex0_add4, MAT_STATE_SIZE, "MAT/texmat0", 1 );
|
|
ALLOC_STATE( mat[4], tcl_tex1_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 );
|
|
ALLOC_STATE( mat[5], tcl_tex2_add4, MAT_STATE_SIZE, "MAT/texmat2", 1 );
|
|
ALLOC_STATE( lit[0], tcl_lit0_add6, LIT_STATE_SIZE, "LIT/light-0", 1 );
|
|
ALLOC_STATE( lit[1], tcl_lit1_add6, LIT_STATE_SIZE, "LIT/light-1", 1 );
|
|
ALLOC_STATE( lit[2], tcl_lit2_add6, LIT_STATE_SIZE, "LIT/light-2", 1 );
|
|
ALLOC_STATE( lit[3], tcl_lit3_add6, LIT_STATE_SIZE, "LIT/light-3", 1 );
|
|
ALLOC_STATE( lit[4], tcl_lit4_add6, LIT_STATE_SIZE, "LIT/light-4", 1 );
|
|
ALLOC_STATE( lit[5], tcl_lit5_add6, LIT_STATE_SIZE, "LIT/light-5", 1 );
|
|
ALLOC_STATE( lit[6], tcl_lit6_add6, LIT_STATE_SIZE, "LIT/light-6", 1 );
|
|
ALLOC_STATE( lit[7], tcl_lit7_add6, LIT_STATE_SIZE, "LIT/light-7", 1 );
|
|
ALLOC_STATE( ucp[0], tcl_ucp0_add4, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
|
|
ALLOC_STATE( ucp[1], tcl_ucp1_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
|
|
ALLOC_STATE( ucp[2], tcl_ucp2_add4, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
|
|
ALLOC_STATE( ucp[3], tcl_ucp3_add4, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
|
|
ALLOC_STATE( ucp[4], tcl_ucp4_add4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
|
|
ALLOC_STATE( ucp[5], tcl_ucp5_add4, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
|
|
ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 );
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
rmesa->hw.tex[i].emit = tex_emit_cs;
|
|
}
|
|
ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
|
|
ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
|
|
ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
|
|
for (i = 0; i < 3; i++)
|
|
rmesa->hw.cube[i].emit = cube_emit_cs;
|
|
|
|
ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 );
|
|
ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 );
|
|
ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 );
|
|
|
|
radeonSetUpAtomList( rmesa );
|
|
|
|
/* Fill in the packet headers:
|
|
*/
|
|
rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
|
|
rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
|
|
rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
|
|
rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
|
|
rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
|
|
rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
|
|
rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
|
|
rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
|
|
rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
|
|
rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
|
|
rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
|
|
rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
|
|
rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
|
|
rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
|
|
rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
|
|
rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
|
|
rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
|
|
rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
|
|
rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
|
|
rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
|
|
rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
|
|
rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
|
|
rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
|
|
rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
|
|
rmesa->hw.mtl.cmd[MTL_CMD_0] =
|
|
cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
|
|
rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
|
|
rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
|
|
rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
|
|
rmesa->hw.grd.cmd[GRD_CMD_0] =
|
|
cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
|
|
rmesa->hw.fog.cmd[FOG_CMD_0] =
|
|
cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
|
|
rmesa->hw.glt.cmd[GLT_CMD_0] =
|
|
cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
|
|
rmesa->hw.eye.cmd[EYE_CMD_0] =
|
|
cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
|
|
|
|
for (i = 0 ; i < 6; i++) {
|
|
rmesa->hw.mat[i].cmd[MAT_CMD_0] =
|
|
cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
|
|
}
|
|
|
|
for (i = 0 ; i < 8; i++) {
|
|
rmesa->hw.lit[i].cmd[LIT_CMD_0] =
|
|
cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
|
|
rmesa->hw.lit[i].cmd[LIT_CMD_1] =
|
|
cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
|
|
}
|
|
|
|
for (i = 0 ; i < 6; i++) {
|
|
rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
|
|
cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
|
|
}
|
|
|
|
rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
|
|
rmesa->hw.stp.cmd[STP_DATA_0] = 0;
|
|
rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
|
|
|
|
rmesa->hw.grd.emit = scl_emit;
|
|
rmesa->hw.fog.emit = vec_emit;
|
|
rmesa->hw.glt.emit = vec_emit;
|
|
rmesa->hw.eye.emit = vec_emit;
|
|
for (i = 0; i < 6; i++)
|
|
rmesa->hw.mat[i].emit = vec_emit;
|
|
|
|
for (i = 0; i < 8; i++)
|
|
rmesa->hw.lit[i].emit = lit_emit;
|
|
|
|
for (i = 0; i < 6; i++)
|
|
rmesa->hw.ucp[i].emit = vec_emit;
|
|
|
|
/* Initial Harware state:
|
|
*/
|
|
rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
|
|
RADEON_CHROMA_FUNC_FAIL |
|
|
RADEON_CHROMA_KEY_NEAREST |
|
|
RADEON_SHADOW_FUNC_EQUAL |
|
|
RADEON_SHADOW_PASS_1 /*|
|
|
RADEON_RIGHT_HAND_CUBE_OGL */);
|
|
|
|
rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
|
|
/* this bit unused for vertex fog */
|
|
RADEON_FOG_USE_DEPTH);
|
|
|
|
rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
|
|
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
|
|
RADEON_SRC_BLEND_GL_ONE |
|
|
RADEON_DST_BLEND_GL_ZERO );
|
|
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
|
|
RADEON_STENCIL_TEST_ALWAYS |
|
|
RADEON_STENCIL_FAIL_KEEP |
|
|
RADEON_STENCIL_ZPASS_KEEP |
|
|
RADEON_STENCIL_ZFAIL_KEEP |
|
|
RADEON_Z_WRITE_ENABLE);
|
|
|
|
if (rmesa->using_hyperz) {
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
|
|
RADEON_Z_DECOMPRESSION_ENABLE;
|
|
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
|
|
/* works for q3, but slight rendering errors with glxgears ? */
|
|
/* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
|
|
/* need this otherwise get lots of lockups with q3 ??? */
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
|
|
}
|
|
}
|
|
|
|
rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
|
|
RADEON_ANTI_ALIAS_NONE);
|
|
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
|
|
RADEON_ZBLOCK16);
|
|
|
|
switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
|
|
case DRI_CONF_DITHER_XERRORDIFFRESET:
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
|
|
break;
|
|
case DRI_CONF_DITHER_ORDERED:
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
|
|
break;
|
|
}
|
|
if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
|
|
DRI_CONF_ROUND_ROUND )
|
|
rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE;
|
|
else
|
|
rmesa->radeon.state.color.roundEnable = 0;
|
|
if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
|
|
DRI_CONF_COLOR_REDUCTION_DITHER )
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
|
|
else
|
|
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
|
|
|
|
|
|
rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
|
|
RADEON_BFACE_SOLID |
|
|
RADEON_FFACE_SOLID |
|
|
/* RADEON_BADVTX_CULL_DISABLE | */
|
|
RADEON_FLAT_SHADE_VTX_LAST |
|
|
RADEON_DIFFUSE_SHADE_GOURAUD |
|
|
RADEON_ALPHA_SHADE_GOURAUD |
|
|
RADEON_SPECULAR_SHADE_GOURAUD |
|
|
RADEON_FOG_SHADE_GOURAUD |
|
|
RADEON_VPORT_XY_XFORM_ENABLE |
|
|
RADEON_VPORT_Z_XFORM_ENABLE |
|
|
RADEON_VTX_PIX_CENTER_OGL |
|
|
RADEON_ROUND_MODE_TRUNC |
|
|
RADEON_ROUND_PREC_8TH_PIX);
|
|
|
|
rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
|
|
#ifdef MESA_BIG_ENDIAN
|
|
RADEON_VC_32BIT_SWAP;
|
|
#else
|
|
RADEON_VC_NO_SWAP;
|
|
#endif
|
|
|
|
if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
|
|
rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
|
|
}
|
|
|
|
rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
|
|
RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
|
|
RADEON_TEX1_W_ROUTING_USE_Q1);
|
|
|
|
|
|
rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
|
|
|
|
rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
|
|
((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
|
|
(1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
|
|
|
|
rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
|
|
|
|
rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
|
|
((0x00 << RADEON_STENCIL_REF_SHIFT) |
|
|
(0xff << RADEON_STENCIL_MASK_SHIFT) |
|
|
(0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
|
|
|
|
rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
|
|
rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
|
|
|
|
rmesa->hw.msc.cmd[MSC_RE_MISC] =
|
|
((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
|
|
(0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
|
|
RADEON_STIPPLE_BIG_BIT_ORDER);
|
|
|
|
rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
|
|
rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
|
|
rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
|
|
rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
|
|
rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
|
|
rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
|
|
|
|
for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
|
|
rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
|
|
rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
|
|
(RADEON_TXFORMAT_ENDIAN_NO_SWAP |
|
|
RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
|
|
(i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
|
|
(2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
|
|
(2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
|
|
|
|
/* Initialize the texture offset to the start of the card texture heap */
|
|
// rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
|
|
// rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
|
|
|
|
rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
|
|
rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
|
|
(RADEON_COLOR_ARG_A_ZERO |
|
|
RADEON_COLOR_ARG_B_ZERO |
|
|
RADEON_COLOR_ARG_C_CURRENT_COLOR |
|
|
RADEON_BLEND_CTL_ADD |
|
|
RADEON_SCALE_1X |
|
|
RADEON_CLAMP_TX);
|
|
rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
|
|
(RADEON_ALPHA_ARG_A_ZERO |
|
|
RADEON_ALPHA_ARG_B_ZERO |
|
|
RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
|
|
RADEON_BLEND_CTL_ADD |
|
|
RADEON_SCALE_1X |
|
|
RADEON_CLAMP_TX);
|
|
rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
|
|
|
|
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
|
|
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
|
|
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
|
|
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
|
|
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
|
|
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
|
|
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
|
|
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
|
|
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
|
|
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
|
|
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
|
|
}
|
|
|
|
/* Can only add ST1 at the time of doing some multitex but can keep
|
|
* it after that. Errors if DIFFUSE is missing.
|
|
*/
|
|
rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
|
|
(RADEON_TCL_VTX_Z0 |
|
|
RADEON_TCL_VTX_W0 |
|
|
RADEON_TCL_VTX_PK_DIFFUSE
|
|
); /* need to keep this uptodate */
|
|
|
|
rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
|
|
( RADEON_TCL_COMPUTE_XYZW |
|
|
(RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
|
|
(RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
|
|
(RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
|
|
|
|
|
|
/* XXX */
|
|
rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
|
|
((MODEL << RADEON_MODELVIEW_0_SHIFT) |
|
|
(MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
|
|
|
|
rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
|
|
((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
|
|
(TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
|
|
(TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) |
|
|
(TEXMAT_2 << RADEON_TEXMAT_2_SHIFT));
|
|
|
|
rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
|
|
(RADEON_UCP_IN_CLIP_SPACE |
|
|
RADEON_CULL_FRONT_IS_CCW);
|
|
|
|
rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
|
|
|
|
rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
|
|
(RADEON_SPECULAR_LIGHTS |
|
|
RADEON_DIFFUSE_SPECULAR_COMBINE |
|
|
RADEON_LOCAL_LIGHT_VEC_GL |
|
|
(RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
|
|
(RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
|
|
(RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
|
|
(RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
|
|
|
|
for (i = 0 ; i < 8; i++) {
|
|
struct gl_light_uniforms *lu = &ctx->Light.LightSource[i];
|
|
GLenum p = GL_LIGHT0 + i;
|
|
*(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
|
|
|
|
ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, lu->Ambient );
|
|
ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, lu->Diffuse );
|
|
ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, lu->Specular );
|
|
ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
|
|
ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
|
|
ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &lu->SpotExponent );
|
|
ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &lu->SpotCutoff );
|
|
ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
|
|
&lu->ConstantAttenuation );
|
|
ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
|
|
&lu->LinearAttenuation );
|
|
ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
|
|
&lu->QuadraticAttenuation );
|
|
*(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
|
|
}
|
|
|
|
ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
|
|
ctx->Light.Model.Ambient );
|
|
|
|
TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
|
|
|
|
for (i = 0 ; i < 6; i++) {
|
|
ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
|
|
}
|
|
|
|
ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
|
|
ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
|
|
ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
|
|
ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
|
|
ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
|
|
ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
|
|
|
|
rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
|
|
rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
|
|
rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
|
|
rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
|
|
|
|
rmesa->hw.eye.cmd[EYE_X] = 0;
|
|
rmesa->hw.eye.cmd[EYE_Y] = 0;
|
|
rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
|
|
rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
|
|
|
|
radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE);
|
|
rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0);
|
|
rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0;
|
|
|
|
rmesa->radeon.hw.all_dirty = GL_TRUE;
|
|
|
|
rcommonInitCmdBuf(&rmesa->radeon);
|
|
}
|