581 lines
17 KiB
C
581 lines
17 KiB
C
/*
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* Copyright (C) 2009 Maciej Cencora.
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* Copyright (C) 2008 Nicolai Haehnle.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "radeon_mipmap_tree.h"
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#include <errno.h>
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#include <unistd.h>
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#include "main/teximage.h"
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#include "main/texobj.h"
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#include "main/enums.h"
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#include "util/u_memory.h"
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#include "radeon_texture.h"
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#include "radeon_tile.h"
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static unsigned get_aligned_compressed_row_stride(
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mesa_format format,
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unsigned width,
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unsigned minStride)
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{
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const unsigned blockBytes = _mesa_get_format_bytes(format);
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unsigned blockWidth, blockHeight;
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unsigned stride;
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_mesa_get_format_block_size(format, &blockWidth, &blockHeight);
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/* Count number of blocks required to store the given width.
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* And then multiple it with bytes required to store a block.
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*/
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stride = (width + blockWidth - 1) / blockWidth * blockBytes;
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/* Round the given minimum stride to the next full blocksize.
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* (minStride + blockBytes - 1) / blockBytes * blockBytes
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*/
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if ( stride < minStride )
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stride = (minStride + blockBytes - 1) / blockBytes * blockBytes;
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radeon_print(RADEON_TEXTURE, RADEON_TRACE,
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"%s width %u, minStride %u, block(bytes %u, width %u):"
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"stride %u\n",
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__func__, width, minStride,
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blockBytes, blockWidth,
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stride);
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return stride;
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}
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unsigned get_texture_image_size(
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mesa_format format,
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unsigned rowStride,
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unsigned height,
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unsigned depth,
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unsigned tiling)
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{
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if (_mesa_is_format_compressed(format)) {
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unsigned blockWidth, blockHeight;
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_mesa_get_format_block_size(format, &blockWidth, &blockHeight);
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return rowStride * ((height + blockHeight - 1) / blockHeight) * depth;
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} else if (tiling) {
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/* Need to align height to tile height */
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unsigned tileWidth, tileHeight;
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get_tile_size(format, &tileWidth, &tileHeight);
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tileHeight--;
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height = (height + tileHeight) & ~tileHeight;
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}
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return rowStride * height * depth;
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}
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unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, GLuint target)
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{
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if (_mesa_is_format_compressed(format)) {
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return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
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} else {
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unsigned row_align;
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if (!util_is_power_of_two_or_zero(width) || target == GL_TEXTURE_RECTANGLE) {
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row_align = rmesa->texture_rect_row_align - 1;
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} else if (tiling) {
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unsigned tileWidth, tileHeight;
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get_tile_size(format, &tileWidth, &tileHeight);
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row_align = tileWidth * _mesa_get_format_bytes(format) - 1;
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} else {
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row_align = rmesa->texture_row_align - 1;
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}
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return (_mesa_format_row_stride(format, width) + row_align) & ~row_align;
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}
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}
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/**
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* Compute sizes and fill in offset and blit information for the given
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* image (determined by \p face and \p level).
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*
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* \param curOffset points to the offset at which the image is to be stored
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* and is updated by this function according to the size of the image.
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*/
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static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
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GLuint face, GLuint level, GLuint* curOffset)
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{
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radeon_mipmap_level *lvl = &mt->levels[level];
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GLuint height;
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height = util_next_power_of_two(lvl->height);
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lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
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lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
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assert(lvl->size > 0);
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lvl->faces[face].offset = *curOffset;
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*curOffset += lvl->size;
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radeon_print(RADEON_TEXTURE, RADEON_TRACE,
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"%s(%p) level %d, face %d: rs:%d %dx%d at %d\n",
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__func__, rmesa,
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level, face,
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lvl->rowstride, lvl->width, height, lvl->faces[face].offset);
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}
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static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
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{
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GLuint curOffset, i, face, level;
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assert(1 << (mt->numLevels - 1) <= rmesa->glCtx.Const.MaxTextureSize);
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curOffset = 0;
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for(face = 0; face < mt->faces; face++) {
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for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
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mt->levels[level].valid = 1;
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mt->levels[level].width = minify(mt->width0, i);
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mt->levels[level].height = minify(mt->height0, i);
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mt->levels[level].depth = minify(mt->depth0, i);
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compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
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}
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}
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/* Note the required size in memory */
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mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
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radeon_print(RADEON_TEXTURE, RADEON_TRACE,
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"%s(%p, %p) total size %d\n",
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__func__, rmesa, mt, mt->totalsize);
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}
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/**
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* Create a new mipmap tree, calculate its layout and allocate memory.
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*/
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radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
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GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels,
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GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
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{
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radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
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radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
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"%s(%p) new tree is %p.\n",
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__func__, rmesa, mt);
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mt->mesaFormat = mesaFormat;
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mt->refcount = 1;
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mt->target = target;
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mt->faces = _mesa_num_tex_faces(target);
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mt->baseLevel = baseLevel;
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mt->numLevels = numLevels;
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mt->width0 = width0;
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mt->height0 = height0;
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mt->depth0 = depth0;
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mt->tilebits = tilebits;
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calculate_miptree_layout(rmesa, mt);
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mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
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0, mt->totalsize, 1024,
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RADEON_GEM_DOMAIN_VRAM,
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0);
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return mt;
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}
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void radeon_miptree_reference(radeon_mipmap_tree *mt, radeon_mipmap_tree **ptr)
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{
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assert(!*ptr);
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mt->refcount++;
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assert(mt->refcount > 0);
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*ptr = mt;
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}
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void radeon_miptree_unreference(radeon_mipmap_tree **ptr)
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{
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radeon_mipmap_tree *mt = *ptr;
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if (!mt)
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return;
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assert(mt->refcount > 0);
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mt->refcount--;
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if (!mt->refcount) {
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radeon_bo_unref(mt->bo);
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free(mt);
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}
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*ptr = 0;
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}
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/**
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* Calculate min and max LOD for the given texture object.
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* @param[in] tObj texture object whose LOD values to calculate
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* @param[out] pminLod minimal LOD
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* @param[out] pmaxLod maximal LOD
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*/
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static void calculate_min_max_lod(struct gl_sampler_object *samp, struct gl_texture_object *tObj,
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unsigned *pminLod, unsigned *pmaxLod)
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{
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int minLod, maxLod;
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/* Yes, this looks overly complicated, but it's all needed.
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*/
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switch (tObj->Target) {
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case GL_TEXTURE_1D:
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case GL_TEXTURE_2D:
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case GL_TEXTURE_3D:
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case GL_TEXTURE_CUBE_MAP:
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if (samp->Attrib.MinFilter == GL_NEAREST || samp->Attrib.MinFilter == GL_LINEAR) {
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/* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
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*/
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minLod = maxLod = tObj->Attrib.BaseLevel;
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} else {
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minLod = tObj->Attrib.BaseLevel + (GLint)(samp->Attrib.MinLod);
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minLod = MAX2(minLod, tObj->Attrib.BaseLevel);
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minLod = MIN2(minLod, tObj->Attrib.MaxLevel);
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maxLod = tObj->Attrib.BaseLevel + (GLint)(samp->Attrib.MaxLod + 0.5);
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maxLod = MIN2(maxLod, tObj->Attrib.MaxLevel);
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maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxNumLevels - 1 + minLod);
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maxLod = MAX2(maxLod, minLod); /* need at least one level */
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}
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break;
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case GL_TEXTURE_RECTANGLE_NV:
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case GL_TEXTURE_4D_SGIS:
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minLod = maxLod = 0;
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break;
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default:
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return;
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}
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radeon_print(RADEON_TEXTURE, RADEON_TRACE,
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"%s(%p) target %s, min %d, max %d.\n",
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__func__, tObj,
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_mesa_enum_to_string(tObj->Target),
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minLod, maxLod);
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/* save these values */
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*pminLod = minLod;
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*pmaxLod = maxLod;
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}
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/**
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* Checks whether the given miptree can hold the given texture image at the
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* given face and level.
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*/
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GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
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struct gl_texture_image *texImage)
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{
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radeon_mipmap_level *lvl;
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GLuint level = texImage->Level;
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if (texImage->TexFormat != mt->mesaFormat)
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return GL_FALSE;
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lvl = &mt->levels[level];
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if (!lvl->valid ||
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lvl->width != texImage->Width ||
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lvl->height != texImage->Height ||
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lvl->depth != texImage->Depth)
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return GL_FALSE;
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return GL_TRUE;
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}
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/**
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* Checks whether the given miptree has the right format to store the given texture object.
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*/
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static GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj)
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{
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struct gl_texture_image *firstImage;
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unsigned numLevels;
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radeon_mipmap_level *mtBaseLevel;
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if (texObj->Attrib.BaseLevel < mt->baseLevel)
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return GL_FALSE;
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mtBaseLevel = &mt->levels[texObj->Attrib.BaseLevel - mt->baseLevel];
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firstImage = texObj->Image[0][texObj->Attrib.BaseLevel];
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numLevels = MIN2(texObj->_MaxLevel - texObj->Attrib.BaseLevel + 1, firstImage->MaxNumLevels);
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if (radeon_is_debug_enabled(RADEON_TEXTURE,RADEON_TRACE)) {
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fprintf(stderr, "Checking if miptree %p matches texObj %p\n", mt, texObj);
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fprintf(stderr, "target %d vs %d\n", mt->target, texObj->Target);
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fprintf(stderr, "format %d vs %d\n", mt->mesaFormat, firstImage->TexFormat);
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fprintf(stderr, "numLevels %d vs %d\n", mt->numLevels, numLevels);
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fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
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fprintf(stderr, "height0 %d vs %d\n", mtBaseLevel->height, firstImage->Height);
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fprintf(stderr, "depth0 %d vs %d\n", mtBaseLevel->depth, firstImage->Depth);
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if (mt->target == texObj->Target &&
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mt->mesaFormat == firstImage->TexFormat &&
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mt->numLevels >= numLevels &&
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mtBaseLevel->width == firstImage->Width &&
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mtBaseLevel->height == firstImage->Height &&
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mtBaseLevel->depth == firstImage->Depth) {
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fprintf(stderr, "MATCHED\n");
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} else {
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fprintf(stderr, "NOT MATCHED\n");
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}
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}
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return (mt->target == texObj->Target &&
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mt->mesaFormat == firstImage->TexFormat &&
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mt->numLevels >= numLevels &&
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mtBaseLevel->width == firstImage->Width &&
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mtBaseLevel->height == firstImage->Height &&
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mtBaseLevel->depth == firstImage->Depth);
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}
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/**
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* Try to allocate a mipmap tree for the given texture object.
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* @param[in] rmesa radeon context
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* @param[in] t radeon texture object
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*/
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void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t)
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{
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struct gl_texture_object *texObj = &t->base;
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struct gl_texture_image *texImg = texObj->Image[0][texObj->Attrib.BaseLevel];
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GLuint numLevels;
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assert(!t->mt);
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if (!texImg) {
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radeon_warning("%s(%p) No image in given texture object(%p).\n",
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__func__, rmesa, t);
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return;
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}
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numLevels = MIN2(texObj->Attrib.MaxLevel - texObj->Attrib.BaseLevel + 1, texImg->MaxNumLevels);
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t->mt = radeon_miptree_create(rmesa, t->base.Target,
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texImg->TexFormat, texObj->Attrib.BaseLevel,
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numLevels, texImg->Width, texImg->Height,
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texImg->Depth, t->tile_bits);
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}
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GLuint
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radeon_miptree_image_offset(radeon_mipmap_tree *mt,
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GLuint face, GLuint level)
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{
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if (mt->target == GL_TEXTURE_CUBE_MAP_ARB)
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return (mt->levels[level].faces[face].offset);
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else
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return mt->levels[level].faces[0].offset;
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}
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/**
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* Ensure that the given image is stored in the given miptree from now on.
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*/
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static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
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radeon_texture_image *image,
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int face, int level)
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{
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radeon_mipmap_level *dstlvl = &mt->levels[level];
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unsigned char *dest;
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assert(image->mt != mt);
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assert(dstlvl->valid);
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assert(dstlvl->width == image->base.Base.Width);
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assert(dstlvl->height == image->base.Base.Height);
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assert(dstlvl->depth == image->base.Base.Depth);
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radeon_print(RADEON_TEXTURE, RADEON_VERBOSE,
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"%s miptree %p, image %p, face %d, level %d.\n",
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__func__, mt, image, face, level);
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radeon_bo_map(mt->bo, GL_TRUE);
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dest = mt->bo->ptr + dstlvl->faces[face].offset;
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if (image->mt) {
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/* Format etc. should match, so we really just need a memcpy().
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* In fact, that memcpy() could be done by the hardware in many
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* cases, provided that we have a proper memory manager.
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*/
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assert(mt->mesaFormat == image->base.Base.TexFormat);
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radeon_mipmap_level *srclvl = &image->mt->levels[image->base.Base.Level];
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assert(image->base.Base.Level == level);
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assert(srclvl->size == dstlvl->size);
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assert(srclvl->rowstride == dstlvl->rowstride);
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radeon_bo_map(image->mt->bo, GL_FALSE);
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memcpy(dest,
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image->mt->bo->ptr + srclvl->faces[face].offset,
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dstlvl->size);
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radeon_bo_unmap(image->mt->bo);
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radeon_miptree_unreference(&image->mt);
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}
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radeon_bo_unmap(mt->bo);
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radeon_miptree_reference(mt, &image->mt);
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}
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/**
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* Filter matching miptrees, and select one with the most of data.
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* @param[in] texObj radeon texture object
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* @param[in] firstLevel first texture level to check
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* @param[in] lastLevel last texture level to check
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*/
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static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
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unsigned firstLevel,
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unsigned lastLevel)
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{
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const unsigned numLevels = lastLevel - firstLevel + 1;
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unsigned *mtSizes = calloc(numLevels, sizeof(unsigned));
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radeon_mipmap_tree **mts = calloc(numLevels, sizeof(radeon_mipmap_tree *));
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unsigned mtCount = 0;
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unsigned maxMtIndex = 0;
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radeon_mipmap_tree *tmp;
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unsigned int level;
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int i;
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for (level = firstLevel; level <= lastLevel; ++level) {
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radeon_texture_image *img = get_radeon_texture_image(texObj->base.Image[0][level]);
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unsigned found = 0;
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// TODO: why this hack??
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if (!img)
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break;
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if (!img->mt)
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continue;
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for (i = 0; i < mtCount; ++i) {
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if (mts[i] == img->mt) {
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found = 1;
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mtSizes[i] += img->mt->levels[img->base.Base.Level].size;
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break;
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}
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}
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|
|
if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) {
|
|
mtSizes[mtCount] = img->mt->levels[img->base.Base.Level].size;
|
|
mts[mtCount] = img->mt;
|
|
mtCount++;
|
|
}
|
|
}
|
|
|
|
if (mtCount == 0) {
|
|
free(mtSizes);
|
|
free(mts);
|
|
return NULL;
|
|
}
|
|
|
|
for (i = 1; i < mtCount; ++i) {
|
|
if (mtSizes[i] > mtSizes[maxMtIndex]) {
|
|
maxMtIndex = i;
|
|
}
|
|
}
|
|
|
|
tmp = mts[maxMtIndex];
|
|
free(mtSizes);
|
|
free(mts);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
/**
|
|
* Validate texture mipmap tree.
|
|
* If individual images are stored in different mipmap trees
|
|
* use the mipmap tree that has the most of the correct data.
|
|
*/
|
|
int radeon_validate_texture_miptree(struct gl_context * ctx,
|
|
struct gl_sampler_object *samp,
|
|
struct gl_texture_object *texObj)
|
|
{
|
|
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
|
|
radeonTexObj *t = radeon_tex_obj(texObj);
|
|
radeon_mipmap_tree *dst_miptree;
|
|
|
|
if (samp == &texObj->Sampler && (t->validated || t->image_override)) {
|
|
return GL_TRUE;
|
|
}
|
|
|
|
calculate_min_max_lod(samp, &t->base, &t->minLod, &t->maxLod);
|
|
|
|
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
|
|
"%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
|
|
__func__, texObj ,t->minLod, t->maxLod);
|
|
|
|
dst_miptree = get_biggest_matching_miptree(t, t->base.Attrib.BaseLevel, t->base._MaxLevel);
|
|
|
|
radeon_miptree_unreference(&t->mt);
|
|
if (!dst_miptree) {
|
|
radeon_try_alloc_miptree(rmesa, t);
|
|
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
|
|
"%s: No matching miptree found, allocated new one %p\n",
|
|
__func__, t->mt);
|
|
|
|
} else {
|
|
radeon_miptree_reference(dst_miptree, &t->mt);
|
|
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
|
|
"%s: Using miptree %p\n", __func__, t->mt);
|
|
}
|
|
|
|
const unsigned faces = _mesa_num_tex_faces(texObj->Target);
|
|
unsigned face, level;
|
|
radeon_texture_image *img;
|
|
/* Validate only the levels that will actually be used during rendering */
|
|
for (face = 0; face < faces; ++face) {
|
|
for (level = t->minLod; level <= t->maxLod; ++level) {
|
|
img = get_radeon_texture_image(texObj->Image[face][level]);
|
|
|
|
radeon_print(RADEON_TEXTURE, RADEON_TRACE,
|
|
"Checking image level %d, face %d, mt %p ... ",
|
|
level, face, img->mt);
|
|
|
|
if (img->mt != t->mt && !img->used_as_render_target) {
|
|
radeon_print(RADEON_TEXTURE, RADEON_TRACE,
|
|
"MIGRATING\n");
|
|
|
|
struct radeon_bo *src_bo = (img->mt) ? img->mt->bo : img->bo;
|
|
if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) {
|
|
radeon_firevertices(rmesa);
|
|
}
|
|
migrate_image_to_miptree(t->mt, img, face, level);
|
|
} else
|
|
radeon_print(RADEON_TEXTURE, RADEON_TRACE, "OK\n");
|
|
}
|
|
}
|
|
|
|
t->validated = GL_TRUE;
|
|
|
|
return GL_TRUE;
|
|
}
|
|
|
|
uint32_t get_base_teximage_offset(radeonTexObj *texObj)
|
|
{
|
|
if (!texObj->mt) {
|
|
return 0;
|
|
} else {
|
|
return radeon_miptree_image_offset(texObj->mt, 0, texObj->minLod);
|
|
}
|
|
}
|