421 lines
14 KiB
C
421 lines
14 KiB
C
/*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "radeon_common.h"
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#include "radeon_context.h"
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#include "radeon_blit.h"
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#include "radeon_tex.h"
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static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
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int reg, int count)
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{
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if (count)
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return CP_PACKET0(reg, count - 1);
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return CP_PACKET2;
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}
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/* common formats supported as both textures and render targets */
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unsigned r100_check_blit(mesa_format mesa_format, uint32_t dst_pitch)
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{
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/* XXX others? */
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switch (mesa_format) {
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#if UTIL_ARCH_LITTLE_ENDIAN
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case MESA_FORMAT_B8G8R8A8_UNORM:
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case MESA_FORMAT_B8G8R8X8_UNORM:
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case MESA_FORMAT_B5G6R5_UNORM:
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case MESA_FORMAT_B4G4R4A4_UNORM:
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case MESA_FORMAT_B5G5R5A1_UNORM:
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#else
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case MESA_FORMAT_A8R8G8B8_UNORM:
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case MESA_FORMAT_X8R8G8B8_UNORM:
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case MESA_FORMAT_R5G6B5_UNORM:
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case MESA_FORMAT_A4R4G4B4_UNORM:
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case MESA_FORMAT_A1R5G5B5_UNORM:
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#endif
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case MESA_FORMAT_A_UNORM8:
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case MESA_FORMAT_L_UNORM8:
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case MESA_FORMAT_I_UNORM8:
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break;
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default:
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return 0;
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}
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/* Rendering to small buffer doesn't work.
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* Looks like a hw limitation.
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*/
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if (dst_pitch < 32)
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return 0;
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/* ??? */
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if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
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return 0;
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return 1;
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}
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static inline void emit_vtx_state(struct r100_context *r100)
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{
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BATCH_LOCALS(&r100->radeon);
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BEGIN_BATCH(8);
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if (r100->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
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OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, 0);
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} else {
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OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
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}
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OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
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RADEON_TEX1_W_ROUTING_USE_W0));
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OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0);
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OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
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RADEON_BFACE_SOLID |
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RADEON_FFACE_SOLID |
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RADEON_VTX_PIX_CENTER_OGL |
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RADEON_ROUND_MODE_ROUND |
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RADEON_ROUND_PREC_4TH_PIX));
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END_BATCH();
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}
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static void inline emit_tx_setup(struct r100_context *r100,
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mesa_format mesa_format,
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struct radeon_bo *bo,
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intptr_t offset,
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unsigned width,
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unsigned height,
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unsigned pitch)
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{
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uint32_t txformat = RADEON_TXFORMAT_NON_POWER2;
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BATCH_LOCALS(&r100->radeon);
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assert(width <= 2048);
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assert(height <= 2048);
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assert(offset % 32 == 0);
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txformat |= tx_table[mesa_format].format;
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if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
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offset |= RADEON_TXO_MACRO_TILE;
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if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
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offset |= RADEON_TXO_MICRO_TILE_X2;
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BEGIN_BATCH(18);
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OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
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OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0, (RADEON_COLOR_ARG_A_ZERO |
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RADEON_COLOR_ARG_B_ZERO |
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RADEON_COLOR_ARG_C_T0_COLOR |
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RADEON_BLEND_CTL_ADD |
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RADEON_CLAMP_TX));
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OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0, (RADEON_ALPHA_ARG_A_ZERO |
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RADEON_ALPHA_ARG_B_ZERO |
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RADEON_ALPHA_ARG_C_T0_ALPHA |
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RADEON_BLEND_CTL_ADD |
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RADEON_CLAMP_TX));
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OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0, (RADEON_CLAMP_S_CLAMP_LAST |
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RADEON_CLAMP_T_CLAMP_LAST |
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RADEON_MAG_FILTER_NEAREST |
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RADEON_MIN_FILTER_NEAREST));
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OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0, txformat);
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OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0, ((width - 1) |
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((height - 1) << RADEON_TEX_VSIZE_SHIFT)));
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OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32);
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OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0, 1);
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OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
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END_BATCH();
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}
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static inline void emit_cb_setup(struct r100_context *r100,
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struct radeon_bo *bo,
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intptr_t offset,
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mesa_format mesa_format,
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unsigned pitch,
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unsigned width,
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unsigned height)
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{
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uint32_t dst_pitch = pitch;
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uint32_t dst_format = 0;
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BATCH_LOCALS(&r100->radeon);
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/* XXX others? */
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switch (mesa_format) {
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/* The first of each pair is for little, the second for big endian. */
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case MESA_FORMAT_B8G8R8A8_UNORM:
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case MESA_FORMAT_A8R8G8B8_UNORM:
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case MESA_FORMAT_B8G8R8X8_UNORM:
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case MESA_FORMAT_X8R8G8B8_UNORM:
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dst_format = RADEON_COLOR_FORMAT_ARGB8888;
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break;
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case MESA_FORMAT_B5G6R5_UNORM:
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case MESA_FORMAT_R5G6B5_UNORM:
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dst_format = RADEON_COLOR_FORMAT_RGB565;
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break;
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case MESA_FORMAT_B4G4R4A4_UNORM:
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case MESA_FORMAT_A4R4G4B4_UNORM:
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dst_format = RADEON_COLOR_FORMAT_ARGB4444;
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break;
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case MESA_FORMAT_B5G5R5A1_UNORM:
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case MESA_FORMAT_A1R5G5B5_UNORM:
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dst_format = RADEON_COLOR_FORMAT_ARGB1555;
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break;
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case MESA_FORMAT_A_UNORM8:
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case MESA_FORMAT_L_UNORM8:
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case MESA_FORMAT_I_UNORM8:
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dst_format = RADEON_COLOR_FORMAT_RGB8;
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break;
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default:
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break;
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}
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if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
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dst_pitch |= RADEON_COLOR_TILE_ENABLE;
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if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
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dst_pitch |= RADEON_COLOR_MICROTILE_ENABLE;
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BEGIN_BATCH(18);
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OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
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OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) |
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((height - 1) << RADEON_RE_HEIGHT_SHIFT)));
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OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
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OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
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OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
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OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
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OUT_BATCH_RELOC(bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
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OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
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OUT_BATCH_RELOC(bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
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END_BATCH();
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}
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static GLboolean validate_buffers(struct r100_context *r100,
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struct radeon_bo *src_bo,
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struct radeon_bo *dst_bo)
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{
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int ret;
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radeon_cs_space_reset_bos(r100->radeon.cmdbuf.cs);
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ret = radeon_cs_space_check_with_bo(r100->radeon.cmdbuf.cs,
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src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
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if (ret)
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return GL_FALSE;
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ret = radeon_cs_space_check_with_bo(r100->radeon.cmdbuf.cs,
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dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
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if (ret)
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return GL_FALSE;
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return GL_TRUE;
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}
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/**
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* Calculate texcoords for given image region.
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* Output values are [minx, maxx, miny, maxy]
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*/
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static inline void calc_tex_coords(float img_width, float img_height,
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float x, float y,
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float reg_width, float reg_height,
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unsigned flip_y, float *buf)
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{
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buf[0] = x / img_width;
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buf[1] = buf[0] + reg_width / img_width;
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buf[2] = y / img_height;
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buf[3] = buf[2] + reg_height / img_height;
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if (flip_y)
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{
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buf[2] = 1.0 - buf[2];
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buf[3] = 1.0 - buf[3];
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}
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}
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static inline void emit_draw_packet(struct r100_context *r100,
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unsigned src_width, unsigned src_height,
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unsigned src_x_offset, unsigned src_y_offset,
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unsigned dst_x_offset, unsigned dst_y_offset,
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unsigned reg_width, unsigned reg_height,
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unsigned flip_y)
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{
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float texcoords[4];
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float verts[12];
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BATCH_LOCALS(&r100->radeon);
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calc_tex_coords(src_width, src_height,
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src_x_offset, src_y_offset,
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reg_width, reg_height,
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flip_y, texcoords);
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verts[0] = dst_x_offset;
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verts[1] = dst_y_offset + reg_height;
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verts[2] = texcoords[0];
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verts[3] = texcoords[3];
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verts[4] = dst_x_offset + reg_width;
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verts[5] = dst_y_offset + reg_height;
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verts[6] = texcoords[1];
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verts[7] = texcoords[3];
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verts[8] = dst_x_offset + reg_width;
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verts[9] = dst_y_offset;
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verts[10] = texcoords[1];
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verts[11] = texcoords[2];
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BEGIN_BATCH(15);
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OUT_BATCH(RADEON_CP_PACKET3_3D_DRAW_IMMD | (13 << 16));
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OUT_BATCH(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0);
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OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
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RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
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RADEON_CP_VC_CNTL_MAOS_ENABLE |
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RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
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(3 << 16));
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OUT_BATCH_TABLE(verts, 12);
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END_BATCH();
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}
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/**
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* Copy a region of [@a width x @a height] pixels from source buffer
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* to destination buffer.
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* @param[in] r100 r100 context
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* @param[in] src_bo source radeon buffer object
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* @param[in] src_offset offset of the source image in the @a src_bo
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* @param[in] src_mesaformat source image format
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* @param[in] src_pitch aligned source image width
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* @param[in] src_width source image width
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* @param[in] src_height source image height
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* @param[in] src_x_offset x offset in the source image
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* @param[in] src_y_offset y offset in the source image
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* @param[in] dst_bo destination radeon buffer object
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* @param[in] dst_offset offset of the destination image in the @a dst_bo
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* @param[in] dst_mesaformat destination image format
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* @param[in] dst_pitch aligned destination image width
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* @param[in] dst_width destination image width
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* @param[in] dst_height destination image height
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* @param[in] dst_x_offset x offset in the destination image
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* @param[in] dst_y_offset y offset in the destination image
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* @param[in] width region width
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* @param[in] height region height
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* @param[in] flip_y set if y coords of the source image need to be flipped
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*/
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unsigned r100_blit(struct gl_context *ctx,
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struct radeon_bo *src_bo,
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intptr_t src_offset,
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mesa_format src_mesaformat,
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unsigned src_pitch,
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unsigned src_width,
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unsigned src_height,
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unsigned src_x_offset,
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unsigned src_y_offset,
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struct radeon_bo *dst_bo,
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intptr_t dst_offset,
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mesa_format dst_mesaformat,
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unsigned dst_pitch,
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unsigned dst_width,
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unsigned dst_height,
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unsigned dst_x_offset,
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unsigned dst_y_offset,
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unsigned reg_width,
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unsigned reg_height,
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unsigned flip_y)
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{
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struct r100_context *r100 = R100_CONTEXT(ctx);
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if (!r100_check_blit(dst_mesaformat, dst_pitch))
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return GL_FALSE;
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/* Make sure that colorbuffer has even width - hw limitation */
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if (dst_pitch % 2 > 0)
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++dst_pitch;
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/* Need to clamp the region size to make sure
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* we don't read outside of the source buffer
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* or write outside of the destination buffer.
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*/
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if (reg_width + src_x_offset > src_width)
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reg_width = src_width - src_x_offset;
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if (reg_height + src_y_offset > src_height)
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reg_height = src_height - src_y_offset;
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if (reg_width + dst_x_offset > dst_width)
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reg_width = dst_width - dst_x_offset;
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if (reg_height + dst_y_offset > dst_height)
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reg_height = dst_height - dst_y_offset;
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if (src_bo == dst_bo) {
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return GL_FALSE;
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}
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if (src_offset % 32 || dst_offset % 32) {
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return GL_FALSE;
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}
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if (0) {
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fprintf(stderr, "src: size [%d x %d], pitch %d, offset %zd "
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"offset [%d x %d], format %s, bo %p\n",
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src_width, src_height, src_pitch, src_offset,
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src_x_offset, src_y_offset,
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_mesa_get_format_name(src_mesaformat),
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src_bo);
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fprintf(stderr, "dst: pitch %d offset %zd, offset[%d x %d], format %s, bo %p\n",
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dst_pitch, dst_offset, dst_x_offset, dst_y_offset,
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_mesa_get_format_name(dst_mesaformat), dst_bo);
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fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
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}
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/* Flush is needed to make sure that source buffer has correct data */
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radeonFlush(ctx, 0);
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rcommonEnsureCmdBufSpace(&r100->radeon, 59, __func__);
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if (!validate_buffers(r100, src_bo, dst_bo))
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return GL_FALSE;
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/* 8 */
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emit_vtx_state(r100);
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/* 18 */
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emit_tx_setup(r100, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
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/* 18 */
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emit_cb_setup(r100, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
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/* 15 */
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emit_draw_packet(r100, src_width, src_height,
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src_x_offset, src_y_offset,
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dst_x_offset, dst_y_offset,
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reg_width, reg_height,
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flip_y);
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radeonFlush(ctx, 0);
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/* We submitted those packets outside our state atom mechanism. Thus
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* make sure they are all resubmitted the next time. */
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r100->hw.ctx.dirty = GL_TRUE;
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r100->hw.msk.dirty = GL_TRUE;
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r100->hw.set.dirty = GL_TRUE;
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r100->hw.tex[0].dirty = GL_TRUE;
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r100->hw.txr[0].dirty = GL_TRUE;
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return GL_TRUE;
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}
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