365 lines
16 KiB
C
365 lines
16 KiB
C
/*
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* Copyright © 2021 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "nir/nir_builder.h"
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#include "radv_meta.h"
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static nir_shader *
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build_fmask_copy_compute_shader(struct radv_device *dev, int samples)
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{
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const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
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const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, false, GLSL_TYPE_FLOAT);
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nir_builder b =
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radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
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b.shader->info.workgroup_size[0] = 8;
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b.shader->info.workgroup_size[1] = 8;
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform, img_type, "out_img");
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
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nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32);
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nir_ssa_def *block_size =
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nir_imm_ivec3(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],
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b.shader->info.workgroup_size[2]);
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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/* Get coordinates. */
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nir_ssa_def *src_coord = nir_channels(&b, global_id, 0x3);
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nir_ssa_def *dst_coord = nir_vec4(&b, nir_channel(&b, src_coord, 0),
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nir_channel(&b, src_coord, 1),
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nir_ssa_undef(&b, 1, 32),
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nir_ssa_undef(&b, 1, 32));
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nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
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/* Fetch the mask for this fragment. */
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nir_tex_instr *frag_mask_fetch = nir_tex_instr_create(b.shader, 3);
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frag_mask_fetch->sampler_dim = GLSL_SAMPLER_DIM_MS;
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frag_mask_fetch->op = nir_texop_fragment_mask_fetch_amd;
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frag_mask_fetch->src[0].src_type = nir_tex_src_coord;
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frag_mask_fetch->src[0].src = nir_src_for_ssa(src_coord);
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frag_mask_fetch->src[1].src_type = nir_tex_src_lod;
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frag_mask_fetch->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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frag_mask_fetch->src[2].src_type = nir_tex_src_texture_deref;
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frag_mask_fetch->src[2].src = nir_src_for_ssa(input_img_deref);
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frag_mask_fetch->dest_type = nir_type_uint32;
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frag_mask_fetch->is_array = false;
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frag_mask_fetch->coord_components = 2;
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nir_ssa_dest_init(&frag_mask_fetch->instr, &frag_mask_fetch->dest, 1, 32, "frag_mask_fetch");
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nir_builder_instr_insert(&b, &frag_mask_fetch->instr);
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nir_ssa_def *frag_mask = &frag_mask_fetch->dest.ssa;
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/* Get the maximum sample used in this fragment. */
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nir_ssa_def *max_sample_index = nir_imm_int(&b, 0);
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for (uint32_t s = 0; s < samples; s++) {
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/* max_sample_index = MAX2(max_sample_index, (frag_mask >> (s * 4)) & 0xf) */
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max_sample_index = nir_umax(&b, max_sample_index,
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nir_ubitfield_extract(&b, frag_mask, nir_imm_int(&b, 4 * s),
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nir_imm_int(&b, 4)));
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}
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nir_variable *counter = nir_local_variable_create(b.impl, glsl_int_type(), "counter");
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nir_store_var(&b, counter, nir_imm_int(&b, 0), 0x1);
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nir_loop *loop = nir_push_loop(&b);
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{
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nir_ssa_def *sample_id = nir_load_var(&b, counter);
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nir_tex_instr *frag_fetch = nir_tex_instr_create(b.shader, 4);
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frag_fetch->sampler_dim = GLSL_SAMPLER_DIM_MS;
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frag_fetch->op = nir_texop_fragment_fetch_amd;
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frag_fetch->src[0].src_type = nir_tex_src_coord;
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frag_fetch->src[0].src = nir_src_for_ssa(src_coord);
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frag_fetch->src[1].src_type = nir_tex_src_lod;
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frag_fetch->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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frag_fetch->src[2].src_type = nir_tex_src_texture_deref;
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frag_fetch->src[2].src = nir_src_for_ssa(input_img_deref);
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frag_fetch->src[3].src_type = nir_tex_src_ms_index;
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frag_fetch->src[3].src = nir_src_for_ssa(sample_id);
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frag_fetch->dest_type = nir_type_uint32;
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frag_fetch->is_array = false;
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frag_fetch->coord_components = 2;
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nir_ssa_dest_init(&frag_fetch->instr, &frag_fetch->dest, 4, 32, "frag_fetch");
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nir_builder_instr_insert(&b, &frag_fetch->instr);
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nir_ssa_def *outval = &frag_fetch->dest.ssa;
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, dst_coord,
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sample_id, outval, nir_imm_int(&b, 0),
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.image_dim = GLSL_SAMPLER_DIM_MS);
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radv_break_on_count(&b, counter, max_sample_index);
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}
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nir_pop_loop(&b, loop);
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return b.shader;
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}
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void
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radv_device_finish_meta_fmask_copy_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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radv_DestroyPipelineLayout(radv_device_to_handle(device), state->fmask_copy.p_layout,
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&state->alloc);
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), state->fmask_copy.ds_layout,
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&state->alloc);
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
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radv_DestroyPipeline(radv_device_to_handle(device), state->fmask_copy.pipeline[i], &state->alloc);
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}
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}
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static VkResult
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create_fmask_copy_pipeline(struct radv_device *device, int samples, VkPipeline *pipeline)
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{
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struct radv_meta_state *state = &device->meta_state;
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nir_shader *cs = build_fmask_copy_compute_shader(device, samples);
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VkResult result;
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = state->fmask_copy.p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&state->cache), 1,
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&vk_pipeline_info, NULL, pipeline);
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ralloc_free(cs);
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return result;
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}
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VkResult
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radv_device_init_meta_fmask_copy_state(struct radv_device *device)
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{
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VkResult result;
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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{.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.fmask_copy.ds_layout);
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if (result != VK_SUCCESS)
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return result;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.fmask_copy.ds_layout,
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.pushConstantRangeCount = 0,
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.pPushConstantRanges = NULL
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};
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result =
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radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
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&device->meta_state.alloc, &device->meta_state.fmask_copy.p_layout);
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if (result != VK_SUCCESS)
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return result;
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) {
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uint32_t samples = 1 << i;
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result = create_fmask_copy_pipeline(device, samples, &device->meta_state.fmask_copy.pipeline[i]);
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if (result != VK_SUCCESS)
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return result;
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}
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return VK_SUCCESS;
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}
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static void
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radv_fixup_copy_dst_metadata(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_image,
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const struct radv_image *dst_image)
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{
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uint64_t src_offset, dst_offset, size;
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assert(src_image->planes[0].surface.cmask_size == dst_image->planes[0].surface.cmask_size &&
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src_image->planes[0].surface.fmask_size == dst_image->planes[0].surface.fmask_size);
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assert(src_image->planes[0].surface.fmask_offset + src_image->planes[0].surface.fmask_size ==
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src_image->planes[0].surface.cmask_offset &&
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dst_image->planes[0].surface.fmask_offset + dst_image->planes[0].surface.fmask_size ==
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dst_image->planes[0].surface.cmask_offset);
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/* Copy CMASK+FMASK. */
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size = src_image->planes[0].surface.cmask_size + src_image->planes[0].surface.fmask_size;
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src_offset = src_image->bindings[0].offset + src_image->planes[0].surface.fmask_offset;
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dst_offset = dst_image->bindings[0].offset + dst_image->planes[0].surface.fmask_offset;
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radv_copy_buffer(cmd_buffer, src_image->bindings[0].bo, dst_image->bindings[0].bo,
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src_offset, dst_offset, size);
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}
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bool
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radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer,
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const struct radv_image *src_image, const struct radv_image *dst_image,
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unsigned num_rects, const struct radv_meta_blit2d_rect *rects)
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{
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/* TODO: Test on pre GFX10 chips. */
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if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX10)
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return false;
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/* TODO: Add support for layers. */
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if (src_image->info.array_size != 1 || dst_image->info.array_size != 1)
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return false;
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/* Source/destination images must have FMASK. */
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if (!radv_image_has_fmask(src_image) || !radv_image_has_fmask(dst_image))
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return false;
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/* Source/destination images must have identical TC-compat mode. */
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if (radv_image_is_tc_compat_cmask(src_image) != radv_image_is_tc_compat_cmask(dst_image))
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return false;
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/* The region must be a whole image copy. */
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if (num_rects != 1 ||
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(rects[0].src_x || rects[0].src_y || rects[0].dst_x || rects[0].dst_y ||
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rects[0].width != src_image->info.width || rects[0].height != src_image->info.height))
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return false;
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/* Source/destination images must have identical size. */
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if (src_image->info.width != dst_image->info.width ||
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src_image->info.height != dst_image->info.height)
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return false;
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/* Source/destination images must have identical swizzle. */
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if (src_image->planes[0].surface.fmask_tile_swizzle !=
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dst_image->planes[0].surface.fmask_tile_swizzle ||
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src_image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode !=
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dst_image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode)
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return false;
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return true;
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}
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void
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radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src,
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struct radv_meta_blit2d_surf *dst)
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{
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struct radv_device *device = cmd_buffer->device;
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struct radv_image_view src_iview, dst_iview;
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uint32_t samples = src->image->info.samples;
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uint32_t samples_log2 = ffs(samples) - 1;
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
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cmd_buffer->device->meta_state.fmask_copy.pipeline[samples_log2]);
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radv_image_view_init(&src_iview, device,
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&(VkImageViewCreateInfo){
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.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
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.image = radv_image_to_handle(src->image),
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.viewType = radv_meta_get_view_type(src->image),
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.format = vk_format_no_srgb(src->image->vk.format),
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.subresourceRange =
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{
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.aspectMask = src->aspect_mask,
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.baseMipLevel = 0,
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.levelCount = 1,
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.baseArrayLayer = 0,
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.layerCount = 1,
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},
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},
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0, NULL);
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radv_image_view_init(&dst_iview, device,
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&(VkImageViewCreateInfo){
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.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
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.image = radv_image_to_handle(dst->image),
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.viewType = radv_meta_get_view_type(dst->image),
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.format = vk_format_no_srgb(dst->image->vk.format),
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.subresourceRange =
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{
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.aspectMask = dst->aspect_mask,
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.baseMipLevel = 0,
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.levelCount = 1,
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.baseArrayLayer = 0,
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.layerCount = 1,
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},
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},
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0, NULL);
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radv_meta_push_descriptor_set(
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cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
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cmd_buffer->device->meta_state.fmask_copy.p_layout, 0, /* set */
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2, /* descriptorWriteCount */
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(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.pImageInfo =
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(VkDescriptorImageInfo[]){
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{.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(&src_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL},
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}},
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{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.pImageInfo = (VkDescriptorImageInfo[]){
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{.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(&dst_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL},
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}}});
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radv_unaligned_dispatch(cmd_buffer, src->image->info.width, src->image->info.height, 1);
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/* Fixup destination image metadata by copying CMASK/FMASK from the source image. */
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radv_fixup_copy_dst_metadata(cmd_buffer, src->image, dst->image);
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}
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