843 lines
32 KiB
C
843 lines
32 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "sid.h"
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enum radv_color_op {
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FAST_CLEAR_ELIMINATE,
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FMASK_DECOMPRESS,
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DCC_DECOMPRESS,
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};
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static nir_shader *
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build_dcc_decompress_compute_shader(struct radv_device *dev)
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{
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const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
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nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_decompress_compute");
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/* We need at least 16/16/1 to cover an entire DCC block in a single workgroup. */
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b.shader->info.workgroup_size[0] = 16;
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b.shader->info.workgroup_size[1] = 16;
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_image, img_type, "in_img");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img");
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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nir_ssa_def *global_id = get_global_ids(&b, 2);
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nir_ssa_def *img_coord = nir_vec4(&b, nir_channel(&b, global_id, 0),
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nir_channel(&b, global_id, 1),
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nir_ssa_undef(&b, 1, 32),
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nir_ssa_undef(&b, 1, 32));
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nir_ssa_def *data = nir_image_deref_load(
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&b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, img_coord, nir_ssa_undef(&b, 1, 32),
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nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_2D);
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/* We need a NIR_SCOPE_DEVICE memory_scope because ACO will avoid
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* creating a vmcnt(0) because it expects the L1 cache to keep memory
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* operations in-order for the same workgroup. The vmcnt(0) seems
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* necessary however. */
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nir_scoped_barrier(&b, .execution_scope = NIR_SCOPE_WORKGROUP, .memory_scope = NIR_SCOPE_DEVICE,
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.memory_semantics = NIR_MEMORY_ACQ_REL, .memory_modes = nir_var_mem_ssbo);
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, img_coord,
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nir_ssa_undef(&b, 1, 32), data, nir_imm_int(&b, 0),
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.image_dim = GLSL_SAMPLER_DIM_2D);
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return b.shader;
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}
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static VkResult
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create_dcc_compress_compute(struct radv_device *device)
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{
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VkResult result = VK_SUCCESS;
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nir_shader *cs = build_dcc_decompress_compute_shader(device);
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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{.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(
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radv_device_to_handle(device), &ds_create_info, &device->meta_state.alloc,
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&device->meta_state.fast_clear_flush.dcc_decompress_compute_ds_layout);
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if (result != VK_SUCCESS)
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goto cleanup;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.fast_clear_flush.dcc_decompress_compute_ds_layout,
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.pushConstantRangeCount = 0,
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.pPushConstantRanges = NULL,
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};
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result = radv_CreatePipelineLayout(
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radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
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&device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout);
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if (result != VK_SUCCESS)
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goto cleanup;
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/* compute shader */
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout,
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};
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result = radv_CreateComputePipelines(
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radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
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&vk_pipeline_info, NULL,
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&device->meta_state.fast_clear_flush.dcc_decompress_compute_pipeline);
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if (result != VK_SUCCESS)
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goto cleanup;
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cleanup:
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ralloc_free(cs);
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return result;
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}
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static VkResult
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create_pipeline_layout(struct radv_device *device, VkPipelineLayout *layout)
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{
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 0,
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.pSetLayouts = NULL,
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.pushConstantRangeCount = 0,
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.pPushConstantRanges = NULL,
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};
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return radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
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&device->meta_state.alloc, layout);
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}
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static VkResult
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create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipelineLayout layout)
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{
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VkResult result;
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VkDevice device_h = radv_device_to_handle(device);
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nir_shader *fs_module = radv_meta_build_nir_fs_noop(device);
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if (!fs_module) {
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/* XXX: Need more accurate error */
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result = VK_ERROR_OUT_OF_HOST_MEMORY;
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goto cleanup;
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}
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const VkPipelineShaderStageCreateInfo stages[2] = {
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_VERTEX_BIT,
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.module = vs_module_h,
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.pName = "main",
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},
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
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.module = vk_shader_module_handle_from_nir(fs_module),
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.pName = "main",
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},
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};
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const VkPipelineVertexInputStateCreateInfo vi_state = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
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.vertexBindingDescriptionCount = 0,
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.vertexAttributeDescriptionCount = 0,
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};
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const VkPipelineInputAssemblyStateCreateInfo ia_state = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
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.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
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.primitiveRestartEnable = false,
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};
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const VkPipelineColorBlendStateCreateInfo blend_state = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
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.logicOpEnable = false,
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.attachmentCount = 1,
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.pAttachments = (VkPipelineColorBlendAttachmentState[]){
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{
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.colorWriteMask = VK_COLOR_COMPONENT_R_BIT | VK_COLOR_COMPONENT_G_BIT |
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VK_COLOR_COMPONENT_B_BIT | VK_COLOR_COMPONENT_A_BIT,
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},
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}};
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const VkPipelineRasterizationStateCreateInfo rs_state = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
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.depthClampEnable = false,
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.rasterizerDiscardEnable = false,
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.polygonMode = VK_POLYGON_MODE_FILL,
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.cullMode = VK_CULL_MODE_NONE,
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.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
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};
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const VkFormat color_format = VK_FORMAT_R8_UNORM;
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const VkPipelineRenderingCreateInfo rendering_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO,
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.colorAttachmentCount = 1,
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.pColorAttachmentFormats = &color_format,
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};
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result = radv_graphics_pipeline_create(
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device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache),
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&(VkGraphicsPipelineCreateInfo){
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.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
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.pNext = &rendering_create_info,
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.stageCount = 2,
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.pStages = stages,
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.pVertexInputState = &vi_state,
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.pInputAssemblyState = &ia_state,
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.pViewportState =
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&(VkPipelineViewportStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.viewportCount = 1,
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.scissorCount = 1,
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},
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.pRasterizationState = &rs_state,
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.pMultisampleState =
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&(VkPipelineMultisampleStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
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.rasterizationSamples = 1,
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.sampleShadingEnable = false,
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.pSampleMask = NULL,
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.alphaToCoverageEnable = false,
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.alphaToOneEnable = false,
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},
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.pColorBlendState = &blend_state,
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.pDynamicState =
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&(VkPipelineDynamicStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.dynamicStateCount = 2,
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.pDynamicStates =
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(VkDynamicState[]){
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VK_DYNAMIC_STATE_VIEWPORT,
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VK_DYNAMIC_STATE_SCISSOR,
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},
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},
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.layout = layout,
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.renderPass = VK_NULL_HANDLE,
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.subpass = 0,
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},
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&(struct radv_graphics_pipeline_create_info){
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.use_rectlist = true,
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.custom_blend_mode = V_028808_CB_ELIMINATE_FAST_CLEAR,
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},
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&device->meta_state.alloc, &device->meta_state.fast_clear_flush.cmask_eliminate_pipeline);
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if (result != VK_SUCCESS)
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goto cleanup;
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result = radv_graphics_pipeline_create(
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device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache),
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&(VkGraphicsPipelineCreateInfo){
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.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
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.pNext = &rendering_create_info,
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.stageCount = 2,
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.pStages = stages,
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.pVertexInputState = &vi_state,
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.pInputAssemblyState = &ia_state,
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.pViewportState =
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&(VkPipelineViewportStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.viewportCount = 1,
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.scissorCount = 1,
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},
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.pRasterizationState = &rs_state,
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.pMultisampleState =
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&(VkPipelineMultisampleStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
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.rasterizationSamples = 1,
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.sampleShadingEnable = false,
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.pSampleMask = NULL,
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.alphaToCoverageEnable = false,
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.alphaToOneEnable = false,
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},
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.pColorBlendState = &blend_state,
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.pDynamicState =
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&(VkPipelineDynamicStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.dynamicStateCount = 2,
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.pDynamicStates =
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(VkDynamicState[]){
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VK_DYNAMIC_STATE_VIEWPORT,
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VK_DYNAMIC_STATE_SCISSOR,
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},
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},
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.layout = layout,
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.renderPass = VK_NULL_HANDLE,
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.subpass = 0,
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},
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&(struct radv_graphics_pipeline_create_info){
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.use_rectlist = true,
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.custom_blend_mode = V_028808_CB_FMASK_DECOMPRESS,
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},
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&device->meta_state.alloc, &device->meta_state.fast_clear_flush.fmask_decompress_pipeline);
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if (result != VK_SUCCESS)
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goto cleanup;
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result = radv_graphics_pipeline_create(
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device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache),
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&(VkGraphicsPipelineCreateInfo){
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.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
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.pNext = &rendering_create_info,
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.stageCount = 2,
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.pStages = stages,
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.pVertexInputState = &vi_state,
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.pInputAssemblyState = &ia_state,
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.pViewportState =
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&(VkPipelineViewportStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.viewportCount = 1,
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.scissorCount = 1,
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},
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.pRasterizationState = &rs_state,
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.pMultisampleState =
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&(VkPipelineMultisampleStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
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.rasterizationSamples = 1,
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.sampleShadingEnable = false,
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.pSampleMask = NULL,
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.alphaToCoverageEnable = false,
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.alphaToOneEnable = false,
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},
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.pColorBlendState = &blend_state,
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.pDynamicState =
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&(VkPipelineDynamicStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.dynamicStateCount = 2,
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.pDynamicStates =
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(VkDynamicState[]){
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VK_DYNAMIC_STATE_VIEWPORT,
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VK_DYNAMIC_STATE_SCISSOR,
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},
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},
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.layout = layout,
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.renderPass = VK_NULL_HANDLE,
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.subpass = 0,
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},
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&(struct radv_graphics_pipeline_create_info){
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.use_rectlist = true,
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.custom_blend_mode = device->physical_device->rad_info.gfx_level >= GFX11
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? V_028808_CB_DCC_DECOMPRESS_GFX11
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: V_028808_CB_DCC_DECOMPRESS_GFX8,
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},
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&device->meta_state.alloc, &device->meta_state.fast_clear_flush.dcc_decompress_pipeline);
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if (result != VK_SUCCESS)
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goto cleanup;
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cleanup:
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ralloc_free(fs_module);
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return result;
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}
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void
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radv_device_finish_meta_fast_clear_flush_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->fast_clear_flush.dcc_decompress_pipeline, &state->alloc);
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->fast_clear_flush.fmask_decompress_pipeline, &state->alloc);
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->fast_clear_flush.cmask_eliminate_pipeline, &state->alloc);
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radv_DestroyPipelineLayout(radv_device_to_handle(device), state->fast_clear_flush.p_layout,
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&state->alloc);
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->fast_clear_flush.dcc_decompress_compute_pipeline, &state->alloc);
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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state->fast_clear_flush.dcc_decompress_compute_p_layout,
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&state->alloc);
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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state->fast_clear_flush.dcc_decompress_compute_ds_layout,
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&state->alloc);
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}
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static VkResult
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radv_device_init_meta_fast_clear_flush_state_internal(struct radv_device *device)
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{
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VkResult res = VK_SUCCESS;
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mtx_lock(&device->meta_state.mtx);
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if (device->meta_state.fast_clear_flush.cmask_eliminate_pipeline) {
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mtx_unlock(&device->meta_state.mtx);
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return VK_SUCCESS;
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}
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nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
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if (!vs_module) {
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/* XXX: Need more accurate error */
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res = VK_ERROR_OUT_OF_HOST_MEMORY;
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goto cleanup;
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}
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res = create_pipeline_layout(device, &device->meta_state.fast_clear_flush.p_layout);
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if (res != VK_SUCCESS)
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goto cleanup;
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|
VkShaderModule vs_module_h = vk_shader_module_handle_from_nir(vs_module);
|
|
res = create_pipeline(device, vs_module_h, device->meta_state.fast_clear_flush.p_layout);
|
|
if (res != VK_SUCCESS)
|
|
goto cleanup;
|
|
|
|
res = create_dcc_compress_compute(device);
|
|
if (res != VK_SUCCESS)
|
|
goto cleanup;
|
|
|
|
cleanup:
|
|
ralloc_free(vs_module);
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
|
|
return res;
|
|
}
|
|
|
|
VkResult
|
|
radv_device_init_meta_fast_clear_flush_state(struct radv_device *device, bool on_demand)
|
|
{
|
|
if (on_demand)
|
|
return VK_SUCCESS;
|
|
|
|
return radv_device_init_meta_fast_clear_flush_state_internal(device);
|
|
}
|
|
|
|
static void
|
|
radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radv_image *image, uint64_t pred_offset,
|
|
bool value)
|
|
{
|
|
uint64_t va = 0;
|
|
|
|
if (value) {
|
|
va = radv_buffer_get_va(image->bindings[0].bo) + image->bindings[0].offset;
|
|
va += pred_offset;
|
|
}
|
|
|
|
si_emit_set_predication_state(cmd_buffer, true, PREDICATION_OP_BOOL64, va);
|
|
}
|
|
|
|
static void
|
|
radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
const VkImageSubresourceRange *range, int level, int layer,
|
|
bool flush_cb)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
struct radv_image_view iview;
|
|
uint32_t width, height;
|
|
|
|
width = radv_minify(image->info.width, range->baseMipLevel + level);
|
|
height = radv_minify(image->info.height, range->baseMipLevel + level);
|
|
|
|
radv_image_view_init(&iview, device,
|
|
&(VkImageViewCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(image),
|
|
.viewType = radv_meta_get_view_type(image),
|
|
.format = image->vk.format,
|
|
.subresourceRange =
|
|
{
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
.baseMipLevel = range->baseMipLevel + level,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = range->baseArrayLayer + layer,
|
|
.layerCount = 1,
|
|
},
|
|
},
|
|
0, NULL);
|
|
|
|
const VkRenderingAttachmentInfo color_att = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
|
|
.imageView = radv_image_view_to_handle(&iview),
|
|
.imageLayout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL,
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
};
|
|
|
|
const VkRenderingInfo rendering_info = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
|
|
.renderArea = {
|
|
.offset = { 0, 0 },
|
|
.extent = { width, height }
|
|
},
|
|
.layerCount = 1,
|
|
.colorAttachmentCount = 1,
|
|
.pColorAttachments = &color_att,
|
|
};
|
|
|
|
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
|
|
|
|
if (flush_cb)
|
|
cmd_buffer->state.flush_bits |=
|
|
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, image);
|
|
|
|
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
|
|
|
|
if (flush_cb)
|
|
cmd_buffer->state.flush_bits |=
|
|
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, image);
|
|
|
|
radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer));
|
|
|
|
radv_image_view_finish(&iview);
|
|
}
|
|
|
|
static void
|
|
radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
const VkImageSubresourceRange *subresourceRange, enum radv_color_op op)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
struct radv_meta_saved_state saved_state;
|
|
bool old_predicating = false;
|
|
bool flush_cb = false;
|
|
uint64_t pred_offset;
|
|
VkPipeline *pipeline;
|
|
|
|
switch (op) {
|
|
case FAST_CLEAR_ELIMINATE:
|
|
pipeline = &device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
|
|
pred_offset = image->fce_pred_offset;
|
|
break;
|
|
case FMASK_DECOMPRESS:
|
|
pipeline = &device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
|
|
pred_offset = 0; /* FMASK_DECOMPRESS is never predicated. */
|
|
|
|
/* Flushing CB is required before and after FMASK_DECOMPRESS. */
|
|
flush_cb = true;
|
|
break;
|
|
case DCC_DECOMPRESS:
|
|
pipeline = &device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
|
|
pred_offset = image->dcc_pred_offset;
|
|
|
|
/* Flushing CB is required before and after DCC_DECOMPRESS. */
|
|
flush_cb = true;
|
|
break;
|
|
default:
|
|
unreachable("Invalid color op");
|
|
}
|
|
|
|
if (radv_dcc_enabled(image, subresourceRange->baseMipLevel) &&
|
|
(image->info.array_size != radv_get_layerCount(image, subresourceRange) ||
|
|
subresourceRange->baseArrayLayer != 0)) {
|
|
/* Only use predication if the image has DCC with mipmaps or
|
|
* if the range of layers covers the whole image because the
|
|
* predication is based on mip level.
|
|
*/
|
|
pred_offset = 0;
|
|
}
|
|
|
|
if (!*pipeline) {
|
|
VkResult ret;
|
|
|
|
ret = radv_device_init_meta_fast_clear_flush_state_internal(device);
|
|
if (ret != VK_SUCCESS) {
|
|
cmd_buffer->record_result = ret;
|
|
return;
|
|
}
|
|
}
|
|
|
|
radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_PASS);
|
|
|
|
if (pred_offset) {
|
|
pred_offset += 8 * subresourceRange->baseMipLevel;
|
|
|
|
old_predicating = cmd_buffer->state.predicating;
|
|
|
|
radv_emit_set_predication_state_from_image(cmd_buffer, image, pred_offset, true);
|
|
cmd_buffer->state.predicating = true;
|
|
}
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
*pipeline);
|
|
|
|
for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) {
|
|
uint32_t width, height;
|
|
|
|
/* Do not decompress levels without DCC. */
|
|
if (op == DCC_DECOMPRESS && !radv_dcc_enabled(image, subresourceRange->baseMipLevel + l))
|
|
continue;
|
|
|
|
width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
|
|
height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
|
|
|
|
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
|
|
&(VkViewport){.x = 0,
|
|
.y = 0,
|
|
.width = width,
|
|
.height = height,
|
|
.minDepth = 0.0f,
|
|
.maxDepth = 1.0f});
|
|
|
|
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
|
|
&(VkRect2D){
|
|
.offset = {0, 0},
|
|
.extent = {width, height},
|
|
});
|
|
|
|
for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
|
|
radv_process_color_image_layer(cmd_buffer, image, subresourceRange, l, s, flush_cb);
|
|
}
|
|
}
|
|
|
|
cmd_buffer->state.flush_bits |=
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
|
|
|
|
if (pred_offset) {
|
|
pred_offset += 8 * subresourceRange->baseMipLevel;
|
|
|
|
cmd_buffer->state.predicating = old_predicating;
|
|
|
|
radv_emit_set_predication_state_from_image(cmd_buffer, image, pred_offset, false);
|
|
|
|
if (cmd_buffer->state.predication_type != -1) {
|
|
/* Restore previous conditional rendering user state. */
|
|
si_emit_set_predication_state(cmd_buffer, cmd_buffer->state.predication_type,
|
|
cmd_buffer->state.predication_op,
|
|
cmd_buffer->state.predication_va);
|
|
}
|
|
}
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
|
|
/* Clear the image's fast-clear eliminate predicate because FMASK_DECOMPRESS and DCC_DECOMPRESS
|
|
* also perform a fast-clear eliminate.
|
|
*/
|
|
radv_update_fce_metadata(cmd_buffer, image, subresourceRange, false);
|
|
|
|
/* Mark the image as being decompressed. */
|
|
if (op == DCC_DECOMPRESS)
|
|
radv_update_dcc_metadata(cmd_buffer, image, subresourceRange, false);
|
|
}
|
|
|
|
static void
|
|
radv_fast_clear_eliminate(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
const VkImageSubresourceRange *subresourceRange)
|
|
{
|
|
struct radv_barrier_data barrier = {0};
|
|
|
|
barrier.layout_transitions.fast_clear_eliminate = 1;
|
|
radv_describe_layout_transition(cmd_buffer, &barrier);
|
|
|
|
radv_process_color_image(cmd_buffer, image, subresourceRange, FAST_CLEAR_ELIMINATE);
|
|
}
|
|
|
|
static void
|
|
radv_fmask_decompress(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
const VkImageSubresourceRange *subresourceRange)
|
|
{
|
|
struct radv_barrier_data barrier = {0};
|
|
|
|
barrier.layout_transitions.fmask_decompress = 1;
|
|
radv_describe_layout_transition(cmd_buffer, &barrier);
|
|
|
|
radv_process_color_image(cmd_buffer, image, subresourceRange, FMASK_DECOMPRESS);
|
|
}
|
|
|
|
void
|
|
radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
const VkImageSubresourceRange *subresourceRange)
|
|
{
|
|
if (radv_image_has_fmask(image) && !image->tc_compatible_cmask) {
|
|
if (radv_image_has_dcc(image) && radv_image_has_cmask(image)) {
|
|
/* MSAA images with DCC and CMASK might have been fast-cleared and might require a FCE but
|
|
* FMASK_DECOMPRESS can't eliminate DCC fast clears.
|
|
*/
|
|
radv_fast_clear_eliminate(cmd_buffer, image, subresourceRange);
|
|
}
|
|
|
|
radv_fmask_decompress(cmd_buffer, image, subresourceRange);
|
|
} else {
|
|
/* Skip fast clear eliminate for images that support comp-to-single fast clears. */
|
|
if (image->support_comp_to_single)
|
|
return;
|
|
|
|
radv_fast_clear_eliminate(cmd_buffer, image, subresourceRange);
|
|
}
|
|
}
|
|
|
|
static void
|
|
radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
const VkImageSubresourceRange *subresourceRange)
|
|
{
|
|
struct radv_meta_saved_state saved_state;
|
|
struct radv_image_view load_iview = {0};
|
|
struct radv_image_view store_iview = {0};
|
|
struct radv_device *device = cmd_buffer->device;
|
|
|
|
cmd_buffer->state.flush_bits |=
|
|
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
|
|
|
|
if (!cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline) {
|
|
VkResult ret = radv_device_init_meta_fast_clear_flush_state_internal(cmd_buffer->device);
|
|
if (ret != VK_SUCCESS) {
|
|
cmd_buffer->record_result = ret;
|
|
return;
|
|
}
|
|
}
|
|
|
|
radv_meta_save(&saved_state, cmd_buffer,
|
|
RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE);
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
device->meta_state.fast_clear_flush.dcc_decompress_compute_pipeline);
|
|
|
|
for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) {
|
|
uint32_t width, height;
|
|
|
|
/* Do not decompress levels without DCC. */
|
|
if (!radv_dcc_enabled(image, subresourceRange->baseMipLevel + l))
|
|
continue;
|
|
|
|
width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
|
|
height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
|
|
|
|
for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
|
|
radv_image_view_init(
|
|
&load_iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(image),
|
|
.viewType = VK_IMAGE_VIEW_TYPE_2D,
|
|
.format = image->vk.format,
|
|
.subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
.baseMipLevel = subresourceRange->baseMipLevel + l,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = subresourceRange->baseArrayLayer + s,
|
|
.layerCount = 1},
|
|
},
|
|
0, &(struct radv_image_view_extra_create_info){.enable_compression = true});
|
|
radv_image_view_init(
|
|
&store_iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(image),
|
|
.viewType = VK_IMAGE_VIEW_TYPE_2D,
|
|
.format = image->vk.format,
|
|
.subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
.baseMipLevel = subresourceRange->baseMipLevel + l,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = subresourceRange->baseArrayLayer + s,
|
|
.layerCount = 1},
|
|
},
|
|
0, &(struct radv_image_view_extra_create_info){.disable_compression = true});
|
|
|
|
radv_meta_push_descriptor_set(
|
|
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout, 0, /* set */
|
|
2, /* descriptorWriteCount */
|
|
(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
.dstBinding = 0,
|
|
.dstArrayElement = 0,
|
|
.descriptorCount = 1,
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
.pImageInfo =
|
|
(VkDescriptorImageInfo[]){
|
|
{
|
|
.sampler = VK_NULL_HANDLE,
|
|
.imageView = radv_image_view_to_handle(&load_iview),
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
}},
|
|
{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
.dstBinding = 1,
|
|
.dstArrayElement = 0,
|
|
.descriptorCount = 1,
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
.pImageInfo = (VkDescriptorImageInfo[]){
|
|
{
|
|
.sampler = VK_NULL_HANDLE,
|
|
.imageView = radv_image_view_to_handle(&store_iview),
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
}}});
|
|
|
|
radv_unaligned_dispatch(cmd_buffer, width, height, 1);
|
|
|
|
radv_image_view_finish(&load_iview);
|
|
radv_image_view_finish(&store_iview);
|
|
}
|
|
}
|
|
|
|
/* Mark this image as actually being decompressed. */
|
|
radv_update_dcc_metadata(cmd_buffer, image, subresourceRange, false);
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
|
|
cmd_buffer->state.flush_bits |=
|
|
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
|
|
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
|
|
|
|
/* Initialize the DCC metadata as "fully expanded". */
|
|
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, subresourceRange, 0xffffffff);
|
|
}
|
|
|
|
void
|
|
radv_decompress_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
|
|
const VkImageSubresourceRange *subresourceRange)
|
|
{
|
|
struct radv_barrier_data barrier = {0};
|
|
|
|
barrier.layout_transitions.dcc_decompress = 1;
|
|
radv_describe_layout_transition(cmd_buffer, &barrier);
|
|
|
|
if (cmd_buffer->qf == RADV_QUEUE_GENERAL)
|
|
radv_process_color_image(cmd_buffer, image, subresourceRange, DCC_DECOMPRESS);
|
|
else
|
|
radv_decompress_dcc_compute(cmd_buffer, image, subresourceRange);
|
|
}
|