287 lines
13 KiB
C
287 lines
13 KiB
C
/*
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* Copyright © 2021 Google
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#define AC_SURFACE_INCLUDE_NIR
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#include "ac_surface.h"
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#include "radv_meta.h"
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#include "radv_private.h"
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static nir_shader *
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build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *surf)
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{
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enum glsl_sampler_dim dim = GLSL_SAMPLER_DIM_BUF;
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const struct glsl_type *buf_type = glsl_image_type(dim, false, GLSL_TYPE_UINT);
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nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_retile_compute");
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b.shader->info.workgroup_size[0] = 8;
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b.shader->info.workgroup_size[1] = 8;
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nir_ssa_def *src_dcc_size = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
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nir_ssa_def *src_dcc_pitch = nir_channels(&b, src_dcc_size, 1);
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nir_ssa_def *src_dcc_height = nir_channels(&b, src_dcc_size, 2);
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nir_ssa_def *dst_dcc_size = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range = 8);
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nir_ssa_def *dst_dcc_pitch = nir_channels(&b, dst_dcc_size, 1);
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nir_ssa_def *dst_dcc_height = nir_channels(&b, dst_dcc_size, 2);
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nir_variable *input_dcc = nir_variable_create(b.shader, nir_var_uniform, buf_type, "dcc_in");
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input_dcc->data.descriptor_set = 0;
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input_dcc->data.binding = 0;
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nir_variable *output_dcc = nir_variable_create(b.shader, nir_var_uniform, buf_type, "dcc_out");
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output_dcc->data.descriptor_set = 0;
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output_dcc->data.binding = 1;
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nir_ssa_def *input_dcc_ref = &nir_build_deref_var(&b, input_dcc)->dest.ssa;
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nir_ssa_def *output_dcc_ref = &nir_build_deref_var(&b, output_dcc)->dest.ssa;
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nir_ssa_def *coord = get_global_ids(&b, 2);
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nir_ssa_def *zero = nir_imm_int(&b, 0);
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coord = nir_imul(
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&b, coord,
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nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height));
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nir_ssa_def *src = ac_nir_dcc_addr_from_coord(&b, &dev->physical_device->rad_info, surf->bpe,
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&surf->u.gfx9.color.dcc_equation, src_dcc_pitch,
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src_dcc_height, zero, nir_channel(&b, coord, 0),
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nir_channel(&b, coord, 1), zero, zero, zero);
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nir_ssa_def *dst = ac_nir_dcc_addr_from_coord(
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&b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
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dst_dcc_pitch, dst_dcc_height, zero, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1),
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zero, zero, zero);
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nir_ssa_def *dcc_val = nir_image_deref_load(&b, 1, 32, input_dcc_ref,
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nir_vec4(&b, src, src, src, src),
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nir_ssa_undef(&b, 1, 32), nir_imm_int(&b, 0),
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.image_dim = dim);
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nir_image_deref_store(&b, output_dcc_ref, nir_vec4(&b, dst, dst, dst, dst),
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nir_ssa_undef(&b, 1, 32), dcc_val, nir_imm_int(&b, 0), .image_dim = dim);
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return b.shader;
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}
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void
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radv_device_finish_meta_dcc_retile_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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for (unsigned i = 0; i < ARRAY_SIZE(state->dcc_retile.pipeline); i++) {
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radv_DestroyPipeline(radv_device_to_handle(device), state->dcc_retile.pipeline[i],
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&state->alloc);
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}
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radv_DestroyPipelineLayout(radv_device_to_handle(device), state->dcc_retile.p_layout,
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&state->alloc);
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), state->dcc_retile.ds_layout,
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&state->alloc);
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/* Reset for next finish. */
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memset(&state->dcc_retile, 0, sizeof(state->dcc_retile));
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}
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/*
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* This take a surface, but the only things used are:
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* - BPE
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* - DCC equations
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* - DCC block size
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*
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* BPE is always 4 at the moment and the rest is derived from the tilemode.
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*/
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static VkResult
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radv_device_init_meta_dcc_retile_state(struct radv_device *device, struct radeon_surf *surf)
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{
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VkResult result = VK_SUCCESS;
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nir_shader *cs = build_dcc_retile_compute_shader(device, surf);
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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{.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.dcc_retile.ds_layout);
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if (result != VK_SUCCESS)
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goto cleanup;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.dcc_retile.ds_layout,
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.pushConstantRangeCount = 1,
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.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
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};
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result =
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radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
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&device->meta_state.alloc, &device->meta_state.dcc_retile.p_layout);
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if (result != VK_SUCCESS)
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goto cleanup;
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/* compute shader */
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.dcc_retile.p_layout,
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};
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result = radv_CreateComputePipelines(
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radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
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&vk_pipeline_info, NULL, &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]);
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if (result != VK_SUCCESS)
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goto cleanup;
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cleanup:
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ralloc_free(cs);
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return result;
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}
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void
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radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
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{
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struct radv_meta_saved_state saved_state;
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struct radv_device *device = cmd_buffer->device;
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struct radv_buffer buffer;
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assert(image->vk.image_type == VK_IMAGE_TYPE_2D);
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assert(image->info.array_size == 1 && image->info.levels == 1);
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struct radv_cmd_state *state = &cmd_buffer->state;
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state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, image) |
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radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
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unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode;
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/* Compile pipelines if not already done so. */
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if (!cmd_buffer->device->meta_state.dcc_retile.pipeline[swizzle_mode]) {
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VkResult ret =
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radv_device_init_meta_dcc_retile_state(cmd_buffer->device, &image->planes[0].surface);
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if (ret != VK_SUCCESS) {
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cmd_buffer->record_result = ret;
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return;
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}
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}
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radv_meta_save(
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&saved_state, cmd_buffer,
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RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.dcc_retile.pipeline[swizzle_mode]);
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radv_buffer_init(&buffer, device, image->bindings[0].bo, image->size, image->bindings[0].offset);
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struct radv_buffer_view views[2];
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VkBufferView view_handles[2];
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radv_buffer_view_init(views, cmd_buffer->device,
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&(VkBufferViewCreateInfo){
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.sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
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.buffer = radv_buffer_to_handle(&buffer),
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.offset = image->planes[0].surface.meta_offset,
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.range = image->planes[0].surface.meta_size,
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.format = VK_FORMAT_R8_UINT,
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});
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radv_buffer_view_init(views + 1, cmd_buffer->device,
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&(VkBufferViewCreateInfo){
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.sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
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.buffer = radv_buffer_to_handle(&buffer),
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.offset = image->planes[0].surface.display_dcc_offset,
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.range = image->planes[0].surface.u.gfx9.color.display_dcc_size,
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.format = VK_FORMAT_R8_UINT,
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});
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for (unsigned i = 0; i < 2; ++i)
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view_handles[i] = radv_buffer_view_to_handle(&views[i]);
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radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.dcc_retile.p_layout, 0, /* set */
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2, /* descriptorWriteCount */
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(VkWriteDescriptorSet[]){
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
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.pTexelBufferView = &view_handles[0],
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},
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
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.pTexelBufferView = &view_handles[1],
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},
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});
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unsigned width = DIV_ROUND_UP(image->info.width, vk_format_get_blockwidth(image->vk.format));
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unsigned height = DIV_ROUND_UP(image->info.height, vk_format_get_blockheight(image->vk.format));
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unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width);
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unsigned dcc_height =
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DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height);
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uint32_t constants[] = {
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image->planes[0].surface.u.gfx9.color.dcc_pitch_max + 1,
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image->planes[0].surface.u.gfx9.color.dcc_height,
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image->planes[0].surface.u.gfx9.color.display_dcc_pitch_max + 1,
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image->planes[0].surface.u.gfx9.color.display_dcc_height,
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};
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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device->meta_state.dcc_retile.p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
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constants);
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radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, 1);
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radv_buffer_view_finish(views);
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radv_buffer_view_finish(views + 1);
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radv_buffer_finish(&buffer);
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radv_meta_restore(&saved_state, cmd_buffer);
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state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
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radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
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}
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