290 lines
10 KiB
C
290 lines
10 KiB
C
/*
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* Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
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* Copyright © 2018-2019 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include <stdio.h>
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#include "freedreno_layout.h"
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static bool
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is_r8g8(const struct fdl_layout *layout)
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{
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return layout->cpp == 2 &&
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util_format_get_nr_components(layout->format) == 2;
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}
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void
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fdl6_get_ubwc_blockwidth(const struct fdl_layout *layout,
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uint32_t *blockwidth, uint32_t *blockheight)
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{
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static const struct {
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uint8_t width;
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uint8_t height;
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} blocksize[] = {
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{ 16, 4 }, /* cpp = 1 */
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{ 16, 4 }, /* cpp = 2 */
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{ 16, 4 }, /* cpp = 4 */
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{ 8, 4 }, /* cpp = 8 */
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{ 4, 4 }, /* cpp = 16 */
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{ 4, 2 }, /* cpp = 32 */
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{ 0, 0 }, /* cpp = 64 (TODO) */
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};
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/* special case for r8g8: */
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if (is_r8g8(layout)) {
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*blockwidth = 16;
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*blockheight = 8;
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return;
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} else if (layout->format == PIPE_FORMAT_Y8_UNORM) {
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*blockwidth = 32;
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*blockheight = 8;
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return;
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}
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uint32_t cpp = fdl_cpp_shift(layout);
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assert(cpp < ARRAY_SIZE(blocksize));
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*blockwidth = blocksize[cpp].width;
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*blockheight = blocksize[cpp].height;
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}
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static void
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fdl6_tile_alignment(struct fdl_layout *layout, uint32_t *heightalign)
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{
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layout->pitchalign = fdl_cpp_shift(layout);
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*heightalign = 16;
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if (is_r8g8(layout) || layout->cpp == 1) {
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layout->pitchalign = 1;
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*heightalign = 32;
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} else if (layout->cpp == 2) {
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layout->pitchalign = 2;
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}
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/* note: this base_align is *probably* not always right,
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* it doesn't really get tested. for example with UBWC we might
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* want 4k alignment, since we align UBWC levels to 4k
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*/
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if (layout->cpp == 1)
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layout->base_align = 64;
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else if (layout->cpp == 2)
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layout->base_align = 128;
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else
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layout->base_align = 256;
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}
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/* NOTE: good way to test this is: (for example)
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* piglit/bin/texelFetch fs sampler3D 100x100x8
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*/
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bool
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fdl6_layout(struct fdl_layout *layout, enum pipe_format format,
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uint32_t nr_samples, uint32_t width0, uint32_t height0,
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uint32_t depth0, uint32_t mip_levels, uint32_t array_size,
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bool is_3d, struct fdl_explicit_layout *explicit_layout)
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{
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uint32_t offset = 0, heightalign;
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uint32_t ubwc_blockwidth, ubwc_blockheight;
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assert(nr_samples > 0);
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layout->width0 = width0;
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layout->height0 = height0;
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layout->depth0 = depth0;
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layout->mip_levels = mip_levels;
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layout->cpp = util_format_get_blocksize(format);
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layout->cpp *= nr_samples;
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layout->cpp_shift = ffs(layout->cpp) - 1;
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layout->format = format;
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layout->nr_samples = nr_samples;
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layout->layer_first = !is_3d;
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fdl6_get_ubwc_blockwidth(layout, &ubwc_blockwidth, &ubwc_blockheight);
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if (depth0 > 1 || ubwc_blockwidth == 0)
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layout->ubwc = false;
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if (layout->ubwc || util_format_is_depth_or_stencil(format))
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layout->tile_all = true;
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/* in layer_first layout, the level (slice) contains just one
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* layer (since in fact the layer contains the slices)
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*/
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uint32_t layers_in_level = layout->layer_first ? 1 : array_size;
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/* note: for tiled+noubwc layouts, we can use a lower pitchalign
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* which will affect the linear levels only, (the hardware will still
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* expect the tiled alignment on the tiled levels)
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*/
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if (layout->tile_mode) {
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fdl6_tile_alignment(layout, &heightalign);
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} else {
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layout->base_align = 64;
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layout->pitchalign = 0;
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/* align pitch to at least 16 pixels:
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* both turnip and galium assume there is enough alignment for 16x4
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* aligned gmem store. turnip can use CP_BLIT to work without this
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* extra alignment, but gallium driver doesn't implement it yet
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*/
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if (layout->cpp > 4)
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layout->pitchalign = fdl_cpp_shift(layout) - 2;
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/* when possible, use a bit more alignment than necessary
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* presumably this is better for performance?
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*/
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if (!explicit_layout)
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layout->pitchalign = fdl_cpp_shift(layout);
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/* not used, avoid "may be used uninitialized" warning */
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heightalign = 1;
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}
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fdl_set_pitchalign(layout, layout->pitchalign + 6);
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if (explicit_layout) {
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offset = explicit_layout->offset;
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layout->pitch0 = explicit_layout->pitch;
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if (align(layout->pitch0, 1 << layout->pitchalign) != layout->pitch0)
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return false;
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}
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uint32_t ubwc_width0 = width0;
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uint32_t ubwc_height0 = height0;
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uint32_t ubwc_tile_height_alignment = RGB_TILE_HEIGHT_ALIGNMENT;
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if (mip_levels > 1) {
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/* With mipmapping enabled, UBWC layout is power-of-two sized,
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* specified in log2 width/height in the descriptors. The height
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* alignment is 64 for mipmapping, but for buffer sharing (always
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* single level) other participants expect 16.
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*/
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ubwc_width0 = util_next_power_of_two(width0);
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ubwc_height0 = util_next_power_of_two(height0);
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ubwc_tile_height_alignment = 64;
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}
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layout->ubwc_width0 = align(DIV_ROUND_UP(ubwc_width0, ubwc_blockwidth),
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RGB_TILE_WIDTH_ALIGNMENT);
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ubwc_height0 = align(DIV_ROUND_UP(ubwc_height0, ubwc_blockheight),
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ubwc_tile_height_alignment);
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uint32_t min_3d_layer_size = 0;
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for (uint32_t level = 0; level < mip_levels; level++) {
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uint32_t depth = u_minify(depth0, level);
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struct fdl_slice *slice = &layout->slices[level];
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struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
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uint32_t tile_mode = fdl_tile_mode(layout, level);
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uint32_t pitch = fdl_pitch(layout, level);
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uint32_t height = u_minify(height0, level);
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uint32_t nblocksy = util_format_get_nblocksy(format, height);
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if (tile_mode)
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nblocksy = align(nblocksy, heightalign);
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/* The blits used for mem<->gmem work at a granularity of
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* 16x4, which can cause faults due to over-fetch on the
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* last level. The simple solution is to over-allocate a
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* bit the last level to ensure any over-fetch is harmless.
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* The pitch is already sufficiently aligned, but height
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* may not be. note this only matters if last level is linear
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*/
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if (level == mip_levels - 1)
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nblocksy = align(nblocksy, 4);
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slice->offset = offset + layout->size;
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/* 1d array and 2d array textures must all have the same layer size for
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* each miplevel on a6xx. For 3D, the layer size automatically reduces
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* until the value we specify in TEX_CONST_3_MIN_LAYERSZ, which is used to
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* make sure that we follow alignment requirements after minification.
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*/
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if (is_3d) {
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if (level == 0) {
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slice->size0 = align(nblocksy * pitch, 4096);
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} else if (min_3d_layer_size) {
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slice->size0 = min_3d_layer_size;
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} else {
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/* Note: level * 2 for minifying in both X and Y. */
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slice->size0 = u_minify(layout->slices[0].size0, level * 2);
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/* If this level didn't reduce the pitch by half, then fix it up,
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* and this is the end of layer size reduction.
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*/
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uint32_t pitch = fdl_pitch(layout, level);
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if (pitch != fdl_pitch(layout, level - 1) / 2)
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min_3d_layer_size = slice->size0 = nblocksy * pitch;
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/* If the height is now less than the alignment requirement, then
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* scale it up and let this be the minimum layer size.
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*/
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if (tile_mode && util_format_get_nblocksy(format, height) < heightalign)
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min_3d_layer_size = slice->size0 = nblocksy * pitch;
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/* If the size would become un-page-aligned, stay aligned instead. */
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if (align(slice->size0, 4096) != slice->size0)
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min_3d_layer_size = slice->size0 = align(slice->size0, 4096);
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}
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} else {
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slice->size0 = nblocksy * pitch;
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}
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layout->size += slice->size0 * depth * layers_in_level;
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if (layout->ubwc) {
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/* with UBWC every level is aligned to 4K */
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layout->size = align(layout->size, 4096);
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uint32_t meta_pitch = fdl_ubwc_pitch(layout, level);
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uint32_t meta_height =
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align(u_minify(ubwc_height0, level), ubwc_tile_height_alignment);
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ubwc_slice->size0 =
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align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT);
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ubwc_slice->offset = offset + layout->ubwc_layer_size;
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layout->ubwc_layer_size += ubwc_slice->size0;
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}
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}
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if (layout->layer_first) {
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layout->layer_size = align(layout->size, 4096);
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layout->size = layout->layer_size * array_size;
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}
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/* Place the UBWC slices before the uncompressed slices, because the
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* kernel expects UBWC to be at the start of the buffer. In the HW, we
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* get to program the UBWC and non-UBWC offset/strides
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* independently.
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*/
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if (layout->ubwc) {
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for (uint32_t level = 0; level < mip_levels; level++)
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layout->slices[level].offset += layout->ubwc_layer_size * array_size;
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layout->size += layout->ubwc_layer_size * array_size;
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}
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/* include explicit offset in size */
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layout->size += offset;
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return true;
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}
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