651 lines
19 KiB
C
651 lines
19 KiB
C
/*
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Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
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The Weather Channel (TM) funded Tungsten Graphics to develop the
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initial release of the Radeon 8500 driver under the XFree86 license.
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This notice must be preserved.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keithw@vmware.com>
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*/
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#ifndef __R200_CONTEXT_H__
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#define __R200_CONTEXT_H__
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#include "tnl/t_vertex.h"
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#include "drm-uapi/drm.h"
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#include "radeon_drm.h"
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#include "dri_util.h"
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#include "main/macros.h"
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#include "main/mtypes.h"
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#include "r200_reg.h"
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#include "r200_vertprog.h"
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#ifndef R200_EMIT_VAP_PVS_CNTL
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#error This driver requires a newer libdrm to compile
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#endif
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#include "radeon_screen.h"
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#include "radeon_common.h"
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struct r200_context;
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typedef struct r200_context r200ContextRec;
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typedef struct r200_context *r200ContextPtr;
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struct r200_vertex_program {
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struct gl_program mesa_program; /* Must be first */
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int translated;
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/* need excess instr: 1 for late loop checking, 2 for
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additional instr due to instr/attr, 3 for fog */
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VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6];
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int pos_end;
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int inputs[VERT_ATTRIB_MAX];
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GLubyte inputmap_rev[16];
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int native;
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int fogpidx;
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int fogmode;
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};
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#define R200_TEX_ALL 0x3f
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struct r200_texture_env_state {
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radeonTexObjPtr texobj;
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GLuint outputreg;
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GLuint unitneeded;
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};
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#define R200_MAX_TEXTURE_UNITS 6
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struct r200_texture_state {
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struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS];
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};
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/* Trying to keep these relatively short as the variables are becoming
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* extravagently long. Drop the driver name prefix off the front of
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* everything - I think we know which driver we're in by now, and keep the
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* prefix to 3 letters unless absolutely impossible.
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*/
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#define CTX_CMD_0 0
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#define CTX_PP_MISC 1
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#define CTX_PP_FOG_COLOR 2
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#define CTX_RE_SOLID_COLOR 3
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#define CTX_RB3D_BLENDCNTL 4
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#define CTX_RB3D_DEPTHOFFSET 5
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#define CTX_RB3D_DEPTHPITCH 6
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#define CTX_RB3D_ZSTENCILCNTL 7
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#define CTX_CMD_1 8
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#define CTX_PP_CNTL 9
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#define CTX_RB3D_CNTL 10
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#define CTX_RB3D_COLOROFFSET 11
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#define CTX_CMD_2 12 /* why */
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#define CTX_RB3D_COLORPITCH 13 /* why */
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#define CTX_CMD_3 14
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#define CTX_RB3D_BLENDCOLOR 15
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#define CTX_RB3D_ABLENDCNTL 16
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#define CTX_RB3D_CBLENDCNTL 17
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#define CTX_STATE_SIZE_NEWDRM 18
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#define SET_CMD_0 0
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#define SET_SE_CNTL 1
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#define SET_RE_CNTL 2 /* replace se_coord_fmt */
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#define SET_STATE_SIZE 3
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#define VTE_CMD_0 0
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#define VTE_SE_VTE_CNTL 1
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#define VTE_STATE_SIZE 2
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#define LIN_CMD_0 0
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#define LIN_RE_LINE_PATTERN 1
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#define LIN_RE_LINE_STATE 2
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#define LIN_CMD_1 3
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#define LIN_SE_LINE_WIDTH 4
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#define LIN_STATE_SIZE 5
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#define MSK_CMD_0 0
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#define MSK_RB3D_STENCILREFMASK 1
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#define MSK_RB3D_ROPCNTL 2
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#define MSK_RB3D_PLANEMASK 3
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#define MSK_STATE_SIZE 4
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#define VPT_CMD_0 0
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#define VPT_SE_VPORT_XSCALE 1
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#define VPT_SE_VPORT_XOFFSET 2
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#define VPT_SE_VPORT_YSCALE 3
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#define VPT_SE_VPORT_YOFFSET 4
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#define VPT_SE_VPORT_ZSCALE 5
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#define VPT_SE_VPORT_ZOFFSET 6
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#define VPT_STATE_SIZE 7
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#define ZBS_CMD_0 0
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#define ZBS_SE_ZBIAS_FACTOR 1
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#define ZBS_SE_ZBIAS_CONSTANT 2
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#define ZBS_STATE_SIZE 3
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#define MSC_CMD_0 0
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#define MSC_RE_MISC 1
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#define MSC_STATE_SIZE 2
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#define TAM_CMD_0 0
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#define TAM_DEBUG3 1
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#define TAM_STATE_SIZE 2
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#define TEX_CMD_0 0
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#define TEX_PP_TXFILTER 1 /*2c00*/
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#define TEX_PP_TXFORMAT 2 /*2c04*/
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#define TEX_PP_TXFORMAT_X 3 /*2c08*/
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#define TEX_PP_TXSIZE 4 /*2c0c*/
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#define TEX_PP_TXPITCH 5 /*2c10*/
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#define TEX_PP_BORDER_COLOR 6 /*2c14*/
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#define TEX_PP_CUBIC_FACES 7
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#define TEX_PP_TXMULTI_CTL 8
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#define TEX_CMD_1_NEWDRM 9
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#define TEX_PP_TXOFFSET_NEWDRM 10
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#define TEX_STATE_SIZE_NEWDRM 11
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#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */
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#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */
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#define CUBE_CMD_1 2 /* 5 registers follow */
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#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */
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#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */
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#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */
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#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */
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#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */
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#define CUBE_STATE_SIZE 8
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#define PIX_CMD_0 0
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#define PIX_PP_TXCBLEND 1
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#define PIX_PP_TXCBLEND2 2
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#define PIX_PP_TXABLEND 3
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#define PIX_PP_TXABLEND2 4
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#define PIX_STATE_SIZE 5
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#define TF_CMD_0 0
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#define TF_TFACTOR_0 1
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#define TF_TFACTOR_1 2
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#define TF_TFACTOR_2 3
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#define TF_TFACTOR_3 4
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#define TF_TFACTOR_4 5
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#define TF_TFACTOR_5 6
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#define TF_STATE_SIZE 7
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#define ATF_CMD_0 0
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#define ATF_TFACTOR_0 1
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#define ATF_TFACTOR_1 2
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#define ATF_TFACTOR_2 3
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#define ATF_TFACTOR_3 4
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#define ATF_TFACTOR_4 5
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#define ATF_TFACTOR_5 6
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#define ATF_TFACTOR_6 7
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#define ATF_TFACTOR_7 8
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#define ATF_STATE_SIZE 9
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/* ATI_FRAGMENT_SHADER */
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#define AFS_CMD_0 0
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#define AFS_IC0 1 /* 2f00 */
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#define AFS_IC1 2 /* 2f04 */
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#define AFS_IA0 3 /* 2f08 */
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#define AFS_IA1 4 /* 2f0c */
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#define AFS_STATE_SIZE 33
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#define PVS_CMD_0 0
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#define PVS_CNTL_1 1
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#define PVS_CNTL_2 2
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#define PVS_STATE_SIZE 3
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/* those are quite big... */
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#define VPI_CMD_0 0
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#define VPI_OPDST_0 1
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#define VPI_SRC0_0 2
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#define VPI_SRC1_0 3
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#define VPI_SRC2_0 4
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#define VPI_OPDST_63 253
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#define VPI_SRC0_63 254
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#define VPI_SRC1_63 255
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#define VPI_SRC2_63 256
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#define VPI_STATE_SIZE 257
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#define VPP_CMD_0 0
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#define VPP_PARAM0_0 1
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#define VPP_PARAM1_0 2
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#define VPP_PARAM2_0 3
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#define VPP_PARAM3_0 4
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#define VPP_PARAM0_95 381
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#define VPP_PARAM1_95 382
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#define VPP_PARAM2_95 383
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#define VPP_PARAM3_95 384
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#define VPP_STATE_SIZE 385
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#define TCL_CMD_0 0
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#define TCL_LIGHT_MODEL_CTL_0 1
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#define TCL_LIGHT_MODEL_CTL_1 2
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#define TCL_PER_LIGHT_CTL_0 3
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#define TCL_PER_LIGHT_CTL_1 4
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#define TCL_PER_LIGHT_CTL_2 5
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#define TCL_PER_LIGHT_CTL_3 6
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#define TCL_CMD_1 7
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#define TCL_UCP_VERT_BLEND_CTL 8
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#define TCL_STATE_SIZE 9
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#define MSL_CMD_0 0
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#define MSL_MATRIX_SELECT_0 1
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#define MSL_MATRIX_SELECT_1 2
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#define MSL_MATRIX_SELECT_2 3
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#define MSL_MATRIX_SELECT_3 4
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#define MSL_MATRIX_SELECT_4 5
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#define MSL_STATE_SIZE 6
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#define TCG_CMD_0 0
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#define TCG_TEX_PROC_CTL_2 1
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#define TCG_TEX_PROC_CTL_3 2
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#define TCG_TEX_PROC_CTL_0 3
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#define TCG_TEX_PROC_CTL_1 4
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#define TCG_TEX_CYL_WRAP_CTL 5
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#define TCG_STATE_SIZE 6
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#define MTL_CMD_0 0
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#define MTL_EMMISSIVE_RED 1
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#define MTL_EMMISSIVE_GREEN 2
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#define MTL_EMMISSIVE_BLUE 3
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#define MTL_EMMISSIVE_ALPHA 4
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#define MTL_AMBIENT_RED 5
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#define MTL_AMBIENT_GREEN 6
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#define MTL_AMBIENT_BLUE 7
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#define MTL_AMBIENT_ALPHA 8
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#define MTL_DIFFUSE_RED 9
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#define MTL_DIFFUSE_GREEN 10
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#define MTL_DIFFUSE_BLUE 11
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#define MTL_DIFFUSE_ALPHA 12
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#define MTL_SPECULAR_RED 13
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#define MTL_SPECULAR_GREEN 14
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#define MTL_SPECULAR_BLUE 15
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#define MTL_SPECULAR_ALPHA 16
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#define MTL_CMD_1 17
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#define MTL_SHININESS 18
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#define MTL_STATE_SIZE 19
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#define VAP_CMD_0 0
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#define VAP_SE_VAP_CNTL 1
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#define VAP_STATE_SIZE 2
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/* Replaces a lot of packet info from radeon
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*/
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#define VTX_CMD_0 0
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#define VTX_VTXFMT_0 1
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#define VTX_VTXFMT_1 2
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#define VTX_TCL_OUTPUT_VTXFMT_0 3
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#define VTX_TCL_OUTPUT_VTXFMT_1 4
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#define VTX_CMD_1 5
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#define VTX_TCL_OUTPUT_COMPSEL 6
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#define VTX_CMD_2 7
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#define VTX_STATE_CNTL 8
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#define VTX_STATE_SIZE 9
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/* SPR - point sprite state
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*/
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#define SPR_CMD_0 0
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#define SPR_POINT_SPRITE_CNTL 1
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#define SPR_STATE_SIZE 2
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#define PTP_CMD_0 0
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#define PTP_VPORT_SCALE_0 1
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#define PTP_VPORT_SCALE_1 2
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#define PTP_VPORT_SCALE_PTSIZE 3
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#define PTP_VPORT_SCALE_3 4
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#define PTP_CMD_1 5
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#define PTP_ATT_CONST_QUAD 6
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#define PTP_ATT_CONST_LIN 7
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#define PTP_ATT_CONST_CON 8
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#define PTP_ATT_CONST_3 9
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#define PTP_EYE_X 10
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#define PTP_EYE_Y 11
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#define PTP_EYE_Z 12
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#define PTP_EYE_3 13
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#define PTP_CLAMP_MIN 14
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#define PTP_CLAMP_MAX 15
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#define PTP_CLAMP_2 16
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#define PTP_CLAMP_3 17
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#define PTP_STATE_SIZE 18
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#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\
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R200_VTX_COLOR_MASK)
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/**
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* Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine
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* how many components are in texture coordinate \c n.
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*/
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#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07)
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#define MAT_CMD_0 0
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#define MAT_ELT_0 1
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#define MAT_STATE_SIZE 17
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#define GRD_CMD_0 0
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#define GRD_VERT_GUARD_CLIP_ADJ 1
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#define GRD_VERT_GUARD_DISCARD_ADJ 2
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#define GRD_HORZ_GUARD_CLIP_ADJ 3
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#define GRD_HORZ_GUARD_DISCARD_ADJ 4
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#define GRD_STATE_SIZE 5
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/* position changes frequently when lighting in modelpos - separate
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* out to new state item?
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*/
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#define LIT_CMD_0 0
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#define LIT_AMBIENT_RED 1
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#define LIT_AMBIENT_GREEN 2
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#define LIT_AMBIENT_BLUE 3
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#define LIT_AMBIENT_ALPHA 4
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#define LIT_DIFFUSE_RED 5
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#define LIT_DIFFUSE_GREEN 6
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#define LIT_DIFFUSE_BLUE 7
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#define LIT_DIFFUSE_ALPHA 8
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#define LIT_SPECULAR_RED 9
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#define LIT_SPECULAR_GREEN 10
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#define LIT_SPECULAR_BLUE 11
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#define LIT_SPECULAR_ALPHA 12
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#define LIT_POSITION_X 13
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#define LIT_POSITION_Y 14
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#define LIT_POSITION_Z 15
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#define LIT_POSITION_W 16
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#define LIT_DIRECTION_X 17
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#define LIT_DIRECTION_Y 18
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#define LIT_DIRECTION_Z 19
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#define LIT_DIRECTION_W 20
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#define LIT_ATTEN_QUADRATIC 21
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#define LIT_ATTEN_LINEAR 22
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#define LIT_ATTEN_CONST 23
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#define LIT_ATTEN_XXX 24
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#define LIT_CMD_1 25
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#define LIT_SPOT_DCD 26
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#define LIT_SPOT_DCM 27
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#define LIT_SPOT_EXPONENT 28
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#define LIT_SPOT_CUTOFF 29
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#define LIT_SPECULAR_THRESH 30
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#define LIT_RANGE_CUTOFF 31 /* ? */
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#define LIT_ATTEN_CONST_INV 32
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#define LIT_STATE_SIZE 33
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/* Fog
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*/
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#define FOG_CMD_0 0
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#define FOG_R 1
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#define FOG_C 2
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#define FOG_D 3
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#define FOG_PAD 4
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#define FOG_STATE_SIZE 5
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/* UCP
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*/
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#define UCP_CMD_0 0
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#define UCP_X 1
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#define UCP_Y 2
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#define UCP_Z 3
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#define UCP_W 4
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#define UCP_STATE_SIZE 5
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/* GLT - Global ambient
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*/
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#define GLT_CMD_0 0
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#define GLT_RED 1
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#define GLT_GREEN 2
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#define GLT_BLUE 3
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#define GLT_ALPHA 4
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#define GLT_STATE_SIZE 5
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/* EYE
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*/
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#define EYE_CMD_0 0
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#define EYE_X 1
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#define EYE_Y 2
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#define EYE_Z 3
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#define EYE_RESCALE_FACTOR 4
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#define EYE_STATE_SIZE 5
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/* CST - constant state
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*/
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#define CST_CMD_0 0
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#define CST_PP_CNTL_X 1
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#define CST_CMD_1 2
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#define CST_RB3D_DEPTHXY_OFFSET 3
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#define CST_CMD_2 4
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#define CST_RE_AUX_SCISSOR_CNTL 5
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#define CST_CMD_4 6
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#define CST_SE_VAP_CNTL_STATUS 7
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#define CST_CMD_5 8
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#define CST_RE_POINTSIZE 9
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#define CST_CMD_6 10
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#define CST_SE_TCL_INPUT_VTX_0 11
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#define CST_SE_TCL_INPUT_VTX_1 12
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#define CST_SE_TCL_INPUT_VTX_2 13
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#define CST_SE_TCL_INPUT_VTX_3 14
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#define CST_STATE_SIZE 15
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#define PRF_CMD_0 0
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#define PRF_PP_TRI_PERF 1
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#define PRF_PP_PERF_CNTL 2
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#define PRF_STATE_SIZE 3
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#define SCI_CMD_1 0
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#define SCI_XY_1 1
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#define SCI_CMD_2 2
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#define SCI_XY_2 3
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#define SCI_STATE_SIZE 4
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#define R200_QUERYOBJ_CMD_0 0
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#define R200_QUERYOBJ_DATA_0 1
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#define R200_QUERYOBJ_CMDSIZE 2
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#define STP_CMD_0 0
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#define STP_DATA_0 1
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#define STP_CMD_1 2
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#define STP_STATE_SIZE 35
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struct r200_hw_state {
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/* Hardware state, stored as cmdbuf commands:
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* -- Need to doublebuffer for
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* - reviving state after loss of context
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* - eliding noop statechange loops? (except line stipple count)
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*/
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struct radeon_state_atom ctx;
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struct radeon_state_atom set;
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struct radeon_state_atom sci;
|
|
struct radeon_state_atom vte;
|
|
struct radeon_state_atom lin;
|
|
struct radeon_state_atom msk;
|
|
struct radeon_state_atom vpt;
|
|
struct radeon_state_atom vap;
|
|
struct radeon_state_atom vtx;
|
|
struct radeon_state_atom tcl;
|
|
struct radeon_state_atom msl;
|
|
struct radeon_state_atom tcg;
|
|
struct radeon_state_atom msc;
|
|
struct radeon_state_atom cst;
|
|
struct radeon_state_atom tam;
|
|
struct radeon_state_atom tf;
|
|
struct radeon_state_atom tex[6];
|
|
struct radeon_state_atom cube[6];
|
|
struct radeon_state_atom zbs;
|
|
struct radeon_state_atom mtl[2];
|
|
struct radeon_state_atom mat[9];
|
|
struct radeon_state_atom lit[8]; /* includes vec, scl commands */
|
|
struct radeon_state_atom ucp[6];
|
|
struct radeon_state_atom pix[6]; /* pixshader stages */
|
|
struct radeon_state_atom eye; /* eye pos */
|
|
struct radeon_state_atom grd; /* guard band clipping */
|
|
struct radeon_state_atom fog;
|
|
struct radeon_state_atom glt;
|
|
struct radeon_state_atom prf;
|
|
struct radeon_state_atom afs[2];
|
|
struct radeon_state_atom pvs;
|
|
struct radeon_state_atom vpi[2];
|
|
struct radeon_state_atom vpp[2];
|
|
struct radeon_state_atom atf;
|
|
struct radeon_state_atom spr;
|
|
struct radeon_state_atom ptp;
|
|
struct radeon_state_atom stp;
|
|
};
|
|
|
|
struct r200_state {
|
|
/* Derived state for internal purposes:
|
|
*/
|
|
struct r200_texture_state texture;
|
|
GLuint envneeded;
|
|
};
|
|
|
|
#define R200_CMD_BUF_SZ (16*1024)
|
|
|
|
#define R200_ELT_BUF_SZ (16*1024)
|
|
/* r200_tcl.c
|
|
*/
|
|
struct r200_tcl_info {
|
|
GLuint hw_primitive;
|
|
|
|
int elt_used;
|
|
|
|
};
|
|
|
|
|
|
/* r200_swtcl.c
|
|
*/
|
|
struct r200_swtcl_info {
|
|
|
|
|
|
radeon_point_func draw_point;
|
|
radeon_line_func draw_line;
|
|
radeon_tri_func draw_tri;
|
|
|
|
/**
|
|
* Offset of the 4UB color data within a hardware (swtcl) vertex.
|
|
*/
|
|
GLuint coloroffset;
|
|
|
|
/**
|
|
* Offset of the 3UB specular color data within a hardware (swtcl) vertex.
|
|
*/
|
|
GLuint specoffset;
|
|
|
|
/**
|
|
* Should Mesa project vertex data or will the hardware do it?
|
|
*/
|
|
GLboolean needproj;
|
|
};
|
|
|
|
|
|
|
|
|
|
/* A maximum total of 29 elements per vertex: 3 floats for position, 3
|
|
* floats for normal, 4 floats for color, 4 bytes for secondary color,
|
|
* 3 floats for each texture unit (18 floats total).
|
|
*
|
|
* we maybe need add. 4 to prevent segfault if someone specifies
|
|
* GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: )
|
|
*
|
|
* The position data is never actually stored here, so 3 elements could be
|
|
* trimmed out of the buffer.
|
|
*/
|
|
|
|
#define R200_MAX_VERTEX_SIZE ((3*6)+11)
|
|
|
|
struct r200_context {
|
|
struct radeon_context radeon;
|
|
|
|
/* Driver and hardware state management
|
|
*/
|
|
struct r200_hw_state hw;
|
|
struct r200_state state;
|
|
struct r200_vertex_program *curr_vp_hw;
|
|
|
|
/* Vertex buffers
|
|
*/
|
|
struct radeon_ioctl ioctl;
|
|
struct radeon_store store;
|
|
|
|
/* Clientdata textures;
|
|
*/
|
|
GLuint prefer_gart_client_texturing;
|
|
|
|
/* TCL stuff
|
|
*/
|
|
GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS];
|
|
GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS];
|
|
GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS];
|
|
GLuint TexMatEnabled;
|
|
GLuint TexMatCompSel;
|
|
GLuint TexGenEnabled;
|
|
GLuint TexGenCompSel;
|
|
GLmatrix tmpmat;
|
|
|
|
/* r200_tcl.c
|
|
*/
|
|
struct r200_tcl_info tcl;
|
|
|
|
/* r200_swtcl.c
|
|
*/
|
|
struct r200_swtcl_info swtcl;
|
|
|
|
GLboolean using_hyperz;
|
|
|
|
struct ati_fragment_shader *afs_loaded;
|
|
};
|
|
|
|
|
|
static inline r200ContextPtr
|
|
R200_CONTEXT(struct gl_context *ctx)
|
|
{
|
|
return (r200ContextPtr) ctx;
|
|
}
|
|
|
|
|
|
extern void r200DestroyContext( __DRIcontext *driContextPriv );
|
|
extern GLboolean r200CreateContext( gl_api api,
|
|
const struct gl_config *glVisual,
|
|
__DRIcontext *driContextPriv,
|
|
const struct __DriverContextConfig *
|
|
ctx_config,
|
|
unsigned *error,
|
|
void *sharedContextPrivate);
|
|
extern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv,
|
|
__DRIdrawable *driDrawPriv,
|
|
__DRIdrawable *driReadPriv );
|
|
extern GLboolean r200UnbindContext( __DRIcontext *driContextPriv );
|
|
|
|
extern void r200_init_texcopy_functions(struct dd_function_table *table);
|
|
|
|
/* ================================================================
|
|
* Debugging:
|
|
*/
|
|
|
|
#define R200_DEBUG RADEON_DEBUG
|
|
|
|
|
|
|
|
#endif /* __R200_CONTEXT_H__ */
|