776 lines
28 KiB
C
776 lines
28 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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#include "sid.h"
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#include "util/format/u_format.h"
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#include "util/u_pack_color.h"
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#include "util/u_surface.h"
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enum
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{
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SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
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SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
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};
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static void si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture *tex)
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{
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/* CMASK for MSAA is allocated in advance or always disabled
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* by "nofmask" option.
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*/
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if (tex->cmask_buffer || !tex->surface.cmask_size || tex->buffer.b.b.nr_samples >= 2)
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return;
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tex->cmask_buffer =
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si_aligned_buffer_create(&sscreen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
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tex->surface.cmask_size, tex->surface.cmask_alignment);
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if (tex->cmask_buffer == NULL)
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return;
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tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
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tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
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p_atomic_inc(&sscreen->compressed_colortex_counter);
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}
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static bool si_set_clear_color(struct si_texture *tex, enum pipe_format surface_format,
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const union pipe_color_union *color)
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{
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union util_color uc;
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memset(&uc, 0, sizeof(uc));
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if (tex->surface.bpe == 16) {
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/* DCC fast clear only:
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* CLEAR_WORD0 = R = G = B
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* CLEAR_WORD1 = A
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*/
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assert(color->ui[0] == color->ui[1] && color->ui[0] == color->ui[2]);
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uc.ui[0] = color->ui[0];
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uc.ui[1] = color->ui[3];
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} else {
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util_pack_color_union(surface_format, &uc, color);
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}
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if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
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return false;
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memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
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return true;
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}
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/** Linearize and convert luminace/intensity to red. */
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enum pipe_format si_simplify_cb_format(enum pipe_format format)
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{
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format = util_format_linear(format);
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format = util_format_luminance_to_red(format);
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return util_format_intensity_to_red(format);
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}
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bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format)
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{
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format = si_simplify_cb_format(format);
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const struct util_format_description *desc = util_format_description(format);
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/* Formats with 3 channels can't have alpha. */
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if (desc->nr_channels == 3)
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return true; /* same as xxxA; is any value OK here? */
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if (sscreen->info.chip_class >= GFX10 && desc->nr_channels == 1)
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return desc->swizzle[3] == PIPE_SWIZZLE_X;
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return si_translate_colorswap(format, false) <= 1;
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}
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static bool vi_get_fast_clear_parameters(struct si_screen *sscreen, enum pipe_format base_format,
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enum pipe_format surface_format,
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const union pipe_color_union *color, uint32_t *clear_value,
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bool *eliminate_needed)
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{
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/* If we want to clear without needing a fast clear eliminate step, we
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* can set color and alpha independently to 0 or 1 (or 0/max for integer
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* formats).
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*/
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bool values[4] = {}; /* whether to clear to 0 or 1 */
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bool color_value = false; /* clear color to 0 or 1 */
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bool alpha_value = false; /* clear alpha to 0 or 1 */
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int alpha_channel; /* index of the alpha component */
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bool has_color = false;
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bool has_alpha = false;
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const struct util_format_description *desc =
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util_format_description(si_simplify_cb_format(surface_format));
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/* 128-bit fast clear with different R,G,B values is unsupported. */
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if (desc->block.bits == 128 && (color->ui[0] != color->ui[1] || color->ui[0] != color->ui[2]))
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return false;
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*eliminate_needed = true;
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*clear_value = DCC_CLEAR_COLOR_REG;
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if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
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return true; /* need ELIMINATE_FAST_CLEAR */
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bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format);
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bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, surface_format);
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/* Formats with 3 channels can't have alpha. */
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if (desc->nr_channels == 3)
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alpha_channel = -1;
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else if (surf_alpha_is_on_msb)
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alpha_channel = desc->nr_channels - 1;
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else
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alpha_channel = 0;
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for (int i = 0; i < 4; ++i) {
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if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
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continue;
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if (desc->channel[i].pure_integer && desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
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/* Use the maximum value for clamping the clear color. */
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int max = u_bit_consecutive(0, desc->channel[i].size - 1);
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values[i] = color->i[i] != 0;
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if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
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return true; /* need ELIMINATE_FAST_CLEAR */
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} else if (desc->channel[i].pure_integer &&
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desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
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/* Use the maximum value for clamping the clear color. */
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unsigned max = u_bit_consecutive(0, desc->channel[i].size);
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values[i] = color->ui[i] != 0U;
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if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
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return true; /* need ELIMINATE_FAST_CLEAR */
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} else {
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values[i] = color->f[i] != 0.0F;
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if (color->f[i] != 0.0F && color->f[i] != 1.0F)
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return true; /* need ELIMINATE_FAST_CLEAR */
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}
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if (desc->swizzle[i] == alpha_channel) {
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alpha_value = values[i];
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has_alpha = true;
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} else {
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color_value = values[i];
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has_color = true;
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}
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}
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/* If alpha isn't present, make it the same as color, and vice versa. */
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if (!has_alpha)
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alpha_value = color_value;
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else if (!has_color)
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color_value = alpha_value;
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if (color_value != alpha_value && base_alpha_is_on_msb != surf_alpha_is_on_msb)
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return true; /* require ELIMINATE_FAST_CLEAR */
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/* Check if all color values are equal if they are present. */
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for (int i = 0; i < 4; ++i) {
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if (desc->swizzle[i] <= PIPE_SWIZZLE_W && desc->swizzle[i] != alpha_channel &&
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values[i] != color_value)
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return true; /* require ELIMINATE_FAST_CLEAR */
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}
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/* This doesn't need ELIMINATE_FAST_CLEAR.
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* On chips predating Raven2, the DCC clear codes and the CB clear
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* color registers must match.
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*/
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*eliminate_needed = false;
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if (color_value) {
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if (alpha_value)
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*clear_value = DCC_CLEAR_COLOR_1111;
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else
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*clear_value = DCC_CLEAR_COLOR_1110;
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} else {
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if (alpha_value)
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*clear_value = DCC_CLEAR_COLOR_0001;
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else
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*clear_value = DCC_CLEAR_COLOR_0000;
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}
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return true;
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}
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bool vi_dcc_clear_level(struct si_context *sctx, struct si_texture *tex, unsigned level,
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unsigned clear_value)
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{
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struct pipe_resource *dcc_buffer;
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uint64_t dcc_offset, clear_size;
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assert(vi_dcc_enabled(tex, level));
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if (tex->dcc_separate_buffer) {
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dcc_buffer = &tex->dcc_separate_buffer->b.b;
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dcc_offset = 0;
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} else {
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dcc_buffer = &tex->buffer.b.b;
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dcc_offset = tex->surface.dcc_offset;
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}
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if (sctx->chip_class >= GFX9) {
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/* Mipmap level clears aren't implemented. */
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if (tex->buffer.b.b.last_level > 0)
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return false;
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/* 4x and 8x MSAA needs a sophisticated compute shader for
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* the clear. See AMDVLK. */
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if (tex->buffer.b.b.nr_storage_samples >= 4)
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return false;
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clear_size = tex->surface.dcc_size;
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} else {
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unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
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/* If this is 0, fast clear isn't possible. (can occur with MSAA) */
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if (!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
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return false;
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/* Layered 4x and 8x MSAA DCC fast clears need to clear
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* dcc_fast_clear_size bytes for each layer. A compute shader
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* would be more efficient than separate per-layer clear operations.
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*/
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if (tex->buffer.b.b.nr_storage_samples >= 4 && num_layers > 1)
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return false;
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dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
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clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size * num_layers;
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}
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si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size, &clear_value, 4, SI_COHERENCY_CB_META,
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false);
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return true;
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}
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/* Set the same micro tile mode as the destination of the last MSAA resolve.
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* This allows hitting the MSAA resolve fast path, which requires that both
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* src and dst micro tile modes match.
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*/
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static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_texture *tex)
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{
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if (sscreen->info.chip_class >= GFX10 || tex->buffer.b.is_shared ||
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tex->buffer.b.b.nr_samples <= 1 ||
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tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
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return;
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assert(sscreen->info.chip_class >= GFX9 ||
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tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
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assert(tex->buffer.b.b.last_level == 0);
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if (sscreen->info.chip_class >= GFX9) {
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/* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
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assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
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/* If you do swizzle_mode % 4, you'll get:
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* 0 = Depth
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* 1 = Standard,
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* 2 = Displayable
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* 3 = Rotated
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*
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* Depth-sample order isn't allowed:
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*/
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assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
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switch (tex->last_msaa_resolve_target_micro_mode) {
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case RADEON_MICRO_MODE_DISPLAY:
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tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
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tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
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break;
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case RADEON_MICRO_MODE_STANDARD:
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tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
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tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
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break;
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case RADEON_MICRO_MODE_RENDER:
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tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
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tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
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break;
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default: /* depth */
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assert(!"unexpected micro mode");
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return;
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}
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} else if (sscreen->info.chip_class >= GFX7) {
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/* These magic numbers were copied from addrlib. It doesn't use
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* any definitions for them either. They are all 2D_TILED_THIN1
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* modes with different bpp and micro tile mode.
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*/
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switch (tex->last_msaa_resolve_target_micro_mode) {
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case RADEON_MICRO_MODE_DISPLAY:
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tex->surface.u.legacy.tiling_index[0] = 10;
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break;
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case RADEON_MICRO_MODE_STANDARD:
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tex->surface.u.legacy.tiling_index[0] = 14;
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break;
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case RADEON_MICRO_MODE_RENDER:
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tex->surface.u.legacy.tiling_index[0] = 28;
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break;
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default: /* depth, thick */
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assert(!"unexpected micro mode");
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return;
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}
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} else { /* GFX6 */
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switch (tex->last_msaa_resolve_target_micro_mode) {
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case RADEON_MICRO_MODE_DISPLAY:
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switch (tex->surface.bpe) {
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case 1:
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tex->surface.u.legacy.tiling_index[0] = 10;
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break;
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case 2:
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tex->surface.u.legacy.tiling_index[0] = 11;
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break;
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default: /* 4, 8 */
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tex->surface.u.legacy.tiling_index[0] = 12;
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break;
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}
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break;
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case RADEON_MICRO_MODE_STANDARD:
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switch (tex->surface.bpe) {
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case 1:
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tex->surface.u.legacy.tiling_index[0] = 14;
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break;
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case 2:
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tex->surface.u.legacy.tiling_index[0] = 15;
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break;
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case 4:
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tex->surface.u.legacy.tiling_index[0] = 16;
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break;
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default: /* 8, 16 */
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tex->surface.u.legacy.tiling_index[0] = 17;
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break;
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}
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break;
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default: /* depth, thick */
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assert(!"unexpected micro mode");
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return;
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}
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}
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tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
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p_atomic_inc(&sscreen->dirty_tex_counter);
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}
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static void si_do_fast_color_clear(struct si_context *sctx, unsigned *buffers,
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const union pipe_color_union *color)
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{
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struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
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int i;
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/* This function is broken in BE, so just disable this path for now */
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#if UTIL_ARCH_BIG_ENDIAN
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return;
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#endif
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if (sctx->render_cond)
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return;
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for (i = 0; i < fb->nr_cbufs; i++) {
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struct si_texture *tex;
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unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
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if (!fb->cbufs[i])
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continue;
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/* if this colorbuffer is not being cleared */
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if (!(*buffers & clear_bit))
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continue;
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unsigned level = fb->cbufs[i]->u.tex.level;
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if (level > 0)
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continue;
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tex = (struct si_texture *)fb->cbufs[i]->texture;
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/* TODO: GFX9: Implement DCC fast clear for level 0 of
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* mipmapped textures. Mipmapped DCC has to clear a rectangular
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* area of DCC for level 0 (because the whole miptree is
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* organized in a 2D plane).
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*/
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if (sctx->chip_class >= GFX9 && tex->buffer.b.b.last_level > 0)
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continue;
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/* the clear is allowed if all layers are bound */
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if (fb->cbufs[i]->u.tex.first_layer != 0 ||
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fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) {
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continue;
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}
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/* only supported on tiled surfaces */
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if (tex->surface.is_linear) {
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continue;
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}
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/* shared textures can't use fast clear without an explicit flush,
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* because there is no way to communicate the clear color among
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* all clients
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*/
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if (tex->buffer.b.is_shared &&
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!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
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continue;
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if (sctx->chip_class <= GFX8 && tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
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!sctx->screen->info.htile_cmask_support_1d_tiling)
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continue;
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/* Use a slow clear for small surfaces where the cost of
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* the eliminate pass can be higher than the benefit of fast
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* clear. The closed driver does this, but the numbers may differ.
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*
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* This helps on both dGPUs and APUs, even small APUs like Mullins.
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*/
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bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
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tex->buffer.b.b.width0 * tex->buffer.b.b.height0 <= 512 * 512;
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bool eliminate_needed = false;
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bool fmask_decompress_needed = false;
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/* Fast clear is the most appropriate place to enable DCC for
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* displayable surfaces.
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*/
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if (sctx->family == CHIP_STONEY && !too_small) {
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vi_separate_dcc_try_enable(sctx, tex);
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/* RB+ isn't supported with a CMASK clear only on Stoney,
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* so all clears are considered to be hypothetically slow
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* clears, which is weighed when determining whether to
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* enable separate DCC.
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*/
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if (tex->dcc_gather_statistics) /* only for Stoney */
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tex->num_slow_clears++;
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}
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/* Try to clear DCC first, otherwise try CMASK. */
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if (vi_dcc_enabled(tex, 0)) {
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uint32_t reset_value;
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|
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if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
|
|
continue;
|
|
|
|
if (!vi_get_fast_clear_parameters(sctx->screen, tex->buffer.b.b.format,
|
|
fb->cbufs[i]->format, color, &reset_value,
|
|
&eliminate_needed))
|
|
continue;
|
|
|
|
if (eliminate_needed && too_small)
|
|
continue;
|
|
|
|
/* TODO: This DCC+CMASK clear doesn't work with MSAA. */
|
|
if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer && eliminate_needed)
|
|
continue;
|
|
|
|
if (!vi_dcc_clear_level(sctx, tex, 0, reset_value))
|
|
continue;
|
|
|
|
tex->separate_dcc_dirty = true;
|
|
tex->displayable_dcc_dirty = true;
|
|
|
|
/* DCC fast clear with MSAA should clear CMASK to 0xC. */
|
|
if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
|
|
uint32_t clear_value = 0xCCCCCCCC;
|
|
si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->surface.cmask_offset,
|
|
tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, false);
|
|
fmask_decompress_needed = true;
|
|
}
|
|
} else {
|
|
if (too_small)
|
|
continue;
|
|
|
|
/* 128-bit formats are unusupported */
|
|
if (tex->surface.bpe > 8) {
|
|
continue;
|
|
}
|
|
|
|
/* RB+ doesn't work with CMASK fast clear on Stoney. */
|
|
if (sctx->family == CHIP_STONEY)
|
|
continue;
|
|
|
|
/* Disable fast clear if tex is encrypted */
|
|
if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED)
|
|
continue;
|
|
|
|
/* ensure CMASK is enabled */
|
|
si_alloc_separate_cmask(sctx->screen, tex);
|
|
if (!tex->cmask_buffer)
|
|
continue;
|
|
|
|
/* Do the fast clear. */
|
|
uint32_t clear_value = 0;
|
|
si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->surface.cmask_offset,
|
|
tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, false);
|
|
eliminate_needed = true;
|
|
}
|
|
|
|
if ((eliminate_needed || fmask_decompress_needed) &&
|
|
!(tex->dirty_level_mask & (1 << level))) {
|
|
tex->dirty_level_mask |= 1 << level;
|
|
p_atomic_inc(&sctx->screen->compressed_colortex_counter);
|
|
}
|
|
|
|
/* We can change the micro tile mode before a full clear. */
|
|
si_set_optimal_micro_tile_mode(sctx->screen, tex);
|
|
|
|
*buffers &= ~clear_bit;
|
|
|
|
/* Chips with DCC constant encoding don't need to set the clear
|
|
* color registers for DCC clear values 0 and 1.
|
|
*/
|
|
if (sctx->screen->info.has_dcc_constant_encode && !eliminate_needed)
|
|
continue;
|
|
|
|
if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
|
|
sctx->framebuffer.dirty_cbufs |= 1 << i;
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void si_clear(struct pipe_context *ctx, unsigned buffers,
|
|
const struct pipe_scissor_state *scissor_state,
|
|
const union pipe_color_union *color, double depth, unsigned stencil)
|
|
{
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
|
|
struct pipe_surface *zsbuf = fb->zsbuf;
|
|
struct si_texture *zstex = zsbuf ? (struct si_texture *)zsbuf->texture : NULL;
|
|
bool needs_db_flush = false;
|
|
|
|
if (buffers & PIPE_CLEAR_COLOR) {
|
|
si_do_fast_color_clear(sctx, &buffers, color);
|
|
if (!buffers)
|
|
return; /* all buffers have been fast cleared */
|
|
|
|
/* These buffers cannot use fast clear, make sure to disable expansion. */
|
|
for (unsigned i = 0; i < fb->nr_cbufs; i++) {
|
|
struct si_texture *tex;
|
|
|
|
/* If not clearing this buffer, skip. */
|
|
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
|
|
continue;
|
|
|
|
tex = (struct si_texture *)fb->cbufs[i]->texture;
|
|
if (tex->surface.fmask_size == 0)
|
|
tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
|
|
}
|
|
}
|
|
|
|
if (zstex && zsbuf->u.tex.first_layer == 0 &&
|
|
zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
|
|
/* See whether we should enable TC-compatible HTILE. */
|
|
if (zstex->enable_tc_compatible_htile_next_clear &&
|
|
!zstex->tc_compatible_htile &&
|
|
si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_ZS) &&
|
|
/* If both depth and stencil are present, they must be cleared together. */
|
|
((buffers & PIPE_CLEAR_DEPTHSTENCIL) == PIPE_CLEAR_DEPTHSTENCIL ||
|
|
(buffers & PIPE_CLEAR_DEPTH && (!zstex->surface.has_stencil ||
|
|
zstex->htile_stencil_disabled)))) {
|
|
/* Enable TC-compatible HTILE. */
|
|
zstex->enable_tc_compatible_htile_next_clear = false;
|
|
zstex->tc_compatible_htile = true;
|
|
|
|
/* Update the framebuffer state to reflect the change. */
|
|
sctx->framebuffer.DB_has_shader_readable_metadata = true;
|
|
sctx->framebuffer.dirty_zsbuf = true;
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
|
|
|
|
/* Update all sampler views and shader images in all contexts. */
|
|
p_atomic_inc(&sctx->screen->dirty_tex_counter);
|
|
|
|
/* Re-initialize HTILE, so that it doesn't contain values incompatible
|
|
* with the new TC-compatible HTILE setting.
|
|
*
|
|
* 0xfffff30f = uncompressed Z + S
|
|
* 0xfffc000f = uncompressed Z only
|
|
*
|
|
* GFX8 always uses the Z+S HTILE format for TC-compatible HTILE even
|
|
* when stencil is not present.
|
|
*/
|
|
uint32_t clear_value = (zstex->surface.has_stencil &&
|
|
!zstex->htile_stencil_disabled) ||
|
|
sctx->chip_class == GFX8 ? 0xfffff30f : 0xfffc000f;
|
|
si_clear_buffer(sctx, &zstex->buffer.b.b, zstex->surface.htile_offset,
|
|
zstex->surface.htile_size, &clear_value, 4,
|
|
SI_COHERENCY_DB_META, false);
|
|
}
|
|
|
|
/* TC-compatible HTILE only supports depth clears to 0 or 1. */
|
|
if (buffers & PIPE_CLEAR_DEPTH && si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_Z) &&
|
|
(!zstex->tc_compatible_htile || depth == 0 || depth == 1)) {
|
|
/* Need to disable EXPCLEAR temporarily if clearing
|
|
* to a new value. */
|
|
if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
|
|
sctx->db_depth_disable_expclear = true;
|
|
}
|
|
|
|
if (zstex->depth_clear_value != (float)depth) {
|
|
if ((zstex->depth_clear_value != 0) != (depth != 0)) {
|
|
/* ZRANGE_PRECISION register of a bound surface will change so we
|
|
* must flush the DB caches. */
|
|
needs_db_flush = true;
|
|
}
|
|
/* Update DB_DEPTH_CLEAR. */
|
|
zstex->depth_clear_value = depth;
|
|
sctx->framebuffer.dirty_zsbuf = true;
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
|
|
}
|
|
sctx->db_depth_clear = true;
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
|
|
}
|
|
|
|
/* TC-compatible HTILE only supports stencil clears to 0. */
|
|
if (buffers & PIPE_CLEAR_STENCIL &&
|
|
si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_S) &&
|
|
(!zstex->tc_compatible_htile || stencil == 0)) {
|
|
stencil &= 0xff;
|
|
|
|
/* Need to disable EXPCLEAR temporarily if clearing
|
|
* to a new value. */
|
|
if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
|
|
sctx->db_stencil_disable_expclear = true;
|
|
}
|
|
|
|
if (zstex->stencil_clear_value != (uint8_t)stencil) {
|
|
/* Update DB_STENCIL_CLEAR. */
|
|
zstex->stencil_clear_value = stencil;
|
|
sctx->framebuffer.dirty_zsbuf = true;
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
|
|
}
|
|
sctx->db_stencil_clear = true;
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
|
|
}
|
|
|
|
if (needs_db_flush)
|
|
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
|
|
}
|
|
|
|
si_blitter_begin(sctx, SI_CLEAR);
|
|
util_blitter_clear(sctx->blitter, fb->width, fb->height, util_framebuffer_get_num_layers(fb),
|
|
buffers, color, depth, stencil, sctx->framebuffer.nr_samples > 1);
|
|
si_blitter_end(sctx);
|
|
|
|
if (sctx->db_depth_clear) {
|
|
sctx->db_depth_clear = false;
|
|
sctx->db_depth_disable_expclear = false;
|
|
zstex->depth_cleared = true;
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
|
|
}
|
|
|
|
if (sctx->db_stencil_clear) {
|
|
sctx->db_stencil_clear = false;
|
|
sctx->db_stencil_disable_expclear = false;
|
|
zstex->stencil_cleared = true;
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
|
|
}
|
|
}
|
|
|
|
static void si_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dst,
|
|
const union pipe_color_union *color, unsigned dstx,
|
|
unsigned dsty, unsigned width, unsigned height,
|
|
bool render_condition_enabled)
|
|
{
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
struct si_texture *sdst = (struct si_texture *)dst->texture;
|
|
|
|
if (dst->texture->nr_samples <= 1 && !vi_dcc_enabled(sdst, dst->u.tex.level)) {
|
|
si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width, height,
|
|
render_condition_enabled);
|
|
return;
|
|
}
|
|
|
|
si_blitter_begin(sctx,
|
|
SI_CLEAR_SURFACE | (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
|
|
util_blitter_clear_render_target(sctx->blitter, dst, color, dstx, dsty, width, height);
|
|
si_blitter_end(sctx);
|
|
}
|
|
|
|
static void si_clear_depth_stencil(struct pipe_context *ctx, struct pipe_surface *dst,
|
|
unsigned clear_flags, double depth, unsigned stencil,
|
|
unsigned dstx, unsigned dsty, unsigned width, unsigned height,
|
|
bool render_condition_enabled)
|
|
{
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
|
|
si_blitter_begin(sctx,
|
|
SI_CLEAR_SURFACE | (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
|
|
util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil, dstx, dsty,
|
|
width, height);
|
|
si_blitter_end(sctx);
|
|
}
|
|
|
|
static void si_clear_texture(struct pipe_context *pipe, struct pipe_resource *tex, unsigned level,
|
|
const struct pipe_box *box, const void *data)
|
|
{
|
|
struct pipe_screen *screen = pipe->screen;
|
|
struct si_texture *stex = (struct si_texture *)tex;
|
|
struct pipe_surface tmpl = {{0}};
|
|
struct pipe_surface *sf;
|
|
|
|
tmpl.format = tex->format;
|
|
tmpl.u.tex.first_layer = box->z;
|
|
tmpl.u.tex.last_layer = box->z + box->depth - 1;
|
|
tmpl.u.tex.level = level;
|
|
sf = pipe->create_surface(pipe, tex, &tmpl);
|
|
if (!sf)
|
|
return;
|
|
|
|
if (stex->is_depth) {
|
|
unsigned clear;
|
|
float depth;
|
|
uint8_t stencil = 0;
|
|
|
|
/* Depth is always present. */
|
|
clear = PIPE_CLEAR_DEPTH;
|
|
util_format_unpack_z_float(tex->format, &depth, data, 1);
|
|
|
|
if (stex->surface.has_stencil) {
|
|
clear |= PIPE_CLEAR_STENCIL;
|
|
util_format_unpack_s_8uint(tex->format, &stencil, data, 1);
|
|
}
|
|
|
|
si_clear_depth_stencil(pipe, sf, clear, depth, stencil, box->x, box->y, box->width,
|
|
box->height, false);
|
|
} else {
|
|
union pipe_color_union color;
|
|
|
|
util_format_unpack_rgba(tex->format, color.ui, data, 1);
|
|
|
|
if (screen->is_format_supported(screen, tex->format, tex->target, 0, 0,
|
|
PIPE_BIND_RENDER_TARGET)) {
|
|
si_clear_render_target(pipe, sf, &color, box->x, box->y, box->width, box->height, false);
|
|
} else {
|
|
/* Software fallback - just for R9G9B9E5_FLOAT */
|
|
util_clear_render_target(pipe, sf, &color, box->x, box->y, box->width, box->height);
|
|
}
|
|
}
|
|
pipe_surface_reference(&sf, NULL);
|
|
}
|
|
|
|
void si_init_clear_functions(struct si_context *sctx)
|
|
{
|
|
sctx->b.clear_render_target = si_clear_render_target;
|
|
sctx->b.clear_texture = si_clear_texture;
|
|
|
|
if (sctx->has_graphics) {
|
|
sctx->b.clear = si_clear;
|
|
sctx->b.clear_depth_stencil = si_clear_depth_stencil;
|
|
}
|
|
}
|