523 lines
17 KiB
C
523 lines
17 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/* This file handles register programming of primitive binning. */
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#include "si_build_pm4.h"
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#include "sid.h"
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struct uvec2 {
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unsigned x, y;
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};
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struct si_bin_size_map {
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unsigned start;
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unsigned bin_size_x;
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unsigned bin_size_y;
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};
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typedef struct si_bin_size_map si_bin_size_subtable[3][10];
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/* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */
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static struct uvec2 si_find_bin_size(struct si_screen *sscreen, const si_bin_size_subtable table[],
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unsigned sum)
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{
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unsigned log_num_rb_per_se =
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util_logbase2_ceil(sscreen->info.max_render_backends / sscreen->info.max_se);
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unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se);
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unsigned i;
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/* Get the chip-specific subtable. */
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const struct si_bin_size_map *subtable = &table[log_num_rb_per_se][log_num_se][0];
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for (i = 0; subtable[i].bin_size_x != 0; i++) {
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if (sum >= subtable[i].start && sum < subtable[i + 1].start)
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break;
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}
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struct uvec2 size = {subtable[i].bin_size_x, subtable[i].bin_size_y};
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return size;
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}
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static struct uvec2 si_get_color_bin_size(struct si_context *sctx, unsigned cb_target_enabled_4bit)
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{
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unsigned num_fragments = sctx->framebuffer.nr_color_samples;
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unsigned sum = 0;
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/* Compute the sum of all Bpp. */
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for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
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if (!(cb_target_enabled_4bit & (0xf << (i * 4))))
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continue;
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struct si_texture *tex = (struct si_texture *)sctx->framebuffer.state.cbufs[i]->texture;
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sum += tex->surface.bpe;
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}
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/* Multiply the sum by some function of the number of samples. */
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if (num_fragments >= 2) {
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if (si_get_ps_iter_samples(sctx) >= 2)
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sum *= num_fragments;
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else
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sum *= 2;
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}
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static const si_bin_size_subtable table[] = {
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{
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/* One RB / SE */
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{
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/* One shader engine */
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{0, 128, 128},
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{1, 64, 128},
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{2, 32, 128},
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{3, 16, 128},
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{17, 0, 0},
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},
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{
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/* Two shader engines */
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{0, 128, 128},
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{2, 64, 128},
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{3, 32, 128},
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{5, 16, 128},
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{17, 0, 0},
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},
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{
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/* Four shader engines */
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{0, 128, 128},
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{3, 64, 128},
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{5, 16, 128},
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{17, 0, 0},
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},
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},
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{
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/* Two RB / SE */
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{
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/* One shader engine */
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{0, 128, 128},
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{2, 64, 128},
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{3, 32, 128},
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{9, 16, 128},
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{33, 0, 0},
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},
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{
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/* Two shader engines */
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{0, 128, 128},
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{3, 64, 128},
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{5, 32, 128},
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{9, 16, 128},
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{33, 0, 0},
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},
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{
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/* Four shader engines */
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{0, 256, 256},
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{2, 128, 256},
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{3, 128, 128},
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{5, 64, 128},
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{9, 16, 128},
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{33, 0, 0},
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},
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},
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{
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/* Four RB / SE */
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{
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/* One shader engine */
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{0, 128, 256},
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{2, 128, 128},
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{3, 64, 128},
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{5, 32, 128},
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{9, 16, 128},
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{17, 0, 0},
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},
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{
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/* Two shader engines */
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{0, 256, 256},
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{2, 128, 256},
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{3, 128, 128},
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{5, 64, 128},
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{9, 32, 128},
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{17, 16, 128},
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{33, 0, 0},
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},
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{
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/* Four shader engines */
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{0, 256, 512},
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{2, 128, 512},
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{3, 64, 512},
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{5, 32, 512},
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{9, 32, 256},
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{17, 32, 128},
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{33, 0, 0},
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},
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},
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};
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return si_find_bin_size(sctx->screen, table, sum);
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}
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static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
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{
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struct si_state_dsa *dsa = sctx->queued.named.dsa;
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if (!sctx->framebuffer.state.zsbuf || (!dsa->depth_enabled && !dsa->stencil_enabled)) {
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/* Return the max size. */
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struct uvec2 size = {512, 512};
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return size;
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}
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struct si_texture *tex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
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unsigned depth_coeff = dsa->depth_enabled ? 5 : 0;
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unsigned stencil_coeff = tex->surface.has_stencil && dsa->stencil_enabled ? 1 : 0;
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unsigned sum = 4 * (depth_coeff + stencil_coeff) * MAX2(tex->buffer.b.b.nr_samples, 1);
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static const si_bin_size_subtable table[] = {
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{
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// One RB / SE
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{
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// One shader engine
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{0, 64, 512},
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{2, 64, 256},
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{4, 64, 128},
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{7, 32, 128},
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{13, 16, 128},
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{49, 0, 0},
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},
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{
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// Two shader engines
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{0, 128, 512},
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{2, 64, 512},
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{4, 64, 256},
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{7, 64, 128},
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{13, 32, 128},
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{25, 16, 128},
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{49, 0, 0},
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},
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{
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// Four shader engines
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{0, 256, 512},
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{2, 128, 512},
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{4, 64, 512},
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{7, 64, 256},
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{13, 64, 128},
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{25, 16, 128},
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{49, 0, 0},
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},
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},
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{
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// Two RB / SE
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{
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// One shader engine
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{0, 128, 512},
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{2, 64, 512},
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{4, 64, 256},
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{7, 64, 128},
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{13, 32, 128},
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{25, 16, 128},
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{97, 0, 0},
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},
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{
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// Two shader engines
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{0, 256, 512},
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{2, 128, 512},
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{4, 64, 512},
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{7, 64, 256},
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{13, 64, 128},
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{25, 32, 128},
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{49, 16, 128},
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{97, 0, 0},
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},
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{
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// Four shader engines
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{0, 512, 512},
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{2, 256, 512},
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{4, 128, 512},
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{7, 64, 512},
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{13, 64, 256},
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{25, 64, 128},
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{49, 16, 128},
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{97, 0, 0},
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},
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},
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{
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// Four RB / SE
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{
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// One shader engine
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{0, 256, 512},
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{2, 128, 512},
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{4, 64, 512},
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{7, 64, 256},
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{13, 64, 128},
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{25, 32, 128},
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{49, 16, 128},
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{193, 0, 0},
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},
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{
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// Two shader engines
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{0, 512, 512},
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{2, 256, 512},
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{4, 128, 512},
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{7, 64, 512},
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{13, 64, 256},
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{25, 64, 128},
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{49, 32, 128},
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{97, 16, 128},
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{193, 0, 0},
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},
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{
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// Four shader engines
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{0, 512, 512},
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{4, 256, 512},
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{7, 128, 512},
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{13, 64, 512},
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{25, 32, 512},
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{49, 32, 256},
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{97, 16, 128},
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{193, 0, 0},
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},
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},
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};
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return si_find_bin_size(sctx->screen, table, sum);
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}
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static void gfx10_get_bin_sizes(struct si_context *sctx, unsigned cb_target_enabled_4bit,
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struct uvec2 *color_bin_size, struct uvec2 *depth_bin_size)
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{
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const unsigned ZsTagSize = 64;
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const unsigned ZsNumTags = 312;
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const unsigned CcTagSize = 1024;
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const unsigned CcReadTags = 31;
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const unsigned FcTagSize = 256;
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const unsigned FcReadTags = 44;
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const unsigned num_rbs = sctx->screen->info.max_render_backends;
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const unsigned num_pipes = MAX2(num_rbs, sctx->screen->info.num_tcc_blocks);
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const unsigned depthBinSizeTagPart =
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((ZsNumTags * num_rbs / num_pipes) * (ZsTagSize * num_pipes));
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const unsigned colorBinSizeTagPart =
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((CcReadTags * num_rbs / num_pipes) * (CcTagSize * num_pipes));
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const unsigned fmaskBinSizeTagPart =
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((FcReadTags * num_rbs / num_pipes) * (FcTagSize * num_pipes));
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const unsigned minBinSizeX = 128;
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const unsigned minBinSizeY = 64;
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const unsigned num_fragments = sctx->framebuffer.nr_color_samples;
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const unsigned num_samples = sctx->framebuffer.nr_samples;
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const bool ps_iter_sample = si_get_ps_iter_samples(sctx) >= 2;
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/* Calculate cColor and cFmask(if applicable) */
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unsigned cColor = 0;
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unsigned cFmask = 0;
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bool has_fmask = false;
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for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
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if (!sctx->framebuffer.state.cbufs[i])
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continue;
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struct si_texture *tex = (struct si_texture *)sctx->framebuffer.state.cbufs[i]->texture;
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const unsigned mmrt = num_fragments == 1 ? 1 : (ps_iter_sample ? num_fragments : 2);
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cColor += tex->surface.bpe * mmrt;
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if (num_samples >= 2 /* if FMASK is bound */) {
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const unsigned fragmentsLog2 = util_logbase2(num_fragments);
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const unsigned samplesLog2 = util_logbase2(num_samples);
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static const unsigned cFmaskMrt[4 /* fragments */][5 /* samples */] = {
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{0, 1, 1, 1, 2}, /* fragments = 1 */
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{0, 1, 1, 2, 4}, /* fragments = 2 */
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{0, 1, 1, 4, 8}, /* fragments = 4 */
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{0, 1, 2, 4, 8} /* fragments = 8 */
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};
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cFmask += cFmaskMrt[fragmentsLog2][samplesLog2];
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has_fmask = true;
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}
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}
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cColor = MAX2(cColor, 1u);
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const unsigned colorLog2Pixels = util_logbase2(colorBinSizeTagPart / cColor);
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const unsigned colorBinSizeX = 1 << ((colorLog2Pixels + 1) / 2); /* round up width */
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const unsigned colorBinSizeY = 1 << (colorLog2Pixels / 2); /* round down height */
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unsigned binSizeX = colorBinSizeX;
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unsigned binSizeY = colorBinSizeY;
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if (has_fmask) {
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cFmask = MAX2(cFmask, 1u);
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const unsigned fmaskLog2Pixels = util_logbase2(fmaskBinSizeTagPart / cFmask);
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const unsigned fmaskBinSizeX = 1 << ((fmaskLog2Pixels + 1) / 2); /* round up width */
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const unsigned fmaskBinSizeY = 1 << (fmaskLog2Pixels / 2); /* round down height */
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/* use the smaller of the Color vs. Fmask bin sizes */
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if (fmaskLog2Pixels < colorLog2Pixels) {
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binSizeX = fmaskBinSizeX;
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binSizeY = fmaskBinSizeY;
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}
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}
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/* Return size adjusted for minimum bin size */
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color_bin_size->x = MAX2(binSizeX, minBinSizeX);
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color_bin_size->y = MAX2(binSizeY, minBinSizeY);
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if (!sctx->framebuffer.state.zsbuf) {
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/* Set to max sizes when no depth buffer is bound. */
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depth_bin_size->x = 512;
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depth_bin_size->y = 512;
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} else {
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struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
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struct si_state_dsa *dsa = sctx->queued.named.dsa;
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const unsigned cPerDepthSample = dsa->depth_enabled ? 5 : 0;
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const unsigned cPerStencilSample = dsa->stencil_enabled ? 1 : 0;
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const unsigned cDepth =
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(cPerDepthSample + cPerStencilSample) * MAX2(zstex->buffer.b.b.nr_samples, 1);
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const unsigned depthLog2Pixels = util_logbase2(depthBinSizeTagPart / MAX2(cDepth, 1u));
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unsigned depthBinSizeX = 1 << ((depthLog2Pixels + 1) / 2);
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unsigned depthBinSizeY = 1 << (depthLog2Pixels / 2);
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depth_bin_size->x = MAX2(depthBinSizeX, minBinSizeX);
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depth_bin_size->y = MAX2(depthBinSizeY, minBinSizeY);
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}
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}
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static void si_emit_dpbb_disable(struct si_context *sctx)
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{
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radeon_begin(&sctx->gfx_cs);
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if (sctx->chip_class >= GFX10) {
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struct uvec2 bin_size = {};
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struct uvec2 bin_size_extend = {};
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bin_size.x = 128;
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bin_size.y = sctx->framebuffer.min_bytes_per_pixel <= 4 ? 128 : 64;
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if (bin_size.x >= 32)
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bin_size_extend.x = util_logbase2(bin_size.x) - 5;
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if (bin_size.y >= 32)
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bin_size_extend.y = util_logbase2(bin_size.y) - 5;
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radeon_opt_set_context_reg(
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sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
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S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
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S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
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S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
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S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | S_028C44_DISABLE_START_OF_PRIM(1) |
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S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->last_binning_enabled != 0));
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} else {
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radeon_opt_set_context_reg(
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sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
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S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
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S_028C44_DISABLE_START_OF_PRIM(1) |
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S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
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sctx->family == CHIP_VEGA20 ||
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sctx->family >= CHIP_RAVEN2) &&
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sctx->last_binning_enabled != 0));
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}
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radeon_end_update_context_roll(sctx);
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sctx->last_binning_enabled = false;
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}
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void si_emit_dpbb_state(struct si_context *sctx)
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{
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struct si_screen *sscreen = sctx->screen;
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struct si_state_blend *blend = sctx->queued.named.blend;
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struct si_state_dsa *dsa = sctx->queued.named.dsa;
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unsigned db_shader_control = sctx->ps_db_shader_control;
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assert(sctx->chip_class >= GFX9);
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if (!sscreen->dpbb_allowed || sctx->dpbb_force_off) {
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si_emit_dpbb_disable(sctx);
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return;
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}
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bool ps_can_kill =
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G_02880C_KILL_ENABLE(db_shader_control) || G_02880C_MASK_EXPORT_ENABLE(db_shader_control) ||
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G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control) || blend->alpha_to_coverage;
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bool db_can_reject_z_trivially = !G_02880C_Z_EXPORT_ENABLE(db_shader_control) ||
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G_02880C_CONSERVATIVE_Z_EXPORT(db_shader_control) ||
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G_02880C_DEPTH_BEFORE_SHADER(db_shader_control);
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/* Disable DPBB when it's believed to be inefficient. */
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if (sscreen->info.max_render_backends > 4 && ps_can_kill && db_can_reject_z_trivially &&
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sctx->framebuffer.state.zsbuf && dsa->db_can_write) {
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si_emit_dpbb_disable(sctx);
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return;
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}
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/* Compute the bin size. */
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/* TODO: We could also look at enabled pixel shader outputs. */
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unsigned cb_target_enabled_4bit =
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sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_enabled_4bit;
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struct uvec2 color_bin_size, depth_bin_size;
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if (sctx->chip_class >= GFX10) {
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gfx10_get_bin_sizes(sctx, cb_target_enabled_4bit, &color_bin_size, &depth_bin_size);
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} else {
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color_bin_size = si_get_color_bin_size(sctx, cb_target_enabled_4bit);
|
|
depth_bin_size = si_get_depth_bin_size(sctx);
|
|
}
|
|
|
|
unsigned color_area = color_bin_size.x * color_bin_size.y;
|
|
unsigned depth_area = depth_bin_size.x * depth_bin_size.y;
|
|
|
|
struct uvec2 bin_size = color_area < depth_area ? color_bin_size : depth_bin_size;
|
|
|
|
if (!bin_size.x || !bin_size.y) {
|
|
si_emit_dpbb_disable(sctx);
|
|
return;
|
|
}
|
|
|
|
/* Tunable parameters. */
|
|
unsigned fpovs_per_batch = 63; /* allowed range: [0, 255], 0 = unlimited */
|
|
|
|
/* Emit registers. */
|
|
struct uvec2 bin_size_extend = {};
|
|
if (bin_size.x >= 32)
|
|
bin_size_extend.x = util_logbase2(bin_size.x) - 5;
|
|
if (bin_size.y >= 32)
|
|
bin_size_extend.y = util_logbase2(bin_size.y) - 5;
|
|
|
|
radeon_begin(&sctx->gfx_cs);
|
|
radeon_opt_set_context_reg(
|
|
sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
|
|
S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) | S_028C44_BIN_SIZE_X(bin_size.x == 16) |
|
|
S_028C44_BIN_SIZE_Y(bin_size.y == 16) | S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
|
|
S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
|
|
S_028C44_CONTEXT_STATES_PER_BIN(sscreen->pbb_context_states_per_bin - 1) |
|
|
S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) |
|
|
S_028C44_DISABLE_START_OF_PRIM(1) |
|
|
S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1) |
|
|
S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
|
|
sctx->family == CHIP_VEGA20 ||
|
|
sctx->family >= CHIP_RAVEN2) &&
|
|
sctx->last_binning_enabled != 1));
|
|
radeon_end_update_context_roll(sctx);
|
|
|
|
sctx->last_binning_enabled = true;
|
|
}
|