878 lines
31 KiB
C
878 lines
31 KiB
C
/*
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* Copyright (c) 2012-2015 Etnaviv Project
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Wladimir J. van der Laan <laanwj@gmail.com>
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* Christian Gmeiner <christian.gmeiner@gmail.com>
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*/
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#include "etnaviv_state.h"
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#include "hw/common.xml.h"
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#include "etnaviv_blend.h"
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#include "etnaviv_clear_blit.h"
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#include "etnaviv_context.h"
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#include "etnaviv_format.h"
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#include "etnaviv_rasterizer.h"
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#include "etnaviv_screen.h"
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#include "etnaviv_shader.h"
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#include "etnaviv_surface.h"
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#include "etnaviv_translate.h"
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#include "etnaviv_util.h"
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#include "etnaviv_zsa.h"
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#include "util/u_framebuffer.h"
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#include "util/u_helpers.h"
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#include "util/u_inlines.h"
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#include "util/u_math.h"
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#include "util/u_memory.h"
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#include "util/u_upload_mgr.h"
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static void
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etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref sr)
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{
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struct etna_context *ctx = etna_context(pctx);
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struct compiled_stencil_ref *cs = &ctx->stencil_ref;
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ctx->stencil_ref_s = sr;
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for (unsigned i = 0; i < 2; i++) {
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cs->PE_STENCIL_CONFIG[i] =
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VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr.ref_value[i]);
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cs->PE_STENCIL_CONFIG_EXT[i] =
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VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr.ref_value[!i]);
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}
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ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
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}
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static void
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etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
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{
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/* NOOP */
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}
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static void
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etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
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{
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struct etna_context *ctx = etna_context(pctx);
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ctx->sample_mask = sample_mask;
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ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
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}
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static void
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etna_set_constant_buffer(struct pipe_context *pctx,
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enum pipe_shader_type shader, uint index, bool take_ownership,
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const struct pipe_constant_buffer *cb)
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{
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struct etna_context *ctx = etna_context(pctx);
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struct etna_constbuf_state *so = &ctx->constant_buffer[shader];
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assert(index < ETNA_MAX_CONST_BUF);
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util_copy_constant_buffer(&so->cb[index], cb, take_ownership);
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/* Note that the gallium frontends can unbind constant buffers by
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* passing NULL here. */
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if (unlikely(!cb || (!cb->buffer && !cb->user_buffer))) {
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so->enabled_mask &= ~(1 << index);
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return;
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}
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assert(index != 0 || cb->user_buffer != NULL);
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if (!cb->buffer) {
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struct pipe_constant_buffer *cb = &so->cb[index];
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u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
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}
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so->enabled_mask |= 1 << index;
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ctx->dirty |= ETNA_DIRTY_CONSTBUF;
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}
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static void
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etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base)
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{
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struct etna_resource *to = base, *from = base;
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if (base->texture && etna_resource_newer(etna_resource(base->texture), base))
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from = etna_resource(base->texture);
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if (base->render)
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to = etna_resource(base->render);
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if ((to != from) && etna_resource_older(to, from)) {
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etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level);
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to->seqno = from->seqno;
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}
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}
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static void
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etna_set_framebuffer_state(struct pipe_context *pctx,
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const struct pipe_framebuffer_state *fb)
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{
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struct etna_context *ctx = etna_context(pctx);
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struct etna_screen *screen = ctx->screen;
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struct compiled_framebuffer_state *cs = &ctx->framebuffer;
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int nr_samples_color = -1;
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int nr_samples_depth = -1;
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bool target_16bpp = false;
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bool target_linear = false;
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/* Set up TS as well. Warning: this state is used by both the RS and PE */
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uint32_t ts_mem_config = 0;
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uint32_t pe_mem_config = 0;
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uint32_t pe_logic_op = 0;
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if (fb->nr_cbufs > 0) { /* at least one color buffer? */
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struct etna_surface *cbuf = etna_surface(fb->cbufs[0]);
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struct etna_resource *res = etna_resource(cbuf->base.texture);
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bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
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uint32_t fmt = translate_pe_format(cbuf->base.format);
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assert((res->layout & ETNA_LAYOUT_BIT_TILE) ||
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VIV_FEATURE(screen, chipMinorFeatures2, LINEAR_PE));
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etna_update_render_resource(pctx, etna_resource(cbuf->prsc));
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if (res->layout == ETNA_LAYOUT_LINEAR)
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target_linear = true;
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if (fmt >= PE_FORMAT_R16F)
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cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) |
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VIVS_PE_COLOR_FORMAT_FORMAT_MASK;
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else
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cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt);
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if (util_format_get_blocksize(cbuf->base.format) <= 2)
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target_16bpp = true;
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cs->PE_COLOR_FORMAT |=
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VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
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VIVS_PE_COLOR_FORMAT_OVERWRITE |
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COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED);
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if (VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE))
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cs->PE_COLOR_FORMAT |= COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
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/* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
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* VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
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* but only if we set the bits above. */
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/* merged with depth_stencil_alpha */
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if ((cbuf->surf.offset & 63) ||
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(((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
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/* XXX Must make temporary surface here.
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* Need the same mechanism on gc2000 when we want to do mipmap
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* generation by
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* rendering to levels > 1 due to multitiled / tiled conversion. */
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BUG("Alignment error, trying to render to offset %08x with tile "
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"stride %i",
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cbuf->surf.offset, cbuf->surf.stride * 4);
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}
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if (screen->specs.halti >= 0) {
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/* Rendertargets on GPUs with more than a single pixel pipe must always
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* be multi-tiled, or single-buffer mode must be supported */
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assert(screen->specs.pixel_pipes == 1 ||
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(res->layout & ETNA_LAYOUT_BIT_MULTI) || screen->specs.single_buffer);
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for (int i = 0; i < screen->specs.pixel_pipes; i++) {
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cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
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cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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}
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} else {
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cs->PE_COLOR_ADDR = cbuf->reloc[0];
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cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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}
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cs->PE_COLOR_STRIDE = cbuf->surf.stride;
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if (cbuf->surf.ts_size) {
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cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
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cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32;
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cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
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cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
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cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
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if (cbuf->level->ts_compress_fmt >= 0) {
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/* overwrite bit breaks v1/v2 compression */
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if (!screen->specs.v4_compression)
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cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
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ts_mem_config |=
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VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
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VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
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}
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}
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nr_samples_color = cbuf->base.texture->nr_samples;
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if (util_format_is_srgb(cbuf->base.format))
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pe_logic_op |= VIVS_PE_LOGIC_OP_SRGB;
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cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0);
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cs->PS_CONTROL_EXT =
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VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, screen->specs.halti >= 5));
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} else {
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/* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
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* VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
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* color target */
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cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
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cs->PE_COLOR_STRIDE = 0;
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cs->TS_COLOR_STATUS_BASE.bo = NULL;
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cs->TS_COLOR_SURFACE_BASE.bo = NULL;
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cs->PE_COLOR_ADDR = screen->dummy_rt_reloc;
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for (int i = 0; i < screen->specs.pixel_pipes; i++)
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cs->PE_PIPE_COLOR_ADDR[i] = screen->dummy_rt_reloc;
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}
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if (fb->zsbuf != NULL) {
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struct etna_surface *zsbuf = etna_surface(fb->zsbuf);
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struct etna_resource *res = etna_resource(zsbuf->base.texture);
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etna_update_render_resource(pctx, etna_resource(zsbuf->prsc));
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assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
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uint32_t depth_format = translate_depth_format(zsbuf->base.format);
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unsigned depth_bits =
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depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
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bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
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if (depth_bits == 16)
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target_16bpp = true;
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cs->PE_DEPTH_CONFIG =
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depth_format |
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COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
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VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
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VIVS_PE_DEPTH_CONFIG_UNK18; /* something to do with clipping? */
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/* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
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/* merged with depth_stencil_alpha */
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if (screen->specs.halti >= 0) {
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for (int i = 0; i < screen->specs.pixel_pipes; i++) {
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cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
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cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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}
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} else {
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cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
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cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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}
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cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
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cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
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cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
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if (zsbuf->surf.ts_size) {
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cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
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cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
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cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
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cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
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if (zsbuf->level->ts_compress_fmt >= 0) {
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ts_mem_config |=
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VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
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COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
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VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
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}
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}
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ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
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nr_samples_depth = zsbuf->base.texture->nr_samples;
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} else {
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cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
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cs->PE_DEPTH_ADDR.bo = NULL;
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cs->PE_DEPTH_STRIDE = 0;
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cs->TS_DEPTH_STATUS_BASE.bo = NULL;
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cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
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for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
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cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
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}
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/* MSAA setup */
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if (nr_samples_depth != -1 && nr_samples_color != -1 &&
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nr_samples_depth != nr_samples_color) {
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BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
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nr_samples_color, nr_samples_depth);
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}
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switch (MAX2(nr_samples_depth, nr_samples_color)) {
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case 0:
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case 1: /* Are 0 and 1 samples allowed? */
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cs->GL_MULTI_SAMPLE_CONFIG =
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VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
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cs->msaa_mode = false;
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break;
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case 2:
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cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
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cs->msaa_mode = true; /* Add input to PS */
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cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
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cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
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cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
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cs->RA_CENTROID_TABLE[1] = 0x88558800;
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cs->RA_CENTROID_TABLE[2] = 0x88881100;
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cs->RA_CENTROID_TABLE[3] = 0x33888800;
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break;
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case 4:
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cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
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cs->msaa_mode = true; /* Add input to PS */
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cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
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cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
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cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
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cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
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cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
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cs->RA_CENTROID_TABLE[1] = 0x888888a2;
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cs->RA_CENTROID_TABLE[2] = 0x888888ea;
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cs->RA_CENTROID_TABLE[3] = 0x888888c6;
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cs->RA_CENTROID_TABLE[4] = 0x46622a88;
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cs->RA_CENTROID_TABLE[5] = 0x888888ae;
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cs->RA_CENTROID_TABLE[6] = 0x888888e6;
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cs->RA_CENTROID_TABLE[7] = 0x888888ca;
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cs->RA_CENTROID_TABLE[8] = 0x262a2288;
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cs->RA_CENTROID_TABLE[9] = 0x886688a2;
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cs->RA_CENTROID_TABLE[10] = 0x888866aa;
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cs->RA_CENTROID_TABLE[11] = 0x668888a6;
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break;
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}
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cs->TS_MEM_CONFIG = ts_mem_config;
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cs->PE_MEM_CONFIG = pe_mem_config;
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/* Single buffer setup. There is only one switch for this, not a separate
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* one per color buffer / depth buffer. To keep the logic simple always use
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* single buffer when this feature is available.
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*/
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if (unlikely(target_linear))
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pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(1);
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else if (screen->specs.single_buffer)
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pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(target_16bpp ? 3 : 2);
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cs->PE_LOGIC_OP = pe_logic_op;
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/* keep copy of original structure */
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util_copy_framebuffer_state(&ctx->framebuffer_s, fb);
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ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
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}
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static void
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etna_set_polygon_stipple(struct pipe_context *pctx,
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const struct pipe_poly_stipple *stipple)
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{
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/* NOP */
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}
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static void
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etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
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unsigned num_scissors, const struct pipe_scissor_state *ss)
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{
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struct etna_context *ctx = etna_context(pctx);
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assert(ss->minx <= ss->maxx);
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assert(ss->miny <= ss->maxy);
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ctx->scissor = *ss;
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ctx->dirty |= ETNA_DIRTY_SCISSOR;
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}
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static void
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etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
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unsigned num_scissors, const struct pipe_viewport_state *vs)
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{
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struct etna_context *ctx = etna_context(pctx);
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struct compiled_viewport_state *cs = &ctx->viewport;
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ctx->viewport_s = *vs;
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/**
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* For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
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* -1..1 to 0..1.
|
|
* scaling and translation to 0..1 already happened, so remove that
|
|
*
|
|
* z' = (z * 2 - 1) * scale + translate
|
|
* = z * (2 * scale) + (translate - scale)
|
|
*
|
|
* scale' = 2 * scale
|
|
* translate' = translate - scale
|
|
*/
|
|
|
|
/* must be fixp as v4 state deltas assume it is */
|
|
cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
|
|
cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
|
|
cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
|
|
cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
|
|
cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
|
|
cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
|
|
|
|
/* Compute scissor rectangle (fixp) from viewport.
|
|
* Make sure left is always < right and top always < bottom.
|
|
*/
|
|
cs->SE_SCISSOR_LEFT = MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f);
|
|
cs->SE_SCISSOR_TOP = MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f);
|
|
cs->SE_SCISSOR_RIGHT = ceilf(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
|
|
cs->SE_SCISSOR_BOTTOM = ceilf(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
|
|
|
|
cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
|
|
cs->PE_DEPTH_FAR = fui(1.0);
|
|
ctx->dirty |= ETNA_DIRTY_VIEWPORT;
|
|
}
|
|
|
|
static void
|
|
etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
|
|
unsigned num_buffers, unsigned unbind_num_trailing_slots, bool take_ownership,
|
|
const struct pipe_vertex_buffer *vb)
|
|
{
|
|
struct etna_context *ctx = etna_context(pctx);
|
|
struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
|
|
|
|
util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot,
|
|
num_buffers, unbind_num_trailing_slots,
|
|
take_ownership);
|
|
so->count = util_last_bit(so->enabled_mask);
|
|
|
|
for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
|
|
struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
|
|
struct pipe_vertex_buffer *vbi = &so->vb[idx];
|
|
|
|
assert(!vbi->is_user_buffer); /* XXX support user_buffer using
|
|
etna_usermem_map */
|
|
|
|
if (vbi->buffer.resource) { /* GPU buffer */
|
|
cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
|
|
cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
|
|
cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
|
|
cs->FE_VERTEX_STREAM_CONTROL =
|
|
FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
|
|
} else {
|
|
cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
|
|
cs->FE_VERTEX_STREAM_CONTROL = 0;
|
|
}
|
|
}
|
|
|
|
ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
|
|
}
|
|
|
|
static void
|
|
etna_blend_state_bind(struct pipe_context *pctx, void *bs)
|
|
{
|
|
struct etna_context *ctx = etna_context(pctx);
|
|
|
|
ctx->blend = bs;
|
|
ctx->dirty |= ETNA_DIRTY_BLEND;
|
|
}
|
|
|
|
static void
|
|
etna_blend_state_delete(struct pipe_context *pctx, void *bs)
|
|
{
|
|
FREE(bs);
|
|
}
|
|
|
|
static void
|
|
etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
|
|
{
|
|
struct etna_context *ctx = etna_context(pctx);
|
|
|
|
ctx->rasterizer = rs;
|
|
ctx->dirty |= ETNA_DIRTY_RASTERIZER;
|
|
}
|
|
|
|
static void
|
|
etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
|
|
{
|
|
FREE(rs);
|
|
}
|
|
|
|
static void
|
|
etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
|
|
{
|
|
struct etna_context *ctx = etna_context(pctx);
|
|
|
|
ctx->zsa = zs;
|
|
ctx->dirty |= ETNA_DIRTY_ZSA;
|
|
}
|
|
|
|
static void
|
|
etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
|
|
{
|
|
FREE(zs);
|
|
}
|
|
|
|
/** Create vertex element states, which define a layout for fetching
|
|
* vertices for rendering.
|
|
*/
|
|
static void *
|
|
etna_vertex_elements_state_create(struct pipe_context *pctx,
|
|
unsigned num_elements, const struct pipe_vertex_element *elements)
|
|
{
|
|
struct etna_context *ctx = etna_context(pctx);
|
|
struct etna_screen *screen = ctx->screen;
|
|
struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
|
|
|
|
if (!cs)
|
|
return NULL;
|
|
|
|
if (num_elements > screen->specs.vertex_max_elements) {
|
|
BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
|
|
screen->specs.vertex_max_elements);
|
|
FREE(cs);
|
|
return NULL;
|
|
}
|
|
|
|
/* XXX could minimize number of consecutive stretches here by sorting, and
|
|
* permuting the inputs in shader or does Mesa do this already? */
|
|
|
|
cs->num_elements = num_elements;
|
|
|
|
unsigned start_offset = 0; /* start of current consecutive stretch */
|
|
bool nonconsecutive = true; /* previous value of nonconsecutive */
|
|
uint32_t buffer_mask = 0; /* mask of buffer_idx already seen */
|
|
|
|
for (unsigned idx = 0; idx < num_elements; ++idx) {
|
|
unsigned buffer_idx = elements[idx].vertex_buffer_index;
|
|
unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
|
|
unsigned end_offset = elements[idx].src_offset + element_size;
|
|
uint32_t format_type, normalize;
|
|
|
|
if (nonconsecutive)
|
|
start_offset = elements[idx].src_offset;
|
|
|
|
/* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */
|
|
assert(buffer_idx < screen->specs.stream_count);
|
|
|
|
/* maximum vertex size is 256 bytes */
|
|
assert(element_size != 0 && (end_offset - start_offset) < 256);
|
|
|
|
/* check whether next element is consecutive to this one */
|
|
nonconsecutive = (idx == (num_elements - 1)) ||
|
|
elements[idx + 1].vertex_buffer_index != buffer_idx ||
|
|
end_offset != elements[idx + 1].src_offset;
|
|
|
|
format_type = translate_vertex_format_type(elements[idx].src_format);
|
|
normalize = translate_vertex_format_normalize(elements[idx].src_format);
|
|
|
|
assert(format_type != ETNA_NO_MATCH);
|
|
assert(normalize != ETNA_NO_MATCH);
|
|
|
|
if (screen->specs.halti < 5) {
|
|
cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
|
|
COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
|
|
format_type |
|
|
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
|
|
normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
|
|
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(buffer_idx) |
|
|
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
|
|
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
|
|
} else { /* HALTI5 spread vertex attrib config over two registers */
|
|
cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
|
|
format_type |
|
|
VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
|
|
normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
|
|
VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(buffer_idx) |
|
|
VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
|
|
cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
|
|
COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
|
|
VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
|
|
}
|
|
|
|
if (util_format_is_pure_integer(elements[idx].src_format))
|
|
cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1;
|
|
else
|
|
cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f);
|
|
|
|
/* instance_divisor is part of elements state but should be the same for all buffers */
|
|
if (buffer_mask & 1 << buffer_idx)
|
|
assert(cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] == elements[idx].instance_divisor);
|
|
else
|
|
cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] = elements[idx].instance_divisor;
|
|
|
|
buffer_mask |= 1 << buffer_idx;
|
|
cs->num_buffers = MAX2(cs->num_buffers, buffer_idx + 1);
|
|
}
|
|
|
|
return cs;
|
|
}
|
|
|
|
static void
|
|
etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
|
|
{
|
|
FREE(ve);
|
|
}
|
|
|
|
static void
|
|
etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
|
|
{
|
|
struct etna_context *ctx = etna_context(pctx);
|
|
|
|
ctx->vertex_elements = ve;
|
|
ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
|
|
}
|
|
|
|
static void
|
|
etna_set_stream_output_targets(struct pipe_context *pctx,
|
|
unsigned num_targets, struct pipe_stream_output_target **targets,
|
|
const unsigned *offsets)
|
|
{
|
|
/* stub */
|
|
}
|
|
|
|
static bool
|
|
etna_update_ts_config(struct etna_context *ctx)
|
|
{
|
|
uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
|
|
|
|
if (ctx->framebuffer_s.nr_cbufs > 0) {
|
|
struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
|
|
|
|
if(c_surf->level->ts_size && c_surf->level->ts_valid) {
|
|
new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
|
|
} else {
|
|
new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
|
|
}
|
|
}
|
|
|
|
if (ctx->framebuffer_s.zsbuf) {
|
|
struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
|
|
|
|
if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
|
|
new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
|
|
} else {
|
|
new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
|
|
}
|
|
}
|
|
|
|
if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
|
|
(ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
|
|
ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
|
|
ctx->dirty |= ETNA_DIRTY_TS;
|
|
}
|
|
|
|
ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
etna_update_clipping(struct etna_context *ctx)
|
|
{
|
|
const struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
|
|
const struct pipe_framebuffer_state *fb = &ctx->framebuffer_s;
|
|
|
|
/* clip framebuffer against viewport */
|
|
uint32_t scissor_left = ctx->viewport.SE_SCISSOR_LEFT;
|
|
uint32_t scissor_top = ctx->viewport.SE_SCISSOR_TOP;
|
|
uint32_t scissor_right = MIN2(fb->width, ctx->viewport.SE_SCISSOR_RIGHT);
|
|
uint32_t scissor_bottom = MIN2(fb->height, ctx->viewport.SE_SCISSOR_BOTTOM);
|
|
|
|
/* clip against scissor */
|
|
if (rasterizer->scissor) {
|
|
scissor_left = MAX2(ctx->scissor.minx, scissor_left);
|
|
scissor_top = MAX2(ctx->scissor.miny, scissor_top);
|
|
scissor_right = MIN2(ctx->scissor.maxx, scissor_right);
|
|
scissor_bottom = MIN2(ctx->scissor.maxy, scissor_bottom);
|
|
}
|
|
|
|
ctx->clipping.minx = scissor_left;
|
|
ctx->clipping.miny = scissor_top;
|
|
ctx->clipping.maxx = scissor_right;
|
|
ctx->clipping.maxy = scissor_bottom;
|
|
|
|
ctx->dirty |= ETNA_DIRTY_SCISSOR_CLIP;
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
etna_update_zsa(struct etna_context *ctx)
|
|
{
|
|
struct compiled_shader_state *shader_state = &ctx->shader_state;
|
|
struct pipe_depth_stencil_alpha_state *zsa_state = ctx->zsa;
|
|
struct etna_zsa_state *zsa = etna_zsa_state(zsa_state);
|
|
struct etna_screen *screen = ctx->screen;
|
|
uint32_t new_pe_depth, new_ra_depth;
|
|
bool late_z_write = false, early_z_write = false,
|
|
late_z_test = false, early_z_test = false;
|
|
|
|
if (zsa->z_write_enabled) {
|
|
if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH) &&
|
|
!VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z) &&
|
|
!zsa->stencil_enabled &&
|
|
!zsa_state->alpha_enabled &&
|
|
!shader_state->writes_z &&
|
|
!shader_state->uses_discard)
|
|
early_z_write = true;
|
|
else
|
|
late_z_write = true;
|
|
}
|
|
|
|
if (zsa->z_test_enabled) {
|
|
if (!VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z) &&
|
|
!zsa->stencil_modified &&
|
|
!shader_state->writes_z)
|
|
early_z_test = true;
|
|
else
|
|
late_z_test = true;
|
|
}
|
|
|
|
/* Linear PE breaks the combination of early test with late write, as it
|
|
* seems RA and PE disagree about the cache layout in this mode. Switch to
|
|
* late test to work around this issue.
|
|
*/
|
|
if (ctx->framebuffer_s.nr_cbufs > 0) {
|
|
struct etna_surface *cbuf = etna_surface(ctx->framebuffer_s.cbufs[0]);
|
|
struct etna_resource *res = etna_resource(cbuf->base.texture);
|
|
|
|
if (res->layout == ETNA_LAYOUT_LINEAR && early_z_test && late_z_write) {
|
|
early_z_test = false;
|
|
late_z_test = true;
|
|
}
|
|
}
|
|
|
|
new_pe_depth = VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(zsa->z_test_enabled ?
|
|
/* compare funcs have 1 to 1 mapping */
|
|
zsa_state->depth_func : PIPE_FUNC_ALWAYS) |
|
|
COND(zsa->z_write_enabled, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) |
|
|
COND(early_z_test, VIVS_PE_DEPTH_CONFIG_EARLY_Z) |
|
|
COND(!late_z_write && !late_z_test && !zsa->stencil_enabled,
|
|
VIVS_PE_DEPTH_CONFIG_DISABLE_ZS);
|
|
|
|
/* blob sets this to 0x40000031 on GC7000, seems to make no difference,
|
|
* but keep it in mind if depth behaves strangely. */
|
|
new_ra_depth = 0x0000030 |
|
|
COND(early_z_test, VIVS_RA_EARLY_DEPTH_TEST_ENABLE);
|
|
|
|
if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH)) {
|
|
if (!early_z_write)
|
|
new_ra_depth |= VIVS_RA_EARLY_DEPTH_WRITE_DISABLE;
|
|
/* The new early hierarchical test seems to only work properly if depth
|
|
* is also written from the early stage.
|
|
*/
|
|
if (late_z_test || (early_z_test && late_z_write))
|
|
new_ra_depth |= VIVS_RA_EARLY_DEPTH_HDEPTH_DISABLE;
|
|
}
|
|
|
|
if (new_pe_depth != zsa->PE_DEPTH_CONFIG ||
|
|
new_ra_depth != zsa->RA_DEPTH_CONFIG)
|
|
ctx->dirty |= ETNA_DIRTY_ZSA;
|
|
|
|
zsa->PE_DEPTH_CONFIG = new_pe_depth;
|
|
zsa->RA_DEPTH_CONFIG = new_ra_depth;
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
etna_record_flush_resources(struct etna_context *ctx)
|
|
{
|
|
struct pipe_framebuffer_state *fb = &ctx->framebuffer_s;
|
|
|
|
if (fb->nr_cbufs > 0) {
|
|
struct etna_surface *surf = etna_surface(fb->cbufs[0]);
|
|
|
|
if (!etna_resource(surf->prsc)->explicit_flush)
|
|
_mesa_set_add(ctx->flush_resources, surf->prsc);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
struct etna_state_updater {
|
|
bool (*update)(struct etna_context *ctx);
|
|
uint32_t dirty;
|
|
};
|
|
|
|
static const struct etna_state_updater etna_state_updates[] = {
|
|
{
|
|
etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
|
|
},
|
|
{
|
|
etna_shader_link, ETNA_DIRTY_SHADER,
|
|
},
|
|
{
|
|
etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
|
|
},
|
|
{
|
|
etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
|
|
},
|
|
{
|
|
etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
|
|
},
|
|
{
|
|
etna_update_clipping, ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
|
|
ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT,
|
|
},
|
|
{
|
|
etna_update_zsa, ETNA_DIRTY_ZSA | ETNA_DIRTY_SHADER |
|
|
ETNA_DIRTY_FRAMEBUFFER,
|
|
},
|
|
{
|
|
etna_record_flush_resources, ETNA_DIRTY_FRAMEBUFFER,
|
|
}
|
|
};
|
|
|
|
bool
|
|
etna_state_update(struct etna_context *ctx)
|
|
{
|
|
for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
|
|
if (ctx->dirty & etna_state_updates[i].dirty)
|
|
if (!etna_state_updates[i].update(ctx))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
void
|
|
etna_state_init(struct pipe_context *pctx)
|
|
{
|
|
pctx->set_blend_color = etna_set_blend_color;
|
|
pctx->set_stencil_ref = etna_set_stencil_ref;
|
|
pctx->set_clip_state = etna_set_clip_state;
|
|
pctx->set_sample_mask = etna_set_sample_mask;
|
|
pctx->set_constant_buffer = etna_set_constant_buffer;
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pctx->set_framebuffer_state = etna_set_framebuffer_state;
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pctx->set_polygon_stipple = etna_set_polygon_stipple;
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pctx->set_scissor_states = etna_set_scissor_states;
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pctx->set_viewport_states = etna_set_viewport_states;
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|
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pctx->set_vertex_buffers = etna_set_vertex_buffers;
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|
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pctx->bind_blend_state = etna_blend_state_bind;
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|
pctx->delete_blend_state = etna_blend_state_delete;
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|
|
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pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
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|
pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
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|
|
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pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
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|
pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
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|
|
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pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
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|
pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
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pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
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|
|
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pctx->set_stream_output_targets = etna_set_stream_output_targets;
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}
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