400 lines
14 KiB
C++
400 lines
14 KiB
C++
/****************************************************************************
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* Copyright (C) 2015 Intel Corporation. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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***************************************************************************/
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#include "swr_screen.h"
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#include "swr_context.h"
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#include "swr_resource.h"
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#include "swr_fence.h"
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#include "swr_query.h"
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#include "jit_api.h"
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#include "util/u_draw.h"
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#include "util/u_prim.h"
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#include <algorithm>
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#include <iostream>
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/*
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* Draw vertex arrays, with optional indexing, optional instancing.
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*/
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static void
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swr_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info,
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unsigned drawid_offset,
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const struct pipe_draw_indirect_info *indirect,
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const struct pipe_draw_start_count_bias *draws,
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unsigned num_draws)
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{
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if (num_draws > 1) {
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struct pipe_draw_info tmp_info = *info;
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unsigned drawid = drawid_offset;
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for (unsigned i = 0; i < num_draws; i++) {
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swr_draw_vbo(pipe, &tmp_info, drawid, indirect, &draws[i], 1);
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if (tmp_info.increment_draw_id)
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drawid++;
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}
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return;
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}
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if (!indirect && (!draws[0].count || !info->instance_count))
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return;
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struct swr_context *ctx = swr_context(pipe);
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if (!indirect &&
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!info->primitive_restart &&
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!u_trim_pipe_prim(info->mode, (unsigned*)&draws[0].count))
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return;
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if (!swr_check_render_cond(pipe))
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return;
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if (indirect && indirect->buffer) {
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util_draw_indirect(pipe, info, indirect);
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return;
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}
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/* If indexed draw, force vertex validation since index buffer comes
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* from draw info. */
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if (info->index_size)
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ctx->dirty |= SWR_NEW_VERTEX;
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/* Update derived state, pass draw info to update function. */
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swr_update_derived(pipe, info, draws);
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swr_update_draw_context(ctx);
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struct pipe_draw_info resolved_info;
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struct pipe_draw_start_count_bias resolved_draw;
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/* DrawTransformFeedback */
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if (indirect && indirect->count_from_stream_output) {
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// trick copied from softpipe to modify const struct *info
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memcpy(&resolved_info, (void*)info, sizeof(struct pipe_draw_info));
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resolved_draw.start = draws[0].start;
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resolved_draw.count = ctx->so_primCounter * ctx->patch_vertices;
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resolved_info.max_index = resolved_draw.count - 1;
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info = &resolved_info;
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indirect = NULL;
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draws = &resolved_draw;
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}
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if (ctx->vs->pipe.stream_output.num_outputs) {
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if (!ctx->vs->soFunc[info->mode]) {
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STREAMOUT_COMPILE_STATE state = {0};
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struct pipe_stream_output_info *so = &ctx->vs->pipe.stream_output;
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state.numVertsPerPrim = u_vertices_per_prim(info->mode);
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uint32_t offsets[MAX_SO_STREAMS] = {0};
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uint32_t num = 0;
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for (uint32_t i = 0; i < so->num_outputs; i++) {
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assert(so->output[i].stream == 0); // @todo
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uint32_t output_buffer = so->output[i].output_buffer;
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if (so->output[i].dst_offset != offsets[output_buffer]) {
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// hole - need to fill
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state.stream.decl[num].bufferIndex = output_buffer;
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state.stream.decl[num].hole = true;
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state.stream.decl[num].componentMask =
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(1 << (so->output[i].dst_offset - offsets[output_buffer]))
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- 1;
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num++;
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offsets[output_buffer] = so->output[i].dst_offset;
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}
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unsigned attrib_slot = so->output[i].register_index;
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attrib_slot = swr_so_adjust_attrib(attrib_slot, ctx->vs);
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state.stream.decl[num].bufferIndex = output_buffer;
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state.stream.decl[num].attribSlot = attrib_slot;
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state.stream.decl[num].componentMask =
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((1 << so->output[i].num_components) - 1)
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<< so->output[i].start_component;
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state.stream.decl[num].hole = false;
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num++;
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offsets[output_buffer] += so->output[i].num_components;
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}
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state.stream.numDecls = num;
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HANDLE hJitMgr = swr_screen(pipe->screen)->hJitMgr;
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ctx->vs->soFunc[info->mode] = JitCompileStreamout(hJitMgr, state);
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debug_printf("so shader %p\n", ctx->vs->soFunc[info->mode]);
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assert(ctx->vs->soFunc[info->mode] && "Error: SoShader = NULL");
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}
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ctx->api.pfnSwrSetSoFunc(ctx->swrContext, ctx->vs->soFunc[info->mode], 0);
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}
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struct swr_vertex_element_state *velems = ctx->velems;
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if (info->primitive_restart)
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velems->fsState.cutIndex = info->restart_index;
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else
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velems->fsState.cutIndex = 0;
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velems->fsState.bEnableCutIndex = info->primitive_restart;
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velems->fsState.bPartialVertexBuffer = (info->index_bounds_valid && info->min_index > 0);
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swr_jit_fetch_key key;
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swr_generate_fetch_key(key, velems);
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auto search = velems->map.find(key);
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if (search != velems->map.end()) {
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velems->fsFunc = search->second;
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} else {
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HANDLE hJitMgr = swr_screen(ctx->pipe.screen)->hJitMgr;
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velems->fsFunc = JitCompileFetch(hJitMgr, velems->fsState);
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debug_printf("fetch shader %p\n", velems->fsFunc);
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assert(velems->fsFunc && "Error: FetchShader = NULL");
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velems->map.insert(std::make_pair(key, velems->fsFunc));
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}
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ctx->api.pfnSwrSetFetchFunc(ctx->swrContext, velems->fsFunc);
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/* Set up frontend state
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* XXX setup provokingVertex & topologyProvokingVertex */
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SWR_FRONTEND_STATE feState = {0};
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// feState.vsVertexSize seeds the PA size that is used as an interface
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// between all the shader stages, so it has to be large enough to
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// incorporate all interfaces between stages
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// max of frontend shaders num_outputs
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feState.vsVertexSize = ctx->vs->info.base.num_outputs;
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if (ctx->gs) {
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feState.vsVertexSize = std::max(feState.vsVertexSize, (uint32_t)ctx->gs->info.base.num_outputs);
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}
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if (ctx->tcs) {
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feState.vsVertexSize = std::max(feState.vsVertexSize, (uint32_t)ctx->tcs->info.base.num_outputs);
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}
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if (ctx->tes) {
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feState.vsVertexSize = std::max(feState.vsVertexSize, (uint32_t)ctx->tes->info.base.num_outputs);
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}
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if (ctx->vs->info.base.num_outputs) {
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// gs does not adjust for position in SGV slot at input from vs
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if (!ctx->gs && !ctx->tcs && !ctx->tes)
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feState.vsVertexSize--;
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}
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// other (non-SGV) slots start at VERTEX_ATTRIB_START_SLOT
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feState.vsVertexSize += VERTEX_ATTRIB_START_SLOT;
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// The PA in the clipper does not handle BE vertex sizes
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// different from FE. Increase vertexsize only for the cases that needed it
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// primid needs a slot
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if (ctx->fs->info.base.uses_primid)
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feState.vsVertexSize++;
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// sprite coord enable
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if (ctx->rasterizer->sprite_coord_enable)
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feState.vsVertexSize++;
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if (ctx->rasterizer->flatshade_first) {
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feState.provokingVertex = {1, 0, 0};
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} else {
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feState.provokingVertex = {2, 1, 2};
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}
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enum pipe_prim_type topology;
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if (ctx->gs)
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topology = (pipe_prim_type)ctx->gs->info.base.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
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else
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topology = info->mode;
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switch (topology) {
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case PIPE_PRIM_TRIANGLE_FAN:
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feState.topologyProvokingVertex = feState.provokingVertex.triFan;
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break;
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case PIPE_PRIM_TRIANGLE_STRIP:
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case PIPE_PRIM_TRIANGLES:
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feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
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break;
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case PIPE_PRIM_QUAD_STRIP:
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case PIPE_PRIM_QUADS:
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if (ctx->rasterizer->flatshade_first)
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feState.topologyProvokingVertex = 0;
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else
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feState.topologyProvokingVertex = 3;
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break;
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case PIPE_PRIM_LINES:
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case PIPE_PRIM_LINE_LOOP:
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case PIPE_PRIM_LINE_STRIP:
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feState.topologyProvokingVertex = feState.provokingVertex.lineStripList;
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break;
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default:
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feState.topologyProvokingVertex = 0;
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}
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feState.bEnableCutIndex = info->primitive_restart;
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ctx->api.pfnSwrSetFrontendState(ctx->swrContext, &feState);
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if (info->index_size)
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ctx->api.pfnSwrDrawIndexedInstanced(ctx->swrContext,
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swr_convert_prim_topology(info->mode, ctx->patch_vertices),
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draws[0].count,
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info->instance_count,
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draws[0].start,
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draws->index_bias,
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info->start_instance);
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else
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ctx->api.pfnSwrDrawInstanced(ctx->swrContext,
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swr_convert_prim_topology(info->mode, ctx->patch_vertices),
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draws[0].count,
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info->instance_count,
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draws[0].start,
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info->start_instance);
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/* On client-buffer draw, we used client buffer directly, without
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* copy. Block until draw is finished.
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* VMD is an example application that benefits from this. */
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if (ctx->dirty & SWR_BLOCK_CLIENT_DRAW) {
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struct swr_screen *screen = swr_screen(pipe->screen);
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swr_fence_submit(ctx, screen->flush_fence);
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swr_fence_finish(pipe->screen, NULL, screen->flush_fence, 0);
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}
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}
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static void
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swr_flush(struct pipe_context *pipe,
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struct pipe_fence_handle **fence,
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unsigned flags)
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{
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struct swr_context *ctx = swr_context(pipe);
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struct swr_screen *screen = swr_screen(pipe->screen);
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for (int i=0; i < ctx->framebuffer.nr_cbufs; i++) {
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struct pipe_surface *cb = ctx->framebuffer.cbufs[i];
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if (cb) {
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swr_store_dirty_resource(pipe, cb->texture, SWR_TILE_RESOLVED);
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}
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}
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if (ctx->framebuffer.zsbuf) {
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swr_store_dirty_resource(pipe, ctx->framebuffer.zsbuf->texture,
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SWR_TILE_RESOLVED);
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}
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if (fence)
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swr_fence_reference(pipe->screen, fence, screen->flush_fence);
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}
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void
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swr_finish(struct pipe_context *pipe)
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{
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struct pipe_fence_handle *fence = nullptr;
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swr_flush(pipe, &fence, 0);
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swr_fence_finish(pipe->screen, NULL, fence, 0);
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swr_fence_reference(pipe->screen, &fence, NULL);
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}
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/*
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* Invalidate tiles so they can be reloaded back when needed
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*/
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void
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swr_invalidate_render_target(struct pipe_context *pipe,
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uint32_t attachment,
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uint16_t width, uint16_t height)
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{
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struct swr_context *ctx = swr_context(pipe);
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/* grab the rect from the passed in arguments */
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swr_update_draw_context(ctx);
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SWR_RECT full_rect =
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{0, 0, (int32_t)width, (int32_t)height};
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ctx->api.pfnSwrInvalidateTiles(ctx->swrContext,
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1 << attachment,
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full_rect);
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}
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/*
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* Store SWR HotTiles back to renderTarget surface.
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*/
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void
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swr_store_render_target(struct pipe_context *pipe,
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uint32_t attachment,
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enum SWR_TILE_STATE post_tile_state)
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{
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struct swr_context *ctx = swr_context(pipe);
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struct swr_draw_context *pDC = &ctx->swrDC;
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struct SWR_SURFACE_STATE *renderTarget = &pDC->renderTargets[attachment];
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/* Only proceed if there's a valid surface to store to */
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if (renderTarget->xpBaseAddress) {
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swr_update_draw_context(ctx);
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SWR_RECT full_rect =
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{0, 0,
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(int32_t)u_minify(renderTarget->width, renderTarget->lod),
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(int32_t)u_minify(renderTarget->height, renderTarget->lod)};
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ctx->api.pfnSwrStoreTiles(ctx->swrContext,
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1 << attachment,
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post_tile_state,
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full_rect);
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}
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}
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void
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swr_store_dirty_resource(struct pipe_context *pipe,
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struct pipe_resource *resource,
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enum SWR_TILE_STATE post_tile_state)
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{
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/* Only store resource if it has been written to */
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if (swr_resource(resource)->status & SWR_RESOURCE_WRITE) {
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struct swr_context *ctx = swr_context(pipe);
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struct swr_screen *screen = swr_screen(pipe->screen);
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struct swr_resource *spr = swr_resource(resource);
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swr_draw_context *pDC = &ctx->swrDC;
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SWR_SURFACE_STATE *renderTargets = pDC->renderTargets;
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for (uint32_t i = 0; i < SWR_NUM_ATTACHMENTS; i++)
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if (renderTargets[i].xpBaseAddress == spr->swr.xpBaseAddress ||
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(spr->secondary.xpBaseAddress &&
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renderTargets[i].xpBaseAddress == spr->secondary.xpBaseAddress)) {
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swr_store_render_target(pipe, i, post_tile_state);
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/* Mesa thinks depth/stencil are fused, so we'll never get an
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* explicit resource for stencil. So, if checking depth, then
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* also check for stencil. */
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if (spr->has_stencil && (i == SWR_ATTACHMENT_DEPTH)) {
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swr_store_render_target(
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pipe, SWR_ATTACHMENT_STENCIL, post_tile_state);
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}
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/* This fence signals StoreTiles completion */
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swr_fence_submit(ctx, screen->flush_fence);
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break;
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}
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}
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}
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void
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swr_draw_init(struct pipe_context *pipe)
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{
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pipe->draw_vbo = swr_draw_vbo;
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pipe->flush = swr_flush;
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}
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