312 lines
9.2 KiB
C
312 lines
9.2 KiB
C
/*
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* Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
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* Copyright © 2018 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#ifndef FD6_EMIT_H
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#define FD6_EMIT_H
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#include "pipe/p_context.h"
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#include "fd6_context.h"
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#include "fd6_format.h"
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#include "fd6_program.h"
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#include "freedreno_context.h"
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#include "ir3_gallium.h"
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struct fd_ringbuffer;
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/* To collect all the state objects to emit in a single CP_SET_DRAW_STATE
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* packet, the emit tracks a collection of however many state_group's that
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* need to be emit'd.
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*/
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enum fd6_state_id {
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FD6_GROUP_PROG_CONFIG,
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FD6_GROUP_PROG,
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FD6_GROUP_PROG_BINNING,
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FD6_GROUP_PROG_INTERP,
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FD6_GROUP_PROG_FB_RAST,
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FD6_GROUP_LRZ,
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FD6_GROUP_LRZ_BINNING,
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FD6_GROUP_VTXSTATE,
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FD6_GROUP_VBO,
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FD6_GROUP_CONST,
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FD6_GROUP_VS_DRIVER_PARAMS,
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FD6_GROUP_PRIMITIVE_PARAMS,
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FD6_GROUP_VS_TEX,
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FD6_GROUP_HS_TEX,
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FD6_GROUP_DS_TEX,
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FD6_GROUP_GS_TEX,
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FD6_GROUP_FS_TEX,
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FD6_GROUP_RASTERIZER,
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FD6_GROUP_ZSA,
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FD6_GROUP_BLEND,
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FD6_GROUP_SCISSOR,
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FD6_GROUP_BLEND_COLOR,
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FD6_GROUP_SO,
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FD6_GROUP_IBO,
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FD6_GROUP_NON_GROUP, /* placeholder group for state emit in IB2, keep last */
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};
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#define ENABLE_ALL \
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(CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | \
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CP_SET_DRAW_STATE__0_SYSMEM)
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#define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
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struct fd6_state_group {
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struct fd_ringbuffer *stateobj;
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enum fd6_state_id group_id;
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/* enable_mask controls which states the stateobj is evaluated in,
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* b0 is binning pass b1 and/or b2 is draw pass
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*/
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uint32_t enable_mask;
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};
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/* grouped together emit-state for prog/vertex/state emit: */
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struct fd6_emit {
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struct fd_context *ctx;
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const struct fd_vertex_state *vtx;
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const struct pipe_draw_info *info;
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unsigned drawid_offset;
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const struct pipe_draw_indirect_info *indirect;
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const struct pipe_draw_start_count_bias *draw;
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struct ir3_cache_key key;
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enum fd_dirty_3d_state dirty;
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uint32_t dirty_groups;
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uint32_t sprite_coord_enable; /* bitmask */
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bool sprite_coord_mode;
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bool rasterflat;
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bool primitive_restart;
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uint8_t patch_vertices;
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/* cached to avoid repeated lookups: */
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const struct fd6_program_state *prog;
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struct ir3_shader_variant *bs;
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struct ir3_shader_variant *vs;
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struct ir3_shader_variant *hs;
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struct ir3_shader_variant *ds;
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struct ir3_shader_variant *gs;
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struct ir3_shader_variant *fs;
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unsigned streamout_mask;
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struct fd6_state_group groups[32];
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unsigned num_groups;
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};
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static inline const struct fd6_program_state *
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fd6_emit_get_prog(struct fd6_emit *emit)
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{
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if (!emit->prog) {
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struct ir3_program_state *s = ir3_cache_lookup(
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emit->ctx->shader_cache, &emit->key, &emit->ctx->debug);
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emit->prog = fd6_program_state(s);
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}
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return emit->prog;
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}
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static inline void
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fd6_emit_take_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
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enum fd6_state_id group_id, unsigned enable_mask)
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{
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debug_assert(emit->num_groups < ARRAY_SIZE(emit->groups));
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struct fd6_state_group *g = &emit->groups[emit->num_groups++];
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g->stateobj = stateobj;
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g->group_id = group_id;
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g->enable_mask = enable_mask;
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}
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static inline void
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fd6_emit_add_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
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enum fd6_state_id group_id, unsigned enable_mask)
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{
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fd6_emit_take_group(emit, fd_ringbuffer_ref(stateobj), group_id,
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enable_mask);
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}
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static inline unsigned
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fd6_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
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enum vgt_event_type evt, bool timestamp)
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{
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unsigned seqno = 0;
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fd_reset_wfi(batch);
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OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1);
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OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt));
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if (timestamp) {
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struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
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seqno = ++fd6_ctx->seqno;
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OUT_RELOC(ring, control_ptr(fd6_ctx, seqno)); /* ADDR_LO/HI */
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OUT_RING(ring, seqno);
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}
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return seqno;
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}
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static inline void
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fd6_cache_inv(struct fd_batch *batch, struct fd_ringbuffer *ring)
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{
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fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
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fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
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fd6_event_write(batch, ring, CACHE_INVALIDATE, false);
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}
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static inline void
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fd6_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
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{
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struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
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unsigned seqno;
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seqno = fd6_event_write(batch, ring, RB_DONE_TS, true);
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OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
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OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
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CP_WAIT_REG_MEM_0_POLL_MEMORY);
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OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
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OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
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OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
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OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
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seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
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OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
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OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
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OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
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OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
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}
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static inline void
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fd6_emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring)
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{
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emit_marker6(ring, 7);
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fd6_event_write(batch, ring, BLIT, false);
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emit_marker6(ring, 7);
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}
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static inline void
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fd6_emit_lrz_flush(struct fd_ringbuffer *ring)
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{
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, LRZ_FLUSH);
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}
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static inline bool
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fd6_geom_stage(gl_shader_stage type)
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{
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switch (type) {
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_TESS_CTRL:
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case MESA_SHADER_TESS_EVAL:
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case MESA_SHADER_GEOMETRY:
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return true;
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case MESA_SHADER_FRAGMENT:
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case MESA_SHADER_COMPUTE:
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case MESA_SHADER_KERNEL:
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return false;
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default:
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unreachable("bad shader type");
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}
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}
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static inline uint32_t
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fd6_stage2opcode(gl_shader_stage type)
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{
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return fd6_geom_stage(type) ? CP_LOAD_STATE6_GEOM : CP_LOAD_STATE6_FRAG;
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}
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static inline enum a6xx_state_block
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fd6_stage2shadersb(gl_shader_stage type)
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{
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switch (type) {
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case MESA_SHADER_VERTEX:
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return SB6_VS_SHADER;
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case MESA_SHADER_TESS_CTRL:
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return SB6_HS_SHADER;
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case MESA_SHADER_TESS_EVAL:
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return SB6_DS_SHADER;
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case MESA_SHADER_GEOMETRY:
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return SB6_GS_SHADER;
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case MESA_SHADER_FRAGMENT:
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return SB6_FS_SHADER;
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case MESA_SHADER_COMPUTE:
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case MESA_SHADER_KERNEL:
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return SB6_CS_SHADER;
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default:
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unreachable("bad shader type");
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return ~0;
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}
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}
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static inline enum a6xx_tess_spacing
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fd6_gl2spacing(enum gl_tess_spacing spacing)
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{
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switch (spacing) {
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case TESS_SPACING_EQUAL:
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return TESS_EQUAL;
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case TESS_SPACING_FRACTIONAL_ODD:
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return TESS_FRACTIONAL_ODD;
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case TESS_SPACING_FRACTIONAL_EVEN:
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return TESS_FRACTIONAL_EVEN;
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case TESS_SPACING_UNSPECIFIED:
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default:
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unreachable("spacing must be specified");
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}
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}
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bool fd6_emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
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enum pipe_shader_type type,
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struct fd_texture_stateobj *tex, unsigned bcolor_offset,
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const struct ir3_shader_variant *v) assert_dt;
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void fd6_emit_state(struct fd_ringbuffer *ring,
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struct fd6_emit *emit) assert_dt;
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void fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
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struct ir3_shader_variant *cp) assert_dt;
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void fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
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void fd6_emit_init_screen(struct pipe_screen *pscreen);
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void fd6_emit_init(struct pipe_context *pctx);
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static inline void
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fd6_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
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{
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emit_marker6(ring, 6);
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__OUT_IB5(ring, target);
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emit_marker6(ring, 6);
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}
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#define WRITE(reg, val) \
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do { \
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OUT_PKT4(ring, reg, 1); \
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OUT_RING(ring, val); \
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} while (0)
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#endif /* FD6_EMIT_H */
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