766 lines
26 KiB
C++
766 lines
26 KiB
C++
/*
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Copyright (C) Intel Corp. 2006. All Rights Reserved.
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Intel funded Tungsten Graphics to
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develop this 3D driver.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**********************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keithw@vmware.com>
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*/
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#include <sys/stat.h>
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#include <fcntl.h>
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#include "brw_eu_defines.h"
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#include "brw_eu.h"
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#include "brw_shader.h"
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#include "brw_gfx_ver_enum.h"
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#include "dev/intel_debug.h"
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#include "util/ralloc.h"
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/* Returns a conditional modifier that negates the condition. */
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enum brw_conditional_mod
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brw_negate_cmod(enum brw_conditional_mod cmod)
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{
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switch (cmod) {
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case BRW_CONDITIONAL_Z:
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return BRW_CONDITIONAL_NZ;
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case BRW_CONDITIONAL_NZ:
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return BRW_CONDITIONAL_Z;
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case BRW_CONDITIONAL_G:
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return BRW_CONDITIONAL_LE;
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case BRW_CONDITIONAL_GE:
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return BRW_CONDITIONAL_L;
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case BRW_CONDITIONAL_L:
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return BRW_CONDITIONAL_GE;
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case BRW_CONDITIONAL_LE:
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return BRW_CONDITIONAL_G;
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default:
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unreachable("Can't negate this cmod");
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}
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}
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/* Returns the corresponding conditional mod for swapping src0 and
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* src1 in e.g. CMP.
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*/
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enum brw_conditional_mod
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brw_swap_cmod(enum brw_conditional_mod cmod)
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{
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switch (cmod) {
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case BRW_CONDITIONAL_Z:
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case BRW_CONDITIONAL_NZ:
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return cmod;
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case BRW_CONDITIONAL_G:
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return BRW_CONDITIONAL_L;
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case BRW_CONDITIONAL_GE:
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return BRW_CONDITIONAL_LE;
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case BRW_CONDITIONAL_L:
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return BRW_CONDITIONAL_G;
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case BRW_CONDITIONAL_LE:
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return BRW_CONDITIONAL_GE;
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default:
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return BRW_CONDITIONAL_NONE;
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}
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}
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/**
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* Get the least significant bit offset of the i+1-th component of immediate
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* type \p type. For \p i equal to the two's complement of j, return the
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* offset of the j-th component starting from the end of the vector. For
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* scalar register types return zero.
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*/
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static unsigned
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imm_shift(enum brw_reg_type type, unsigned i)
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{
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assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
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"Not implemented.");
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if (type == BRW_REGISTER_TYPE_VF)
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return 8 * (i & 3);
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else
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return 0;
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}
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/**
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* Swizzle an arbitrary immediate \p x of the given type according to the
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* permutation specified as \p swz.
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*/
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uint32_t
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brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
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{
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if (imm_shift(type, 1)) {
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const unsigned n = 32 / imm_shift(type, 1);
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uint32_t y = 0;
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for (unsigned i = 0; i < n; i++) {
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/* Shift the specified component all the way to the right and left to
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* discard any undesired L/MSBs, then shift it right into component i.
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*/
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y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3))
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<< imm_shift(type, ~0u)
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>> imm_shift(type, ~0u - i);
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}
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return y;
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} else {
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return x;
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}
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}
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unsigned
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brw_get_default_exec_size(struct brw_codegen *p)
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{
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return p->current->exec_size;
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}
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unsigned
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brw_get_default_group(struct brw_codegen *p)
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{
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return p->current->group;
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}
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unsigned
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brw_get_default_access_mode(struct brw_codegen *p)
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{
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return p->current->access_mode;
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}
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tgl_swsb
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brw_get_default_swsb(struct brw_codegen *p)
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{
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return p->current->swsb;
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}
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void
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brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
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{
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p->current->exec_size = value;
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}
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void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc)
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{
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p->current->predicate = pc;
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}
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void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
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{
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p->current->pred_inv = predicate_inverse;
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}
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void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
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{
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assert(subreg < 2);
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p->current->flag_subreg = reg * 2 + subreg;
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}
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void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
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{
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p->current->access_mode = access_mode;
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}
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void
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brw_set_default_compression_control(struct brw_codegen *p,
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enum brw_compression compression_control)
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{
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switch (compression_control) {
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case BRW_COMPRESSION_NONE:
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/* This is the "use the first set of bits of dmask/vmask/arf
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* according to execsize" option.
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*/
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p->current->group = 0;
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break;
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case BRW_COMPRESSION_2NDHALF:
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/* For SIMD8, this is "use the second set of 8 bits." */
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p->current->group = 8;
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break;
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case BRW_COMPRESSION_COMPRESSED:
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/* For SIMD16 instruction compression, use the first set of 16 bits
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* since we don't do SIMD32 dispatch.
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*/
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p->current->group = 0;
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break;
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default:
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unreachable("not reached");
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}
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if (p->devinfo->ver <= 6) {
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p->current->compressed =
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(compression_control == BRW_COMPRESSION_COMPRESSED);
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}
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}
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/**
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* Enable or disable instruction compression on the given instruction leaving
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* the currently selected channel enable group untouched.
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*/
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void
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brw_inst_set_compression(const struct intel_device_info *devinfo,
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brw_inst *inst, bool on)
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{
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if (devinfo->ver >= 6) {
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/* No-op, the EU will figure out for us whether the instruction needs to
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* be compressed.
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*/
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} else {
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/* The channel group and compression controls are non-orthogonal, there
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* are two possible representations for uncompressed instructions and we
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* may need to preserve the current one to avoid changing the selected
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* channel group inadvertently.
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*/
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if (on)
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brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED);
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else if (brw_inst_qtr_control(devinfo, inst)
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== BRW_COMPRESSION_COMPRESSED)
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brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
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}
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}
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void
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brw_set_default_compression(struct brw_codegen *p, bool on)
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{
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p->current->compressed = on;
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}
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/**
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* Apply the range of channel enable signals given by
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* [group, group + exec_size) to the instruction passed as argument.
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*/
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void
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brw_inst_set_group(const struct intel_device_info *devinfo,
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brw_inst *inst, unsigned group)
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{
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if (devinfo->ver >= 7) {
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assert(group % 4 == 0 && group < 32);
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brw_inst_set_qtr_control(devinfo, inst, group / 8);
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brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
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} else if (devinfo->ver == 6) {
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assert(group % 8 == 0 && group < 32);
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brw_inst_set_qtr_control(devinfo, inst, group / 8);
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} else {
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assert(group % 8 == 0 && group < 16);
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/* The channel group and compression controls are non-orthogonal, there
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* are two possible representations for group zero and we may need to
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* preserve the current one to avoid changing the selected compression
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* enable inadvertently.
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*/
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if (group == 8)
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brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF);
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else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF)
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brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
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}
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}
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void
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brw_set_default_group(struct brw_codegen *p, unsigned group)
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{
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p->current->group = group;
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}
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void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
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{
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p->current->mask_control = value;
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}
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void brw_set_default_saturate( struct brw_codegen *p, bool enable )
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{
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p->current->saturate = enable;
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}
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void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
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{
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p->current->acc_wr_control = value;
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}
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void brw_set_default_swsb(struct brw_codegen *p, tgl_swsb value)
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{
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p->current->swsb = value;
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}
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void brw_push_insn_state( struct brw_codegen *p )
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{
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assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
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*(p->current + 1) = *p->current;
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p->current++;
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}
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void brw_pop_insn_state( struct brw_codegen *p )
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{
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assert(p->current != p->stack);
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p->current--;
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}
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/***********************************************************************
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*/
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void
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brw_init_codegen(const struct intel_device_info *devinfo,
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struct brw_codegen *p, void *mem_ctx)
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{
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memset(p, 0, sizeof(*p));
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p->devinfo = devinfo;
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p->automatic_exec_sizes = true;
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/*
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* Set the initial instruction store array size to 1024, if found that
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* isn't enough, then it will double the store size at brw_next_insn()
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* until out of memory.
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*/
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p->store_size = 1024;
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p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
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p->nr_insn = 0;
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p->current = p->stack;
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memset(p->current, 0, sizeof(p->current[0]));
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p->mem_ctx = mem_ctx;
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/* Some defaults?
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*/
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brw_set_default_exec_size(p, BRW_EXECUTE_8);
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brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
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brw_set_default_saturate(p, 0);
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brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
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/* Set up control flow stack */
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p->if_stack_depth = 0;
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p->if_stack_array_size = 16;
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p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
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p->loop_stack_depth = 0;
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p->loop_stack_array_size = 16;
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p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
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p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
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}
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const unsigned *brw_get_program( struct brw_codegen *p,
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unsigned *sz )
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{
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*sz = p->next_insn_offset;
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return (const unsigned *)p->store;
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}
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const brw_shader_reloc *
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brw_get_shader_relocs(struct brw_codegen *p, unsigned *num_relocs)
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{
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*num_relocs = p->num_relocs;
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return p->relocs;
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}
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bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
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const char *identifier)
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{
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const char *read_path = getenv("INTEL_SHADER_ASM_READ_PATH");
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if (!read_path) {
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return false;
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}
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char *name = ralloc_asprintf(NULL, "%s/%s.bin", read_path, identifier);
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int fd = open(name, O_RDONLY);
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ralloc_free(name);
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if (fd == -1) {
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return false;
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}
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struct stat sb;
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if (fstat(fd, &sb) != 0 || (!S_ISREG(sb.st_mode))) {
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close(fd);
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return false;
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}
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p->nr_insn -= (p->next_insn_offset - start_offset) / sizeof(brw_inst);
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p->nr_insn += sb.st_size / sizeof(brw_inst);
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p->next_insn_offset = start_offset + sb.st_size;
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p->store_size = (start_offset + sb.st_size) / sizeof(brw_inst);
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p->store = (brw_inst *)reralloc_size(p->mem_ctx, p->store, p->next_insn_offset);
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assert(p->store);
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ssize_t ret = read(fd, (char *)p->store + start_offset, sb.st_size);
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close(fd);
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if (ret != sb.st_size) {
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return false;
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}
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ASSERTED bool valid =
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brw_validate_instructions(p->devinfo, p->store,
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start_offset, p->next_insn_offset,
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NULL);
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assert(valid);
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return true;
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}
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const struct brw_label *
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brw_find_label(const struct brw_label *root, int offset)
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{
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const struct brw_label *curr = root;
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if (curr != NULL)
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{
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do {
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if (curr->offset == offset)
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return curr;
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curr = curr->next;
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} while (curr != NULL);
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}
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return curr;
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}
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void
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brw_create_label(struct brw_label **labels, int offset, void *mem_ctx)
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{
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if (*labels != NULL) {
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struct brw_label *curr = *labels;
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struct brw_label *prev;
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do {
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prev = curr;
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if (curr->offset == offset)
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return;
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curr = curr->next;
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} while (curr != NULL);
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curr = ralloc(mem_ctx, struct brw_label);
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curr->offset = offset;
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curr->number = prev->number + 1;
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curr->next = NULL;
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prev->next = curr;
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} else {
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struct brw_label *root = ralloc(mem_ctx, struct brw_label);
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root->number = 0;
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root->offset = offset;
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root->next = NULL;
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*labels = root;
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}
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}
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const struct brw_label *
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brw_label_assembly(const struct intel_device_info *devinfo,
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const void *assembly, int start, int end, void *mem_ctx)
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{
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struct brw_label *root_label = NULL;
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int to_bytes_scale = sizeof(brw_inst) / brw_jump_scale(devinfo);
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for (int offset = start; offset < end;) {
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const brw_inst *inst = (const brw_inst *) ((const char *) assembly + offset);
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brw_inst uncompacted;
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bool is_compact = brw_inst_cmpt_control(devinfo, inst);
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if (is_compact) {
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brw_compact_inst *compacted = (brw_compact_inst *)inst;
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brw_uncompact_instruction(devinfo, &uncompacted, compacted);
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inst = &uncompacted;
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}
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if (brw_has_uip(devinfo, brw_inst_opcode(devinfo, inst))) {
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/* Instructions that have UIP also have JIP. */
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brw_create_label(&root_label,
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offset + brw_inst_uip(devinfo, inst) * to_bytes_scale, mem_ctx);
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brw_create_label(&root_label,
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offset + brw_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx);
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} else if (brw_has_jip(devinfo, brw_inst_opcode(devinfo, inst))) {
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int jip;
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if (devinfo->ver >= 7) {
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jip = brw_inst_jip(devinfo, inst);
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} else {
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jip = brw_inst_gfx6_jump_count(devinfo, inst);
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}
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brw_create_label(&root_label, offset + jip * to_bytes_scale, mem_ctx);
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}
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if (is_compact) {
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offset += sizeof(brw_compact_inst);
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} else {
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offset += sizeof(brw_inst);
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}
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}
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return root_label;
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}
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void
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brw_disassemble_with_labels(const struct intel_device_info *devinfo,
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const void *assembly, int start, int end, FILE *out)
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{
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|
void *mem_ctx = ralloc_context(NULL);
|
|
const struct brw_label *root_label =
|
|
brw_label_assembly(devinfo, assembly, start, end, mem_ctx);
|
|
|
|
brw_disassemble(devinfo, assembly, start, end, root_label, out);
|
|
|
|
ralloc_free(mem_ctx);
|
|
}
|
|
|
|
void
|
|
brw_disassemble(const struct intel_device_info *devinfo,
|
|
const void *assembly, int start, int end,
|
|
const struct brw_label *root_label, FILE *out)
|
|
{
|
|
bool dump_hex = INTEL_DEBUG(DEBUG_HEX);
|
|
|
|
for (int offset = start; offset < end;) {
|
|
const brw_inst *insn = (const brw_inst *)((char *)assembly + offset);
|
|
brw_inst uncompacted;
|
|
|
|
if (root_label != NULL) {
|
|
const struct brw_label *label = brw_find_label(root_label, offset);
|
|
if (label != NULL) {
|
|
fprintf(out, "\nLABEL%d:\n", label->number);
|
|
}
|
|
}
|
|
|
|
bool compacted = brw_inst_cmpt_control(devinfo, insn);
|
|
if (0)
|
|
fprintf(out, "0x%08x: ", offset);
|
|
|
|
if (compacted) {
|
|
brw_compact_inst *compacted = (brw_compact_inst *)insn;
|
|
if (dump_hex) {
|
|
unsigned char * insn_ptr = ((unsigned char *)&insn[0]);
|
|
const unsigned int blank_spaces = 24;
|
|
for (int i = 0 ; i < 8; i = i + 4) {
|
|
fprintf(out, "%02x %02x %02x %02x ",
|
|
insn_ptr[i],
|
|
insn_ptr[i + 1],
|
|
insn_ptr[i + 2],
|
|
insn_ptr[i + 3]);
|
|
}
|
|
/* Make compacted instructions hex value output vertically aligned
|
|
* with uncompacted instructions hex value
|
|
*/
|
|
fprintf(out, "%*c", blank_spaces, ' ');
|
|
}
|
|
|
|
brw_uncompact_instruction(devinfo, &uncompacted, compacted);
|
|
insn = &uncompacted;
|
|
} else {
|
|
if (dump_hex) {
|
|
unsigned char * insn_ptr = ((unsigned char *)&insn[0]);
|
|
for (int i = 0 ; i < 16; i = i + 4) {
|
|
fprintf(out, "%02x %02x %02x %02x ",
|
|
insn_ptr[i],
|
|
insn_ptr[i + 1],
|
|
insn_ptr[i + 2],
|
|
insn_ptr[i + 3]);
|
|
}
|
|
}
|
|
}
|
|
|
|
brw_disassemble_inst(out, devinfo, insn, compacted, offset, root_label);
|
|
|
|
if (compacted) {
|
|
offset += sizeof(brw_compact_inst);
|
|
} else {
|
|
offset += sizeof(brw_inst);
|
|
}
|
|
}
|
|
}
|
|
|
|
static const struct opcode_desc opcode_descs[] = {
|
|
/* IR, HW, name, nsrc, ndst, gfx_vers */
|
|
{ BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_SYNC, 1, "sync", 1, 0, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_MOV, 1, "mov", 1, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_MOV, 97, "mov", 1, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_SEL, 2, "sel", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_SEL, 98, "sel", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_MOVI, 3, "movi", 2, 1, GFX_GE(GFX45) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_MOVI, 99, "movi", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_NOT, 4, "not", 1, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_NOT, 100, "not", 1, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_AND, 5, "and", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_AND, 101, "and", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_OR, 6, "or", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_OR, 102, "or", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_XOR, 7, "xor", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_XOR, 103, "xor", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_SHR, 8, "shr", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_SHR, 104, "shr", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_SHL, 9, "shl", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_SHL, 105, "shl", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_DIM, 10, "dim", 1, 1, GFX75 },
|
|
{ BRW_OPCODE_SMOV, 10, "smov", 0, 0, GFX_GE(GFX8) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_SMOV, 106, "smov", 0, 0, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_ASR, 12, "asr", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_ASR, 108, "asr", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_ROR, 14, "ror", 2, 1, GFX11 },
|
|
{ BRW_OPCODE_ROR, 110, "ror", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_ROL, 15, "rol", 2, 1, GFX11 },
|
|
{ BRW_OPCODE_ROL, 111, "rol", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_CMP, 16, "cmp", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_CMP, 112, "cmp", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_CMPN, 17, "cmpn", 2, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_CMPN, 113, "cmpn", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_CSEL, 18, "csel", 3, 1, GFX_GE(GFX8) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_CSEL, 114, "csel", 3, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 },
|
|
{ BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 },
|
|
{ BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_BFREV, 119, "bfrev", 1, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_BFE, 120, "bfe", 3, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_BFI1, 121, "bfi1", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_BFI2, 122, "bfi2", 3, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_JMPI, 32, "jmpi", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_BRD, 33, "brd", 0, 0, GFX_GE(GFX7) },
|
|
{ BRW_OPCODE_IF, 34, "if", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_IFF, 35, "iff", 0, 0, GFX_LE(GFX5) },
|
|
{ BRW_OPCODE_BRC, 35, "brc", 0, 0, GFX_GE(GFX7) },
|
|
{ BRW_OPCODE_ELSE, 36, "else", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_ENDIF, 37, "endif", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_DO, 38, "do", 0, 0, GFX_LE(GFX5) },
|
|
{ BRW_OPCODE_CASE, 38, "case", 0, 0, GFX6 },
|
|
{ BRW_OPCODE_WHILE, 39, "while", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_BREAK, 40, "break", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_CONTINUE, 41, "cont", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_HALT, 42, "halt", 0, 0, GFX_ALL },
|
|
{ BRW_OPCODE_CALLA, 43, "calla", 0, 0, GFX_GE(GFX75) },
|
|
{ BRW_OPCODE_MSAVE, 44, "msave", 0, 0, GFX_LE(GFX5) },
|
|
{ BRW_OPCODE_CALL, 44, "call", 0, 0, GFX_GE(GFX6) },
|
|
{ BRW_OPCODE_MREST, 45, "mrest", 0, 0, GFX_LE(GFX5) },
|
|
{ BRW_OPCODE_RET, 45, "ret", 0, 0, GFX_GE(GFX6) },
|
|
{ BRW_OPCODE_PUSH, 46, "push", 0, 0, GFX_LE(GFX5) },
|
|
{ BRW_OPCODE_FORK, 46, "fork", 0, 0, GFX6 },
|
|
{ BRW_OPCODE_GOTO, 46, "goto", 0, 0, GFX_GE(GFX8) },
|
|
{ BRW_OPCODE_POP, 47, "pop", 2, 0, GFX_LE(GFX5) },
|
|
{ BRW_OPCODE_WAIT, 48, "wait", 0, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_SEND, 49, "send", 1, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_SENDC, 50, "sendc", 1, 1, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_SEND, 49, "send", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_SENDC, 50, "sendc", 2, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_SENDS, 51, "sends", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_SENDSC, 52, "sendsc", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_MATH, 56, "math", 2, 1, GFX_GE(GFX6) },
|
|
{ BRW_OPCODE_ADD, 64, "add", 2, 1, GFX_ALL },
|
|
{ BRW_OPCODE_MUL, 65, "mul", 2, 1, GFX_ALL },
|
|
{ BRW_OPCODE_AVG, 66, "avg", 2, 1, GFX_ALL },
|
|
{ BRW_OPCODE_FRC, 67, "frc", 1, 1, GFX_ALL },
|
|
{ BRW_OPCODE_RNDU, 68, "rndu", 1, 1, GFX_ALL },
|
|
{ BRW_OPCODE_RNDD, 69, "rndd", 1, 1, GFX_ALL },
|
|
{ BRW_OPCODE_RNDE, 70, "rnde", 1, 1, GFX_ALL },
|
|
{ BRW_OPCODE_RNDZ, 71, "rndz", 1, 1, GFX_ALL },
|
|
{ BRW_OPCODE_MAC, 72, "mac", 2, 1, GFX_ALL },
|
|
{ BRW_OPCODE_MACH, 73, "mach", 2, 1, GFX_ALL },
|
|
{ BRW_OPCODE_LZD, 74, "lzd", 1, 1, GFX_ALL },
|
|
{ BRW_OPCODE_FBH, 75, "fbh", 1, 1, GFX_GE(GFX7) },
|
|
{ BRW_OPCODE_FBL, 76, "fbl", 1, 1, GFX_GE(GFX7) },
|
|
{ BRW_OPCODE_CBIT, 77, "cbit", 1, 1, GFX_GE(GFX7) },
|
|
{ BRW_OPCODE_ADDC, 78, "addc", 2, 1, GFX_GE(GFX7) },
|
|
{ BRW_OPCODE_SUBB, 79, "subb", 2, 1, GFX_GE(GFX7) },
|
|
{ BRW_OPCODE_SAD2, 80, "sad2", 2, 1, GFX_ALL },
|
|
{ BRW_OPCODE_SADA2, 81, "sada2", 2, 1, GFX_ALL },
|
|
{ BRW_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) },
|
|
{ BRW_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) },
|
|
{ BRW_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) },
|
|
{ BRW_OPCODE_DP3, 86, "dp3", 2, 1, GFX_LT(GFX11) },
|
|
{ BRW_OPCODE_DP2, 87, "dp2", 2, 1, GFX_LT(GFX11) },
|
|
{ BRW_OPCODE_DP4A, 88, "dp4a", 3, 1, GFX_GE(GFX12) },
|
|
{ BRW_OPCODE_LINE, 89, "line", 2, 1, GFX_LE(GFX10) },
|
|
{ BRW_OPCODE_PLN, 90, "pln", 2, 1, GFX_GE(GFX45) & GFX_LE(GFX10) },
|
|
{ BRW_OPCODE_MAD, 91, "mad", 3, 1, GFX_GE(GFX6) },
|
|
{ BRW_OPCODE_LRP, 92, "lrp", 3, 1, GFX_GE(GFX6) & GFX_LE(GFX10) },
|
|
{ BRW_OPCODE_MADM, 93, "madm", 3, 1, GFX_GE(GFX8) },
|
|
{ BRW_OPCODE_NENOP, 125, "nenop", 0, 0, GFX45 },
|
|
{ BRW_OPCODE_NOP, 126, "nop", 0, 0, GFX_LT(GFX12) },
|
|
{ BRW_OPCODE_NOP, 96, "nop", 0, 0, GFX_GE(GFX12) }
|
|
};
|
|
|
|
/**
|
|
* Look up the opcode_descs[] entry with \p key member matching \p k which is
|
|
* supported by the device specified by \p devinfo, or NULL if there is no
|
|
* matching entry.
|
|
*
|
|
* This is implemented by using an index data structure (storage for which is
|
|
* provided by the caller as \p index_ver and \p index_descs) in order to
|
|
* provide efficient constant-time look-up.
|
|
*/
|
|
static const opcode_desc *
|
|
lookup_opcode_desc(gfx_ver *index_ver,
|
|
const opcode_desc **index_descs,
|
|
unsigned index_size,
|
|
unsigned opcode_desc::*key,
|
|
const intel_device_info *devinfo,
|
|
unsigned k)
|
|
{
|
|
if (*index_ver != gfx_ver_from_devinfo(devinfo)) {
|
|
*index_ver = gfx_ver_from_devinfo(devinfo);
|
|
|
|
for (unsigned l = 0; l < index_size; l++)
|
|
index_descs[l] = NULL;
|
|
|
|
for (unsigned i = 0; i < ARRAY_SIZE(opcode_descs); i++) {
|
|
if (opcode_descs[i].gfx_vers & *index_ver) {
|
|
const unsigned l = opcode_descs[i].*key;
|
|
assert(l < index_size && !index_descs[l]);
|
|
index_descs[l] = &opcode_descs[i];
|
|
}
|
|
}
|
|
}
|
|
|
|
if (k < index_size)
|
|
return index_descs[k];
|
|
else
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* Return the matching opcode_desc for the specified IR opcode and hardware
|
|
* generation, or NULL if the opcode is not supported by the device.
|
|
*/
|
|
const struct opcode_desc *
|
|
brw_opcode_desc(const struct intel_device_info *devinfo, enum opcode opcode)
|
|
{
|
|
static thread_local gfx_ver index_ver = {};
|
|
static thread_local const opcode_desc *index_descs[NUM_BRW_OPCODES];
|
|
return lookup_opcode_desc(&index_ver, index_descs, ARRAY_SIZE(index_descs),
|
|
&opcode_desc::ir, devinfo, opcode);
|
|
}
|
|
|
|
/**
|
|
* Return the matching opcode_desc for the specified HW opcode and hardware
|
|
* generation, or NULL if the opcode is not supported by the device.
|
|
*/
|
|
const struct opcode_desc *
|
|
brw_opcode_desc_from_hw(const struct intel_device_info *devinfo, unsigned hw)
|
|
{
|
|
static thread_local gfx_ver index_ver = {};
|
|
static thread_local const opcode_desc *index_descs[128];
|
|
return lookup_opcode_desc(&index_ver, index_descs, ARRAY_SIZE(index_descs),
|
|
&opcode_desc::hw, devinfo, hw);
|
|
}
|