1126 lines
39 KiB
C++
1126 lines
39 KiB
C++
/*
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* Copyright © 2018 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "aco_builder.h"
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#include "aco_ir.h"
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#include "common/amdgfxregs.h"
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#include <algorithm>
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#include <unordered_set>
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#include <vector>
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#define SMEM_WINDOW_SIZE (350 - ctx.num_waves * 35)
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#define VMEM_WINDOW_SIZE (1024 - ctx.num_waves * 64)
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#define POS_EXP_WINDOW_SIZE 512
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#define SMEM_MAX_MOVES (64 - ctx.num_waves * 4)
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#define VMEM_MAX_MOVES (256 - ctx.num_waves * 16)
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/* creating clauses decreases def-use distances, so make it less aggressive the lower num_waves is */
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#define VMEM_CLAUSE_MAX_GRAB_DIST (ctx.num_waves * 2)
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#define POS_EXP_MAX_MOVES 512
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namespace aco {
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enum MoveResult {
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move_success,
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move_fail_ssa,
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move_fail_rar,
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move_fail_pressure,
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};
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/**
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* Cursor for downwards moves, where a single instruction is moved towards
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* or below a group of instruction that hardware can execute as a clause.
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*/
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struct DownwardsCursor {
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int source_idx; /* Current instruction to consider for moving */
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int insert_idx_clause; /* First clause instruction */
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int insert_idx; /* First instruction *after* the clause */
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/* Maximum demand of all clause instructions,
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* i.e. from insert_idx_clause (inclusive) to insert_idx (exclusive) */
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RegisterDemand clause_demand;
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/* Maximum demand of instructions from source_idx to insert_idx_clause (both exclusive) */
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RegisterDemand total_demand;
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DownwardsCursor(int current_idx, RegisterDemand initial_clause_demand)
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: source_idx(current_idx - 1), insert_idx_clause(current_idx), insert_idx(current_idx + 1),
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clause_demand(initial_clause_demand)
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{}
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void verify_invariants(const RegisterDemand* register_demand);
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};
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/**
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* Cursor for upwards moves, where a single instruction is moved below
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* another instruction.
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*/
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struct UpwardsCursor {
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int source_idx; /* Current instruction to consider for moving */
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int insert_idx; /* Instruction to move in front of */
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/* Maximum demand of instructions from insert_idx (inclusive) to source_idx (exclusive) */
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RegisterDemand total_demand;
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UpwardsCursor(int source_idx_) : source_idx(source_idx_)
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{
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insert_idx = -1; /* to be initialized later */
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}
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bool has_insert_idx() const { return insert_idx != -1; }
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void verify_invariants(const RegisterDemand* register_demand);
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};
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struct MoveState {
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RegisterDemand max_registers;
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Block* block;
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Instruction* current;
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RegisterDemand* register_demand; /* demand per instruction */
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bool improved_rar;
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std::vector<bool> depends_on;
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/* Two are needed because, for downwards VMEM scheduling, one needs to
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* exclude the instructions in the clause, since new instructions in the
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* clause are not moved past any other instructions in the clause. */
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std::vector<bool> RAR_dependencies;
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std::vector<bool> RAR_dependencies_clause;
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/* for moving instructions before the current instruction to after it */
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DownwardsCursor downwards_init(int current_idx, bool improved_rar, bool may_form_clauses);
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MoveResult downwards_move(DownwardsCursor&, bool clause);
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void downwards_skip(DownwardsCursor&);
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/* for moving instructions after the first use of the current instruction upwards */
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UpwardsCursor upwards_init(int source_idx, bool improved_rar);
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bool upwards_check_deps(UpwardsCursor&);
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void upwards_update_insert_idx(UpwardsCursor&);
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MoveResult upwards_move(UpwardsCursor&);
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void upwards_skip(UpwardsCursor&);
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};
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struct sched_ctx {
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int16_t num_waves;
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int16_t last_SMEM_stall;
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int last_SMEM_dep_idx;
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MoveState mv;
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bool schedule_pos_exports = true;
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unsigned schedule_pos_export_div = 1;
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};
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/* This scheduler is a simple bottom-up pass based on ideas from
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* "A Novel Lightweight Instruction Scheduling Algorithm for Just-In-Time Compiler"
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* from Xiaohua Shi and Peng Guo.
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* The basic approach is to iterate over all instructions. When a memory instruction
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* is encountered it tries to move independent instructions from above and below
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* between the memory instruction and it's first user.
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* The novelty is that this scheduler cares for the current register pressure:
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* Instructions will only be moved if the register pressure won't exceed a certain bound.
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*/
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template <typename T>
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void
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move_element(T begin_it, size_t idx, size_t before)
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{
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if (idx < before) {
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auto begin = std::next(begin_it, idx);
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auto end = std::next(begin_it, before);
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std::rotate(begin, begin + 1, end);
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} else if (idx > before) {
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auto begin = std::next(begin_it, before);
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auto end = std::next(begin_it, idx + 1);
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std::rotate(begin, end - 1, end);
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}
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}
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void
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DownwardsCursor::verify_invariants(const RegisterDemand* register_demand)
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{
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assert(source_idx < insert_idx_clause);
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assert(insert_idx_clause < insert_idx);
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#ifndef NDEBUG
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RegisterDemand reference_demand;
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for (int i = source_idx + 1; i < insert_idx_clause; ++i) {
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reference_demand.update(register_demand[i]);
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}
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assert(total_demand == reference_demand);
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reference_demand = {};
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for (int i = insert_idx_clause; i < insert_idx; ++i) {
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reference_demand.update(register_demand[i]);
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}
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assert(clause_demand == reference_demand);
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#endif
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}
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DownwardsCursor
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MoveState::downwards_init(int current_idx, bool improved_rar_, bool may_form_clauses)
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{
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improved_rar = improved_rar_;
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std::fill(depends_on.begin(), depends_on.end(), false);
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if (improved_rar) {
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std::fill(RAR_dependencies.begin(), RAR_dependencies.end(), false);
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if (may_form_clauses)
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std::fill(RAR_dependencies_clause.begin(), RAR_dependencies_clause.end(), false);
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}
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for (const Operand& op : current->operands) {
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if (op.isTemp()) {
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depends_on[op.tempId()] = true;
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if (improved_rar && op.isFirstKill())
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RAR_dependencies[op.tempId()] = true;
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}
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}
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DownwardsCursor cursor(current_idx, register_demand[current_idx]);
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cursor.verify_invariants(register_demand);
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return cursor;
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}
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/* If add_to_clause is true, the current clause is extended by moving the
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* instruction at source_idx in front of the clause. Otherwise, the instruction
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* is moved past the end of the clause without extending it */
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MoveResult
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MoveState::downwards_move(DownwardsCursor& cursor, bool add_to_clause)
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{
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aco_ptr<Instruction>& instr = block->instructions[cursor.source_idx];
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for (const Definition& def : instr->definitions)
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if (def.isTemp() && depends_on[def.tempId()])
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return move_fail_ssa;
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/* check if one of candidate's operands is killed by depending instruction */
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std::vector<bool>& RAR_deps =
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improved_rar ? (add_to_clause ? RAR_dependencies_clause : RAR_dependencies) : depends_on;
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for (const Operand& op : instr->operands) {
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if (op.isTemp() && RAR_deps[op.tempId()]) {
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// FIXME: account for difference in register pressure
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return move_fail_rar;
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}
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}
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if (add_to_clause) {
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for (const Operand& op : instr->operands) {
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if (op.isTemp()) {
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depends_on[op.tempId()] = true;
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if (op.isFirstKill())
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RAR_dependencies[op.tempId()] = true;
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}
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}
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}
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const int dest_insert_idx = add_to_clause ? cursor.insert_idx_clause : cursor.insert_idx;
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RegisterDemand register_pressure = cursor.total_demand;
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if (!add_to_clause) {
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register_pressure.update(cursor.clause_demand);
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}
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/* Check the new demand of the instructions being moved over */
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const RegisterDemand candidate_diff = get_live_changes(instr);
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if (RegisterDemand(register_pressure - candidate_diff).exceeds(max_registers))
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return move_fail_pressure;
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/* New demand for the moved instruction */
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const RegisterDemand temp = get_temp_registers(instr);
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const RegisterDemand temp2 = get_temp_registers(block->instructions[dest_insert_idx - 1]);
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const RegisterDemand new_demand = register_demand[dest_insert_idx - 1] - temp2 + temp;
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if (new_demand.exceeds(max_registers))
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return move_fail_pressure;
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/* move the candidate below the memory load */
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move_element(block->instructions.begin(), cursor.source_idx, dest_insert_idx);
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/* update register pressure */
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move_element(register_demand, cursor.source_idx, dest_insert_idx);
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for (int i = cursor.source_idx; i < dest_insert_idx - 1; i++)
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register_demand[i] -= candidate_diff;
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register_demand[dest_insert_idx - 1] = new_demand;
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cursor.insert_idx_clause--;
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if (cursor.source_idx != cursor.insert_idx_clause) {
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/* Update demand if we moved over any instructions before the clause */
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cursor.total_demand -= candidate_diff;
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} else {
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assert(cursor.total_demand == RegisterDemand{});
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}
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if (add_to_clause) {
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cursor.clause_demand.update(new_demand);
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} else {
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cursor.clause_demand -= candidate_diff;
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cursor.insert_idx--;
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}
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cursor.source_idx--;
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cursor.verify_invariants(register_demand);
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return move_success;
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}
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void
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MoveState::downwards_skip(DownwardsCursor& cursor)
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{
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aco_ptr<Instruction>& instr = block->instructions[cursor.source_idx];
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for (const Operand& op : instr->operands) {
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if (op.isTemp()) {
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depends_on[op.tempId()] = true;
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if (improved_rar && op.isFirstKill()) {
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RAR_dependencies[op.tempId()] = true;
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RAR_dependencies_clause[op.tempId()] = true;
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}
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}
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}
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cursor.total_demand.update(register_demand[cursor.source_idx]);
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cursor.source_idx--;
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cursor.verify_invariants(register_demand);
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}
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void
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UpwardsCursor::verify_invariants(const RegisterDemand* register_demand)
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{
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#ifndef NDEBUG
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if (!has_insert_idx()) {
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return;
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}
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assert(insert_idx < source_idx);
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RegisterDemand reference_demand;
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for (int i = insert_idx; i < source_idx; ++i) {
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reference_demand.update(register_demand[i]);
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}
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assert(total_demand == reference_demand);
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#endif
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}
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UpwardsCursor
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MoveState::upwards_init(int source_idx, bool improved_rar_)
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{
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improved_rar = improved_rar_;
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std::fill(depends_on.begin(), depends_on.end(), false);
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std::fill(RAR_dependencies.begin(), RAR_dependencies.end(), false);
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for (const Definition& def : current->definitions) {
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if (def.isTemp())
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depends_on[def.tempId()] = true;
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}
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return UpwardsCursor(source_idx);
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}
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bool
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MoveState::upwards_check_deps(UpwardsCursor& cursor)
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{
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aco_ptr<Instruction>& instr = block->instructions[cursor.source_idx];
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for (const Operand& op : instr->operands) {
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if (op.isTemp() && depends_on[op.tempId()])
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return false;
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}
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return true;
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}
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void
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MoveState::upwards_update_insert_idx(UpwardsCursor& cursor)
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{
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cursor.insert_idx = cursor.source_idx;
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cursor.total_demand = register_demand[cursor.insert_idx];
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}
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MoveResult
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MoveState::upwards_move(UpwardsCursor& cursor)
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{
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assert(cursor.has_insert_idx());
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aco_ptr<Instruction>& instr = block->instructions[cursor.source_idx];
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for (const Operand& op : instr->operands) {
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if (op.isTemp() && depends_on[op.tempId()])
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return move_fail_ssa;
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}
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/* check if candidate uses/kills an operand which is used by a dependency */
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for (const Operand& op : instr->operands) {
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if (op.isTemp() && (!improved_rar || op.isFirstKill()) && RAR_dependencies[op.tempId()])
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return move_fail_rar;
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}
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/* check if register pressure is low enough: the diff is negative if register pressure is
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* decreased */
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const RegisterDemand candidate_diff = get_live_changes(instr);
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const RegisterDemand temp = get_temp_registers(instr);
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if (RegisterDemand(cursor.total_demand + candidate_diff).exceeds(max_registers))
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return move_fail_pressure;
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const RegisterDemand temp2 = get_temp_registers(block->instructions[cursor.insert_idx - 1]);
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const RegisterDemand new_demand =
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register_demand[cursor.insert_idx - 1] - temp2 + candidate_diff + temp;
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if (new_demand.exceeds(max_registers))
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return move_fail_pressure;
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/* move the candidate above the insert_idx */
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move_element(block->instructions.begin(), cursor.source_idx, cursor.insert_idx);
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/* update register pressure */
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move_element(register_demand, cursor.source_idx, cursor.insert_idx);
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register_demand[cursor.insert_idx] = new_demand;
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for (int i = cursor.insert_idx + 1; i <= cursor.source_idx; i++)
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register_demand[i] += candidate_diff;
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cursor.total_demand += candidate_diff;
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cursor.total_demand.update(register_demand[cursor.source_idx]);
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cursor.insert_idx++;
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cursor.source_idx++;
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cursor.verify_invariants(register_demand);
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return move_success;
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}
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void
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MoveState::upwards_skip(UpwardsCursor& cursor)
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{
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if (cursor.has_insert_idx()) {
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aco_ptr<Instruction>& instr = block->instructions[cursor.source_idx];
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for (const Definition& def : instr->definitions) {
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if (def.isTemp())
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depends_on[def.tempId()] = true;
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}
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for (const Operand& op : instr->operands) {
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if (op.isTemp())
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RAR_dependencies[op.tempId()] = true;
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}
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cursor.total_demand.update(register_demand[cursor.source_idx]);
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}
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cursor.source_idx++;
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cursor.verify_invariants(register_demand);
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}
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bool
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is_gs_or_done_sendmsg(const Instruction* instr)
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{
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if (instr->opcode == aco_opcode::s_sendmsg) {
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uint16_t imm = instr->sopp().imm;
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return (imm & sendmsg_id_mask) == _sendmsg_gs || (imm & sendmsg_id_mask) == _sendmsg_gs_done;
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}
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return false;
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}
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bool
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is_done_sendmsg(const Instruction* instr)
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{
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if (instr->opcode == aco_opcode::s_sendmsg)
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return (instr->sopp().imm & sendmsg_id_mask) == _sendmsg_gs_done;
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return false;
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}
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memory_sync_info
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get_sync_info_with_hack(const Instruction* instr)
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{
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memory_sync_info sync = get_sync_info(instr);
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if (instr->isSMEM() && !instr->operands.empty() && instr->operands[0].bytes() == 16) {
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// FIXME: currently, it doesn't seem beneficial to omit this due to how our scheduler works
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sync.storage = (storage_class)(sync.storage | storage_buffer);
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sync.semantics =
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(memory_semantics)((sync.semantics | semantic_private) & ~semantic_can_reorder);
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}
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return sync;
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}
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struct memory_event_set {
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bool has_control_barrier;
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unsigned bar_acquire;
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unsigned bar_release;
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unsigned bar_classes;
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unsigned access_acquire;
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unsigned access_release;
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unsigned access_relaxed;
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unsigned access_atomic;
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};
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struct hazard_query {
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bool contains_spill;
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bool contains_sendmsg;
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bool uses_exec;
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memory_event_set mem_events;
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unsigned aliasing_storage; /* storage classes which are accessed (non-SMEM) */
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unsigned aliasing_storage_smem; /* storage classes which are accessed (SMEM) */
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};
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void
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init_hazard_query(hazard_query* query)
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{
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query->contains_spill = false;
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query->contains_sendmsg = false;
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query->uses_exec = false;
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memset(&query->mem_events, 0, sizeof(query->mem_events));
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query->aliasing_storage = 0;
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query->aliasing_storage_smem = 0;
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}
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void
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add_memory_event(memory_event_set* set, Instruction* instr, memory_sync_info* sync)
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{
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set->has_control_barrier |= is_done_sendmsg(instr);
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if (instr->opcode == aco_opcode::p_barrier) {
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Pseudo_barrier_instruction& bar = instr->barrier();
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if (bar.sync.semantics & semantic_acquire)
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set->bar_acquire |= bar.sync.storage;
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if (bar.sync.semantics & semantic_release)
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set->bar_release |= bar.sync.storage;
|
|
set->bar_classes |= bar.sync.storage;
|
|
|
|
set->has_control_barrier |= bar.exec_scope > scope_invocation;
|
|
}
|
|
|
|
if (!sync->storage)
|
|
return;
|
|
|
|
if (sync->semantics & semantic_acquire)
|
|
set->access_acquire |= sync->storage;
|
|
if (sync->semantics & semantic_release)
|
|
set->access_release |= sync->storage;
|
|
|
|
if (!(sync->semantics & semantic_private)) {
|
|
if (sync->semantics & semantic_atomic)
|
|
set->access_atomic |= sync->storage;
|
|
else
|
|
set->access_relaxed |= sync->storage;
|
|
}
|
|
}
|
|
|
|
void
|
|
add_to_hazard_query(hazard_query* query, Instruction* instr)
|
|
{
|
|
if (instr->opcode == aco_opcode::p_spill || instr->opcode == aco_opcode::p_reload)
|
|
query->contains_spill = true;
|
|
query->contains_sendmsg |= instr->opcode == aco_opcode::s_sendmsg;
|
|
query->uses_exec |= needs_exec_mask(instr);
|
|
|
|
memory_sync_info sync = get_sync_info_with_hack(instr);
|
|
|
|
add_memory_event(&query->mem_events, instr, &sync);
|
|
|
|
if (!(sync.semantics & semantic_can_reorder)) {
|
|
unsigned storage = sync.storage;
|
|
/* images and buffer/global memory can alias */ // TODO: more precisely, buffer images and
|
|
// buffer/global memory can alias
|
|
if (storage & (storage_buffer | storage_image))
|
|
storage |= storage_buffer | storage_image;
|
|
if (instr->isSMEM())
|
|
query->aliasing_storage_smem |= storage;
|
|
else
|
|
query->aliasing_storage |= storage;
|
|
}
|
|
}
|
|
|
|
enum HazardResult {
|
|
hazard_success,
|
|
hazard_fail_reorder_vmem_smem,
|
|
hazard_fail_reorder_ds,
|
|
hazard_fail_reorder_sendmsg,
|
|
hazard_fail_spill,
|
|
hazard_fail_export,
|
|
hazard_fail_barrier,
|
|
/* Must stop at these failures. The hazard query code doesn't consider them
|
|
* when added. */
|
|
hazard_fail_exec,
|
|
hazard_fail_unreorderable,
|
|
};
|
|
|
|
HazardResult
|
|
perform_hazard_query(hazard_query* query, Instruction* instr, bool upwards)
|
|
{
|
|
/* don't schedule discards downwards */
|
|
if (!upwards && instr->opcode == aco_opcode::p_exit_early_if)
|
|
return hazard_fail_unreorderable;
|
|
|
|
if (query->uses_exec) {
|
|
for (const Definition& def : instr->definitions) {
|
|
if (def.isFixed() && def.physReg() == exec)
|
|
return hazard_fail_exec;
|
|
}
|
|
}
|
|
|
|
/* don't move exports so that they stay closer together */
|
|
if (instr->isEXP())
|
|
return hazard_fail_export;
|
|
|
|
/* don't move non-reorderable instructions */
|
|
if (instr->opcode == aco_opcode::s_memtime || instr->opcode == aco_opcode::s_memrealtime ||
|
|
instr->opcode == aco_opcode::s_setprio || instr->opcode == aco_opcode::s_getreg_b32)
|
|
return hazard_fail_unreorderable;
|
|
|
|
memory_event_set instr_set;
|
|
memset(&instr_set, 0, sizeof(instr_set));
|
|
memory_sync_info sync = get_sync_info_with_hack(instr);
|
|
add_memory_event(&instr_set, instr, &sync);
|
|
|
|
memory_event_set* first = &instr_set;
|
|
memory_event_set* second = &query->mem_events;
|
|
if (upwards)
|
|
std::swap(first, second);
|
|
|
|
/* everything after barrier(acquire) happens after the atomics/control_barriers before
|
|
* everything after load(acquire) happens after the load
|
|
*/
|
|
if ((first->has_control_barrier || first->access_atomic) && second->bar_acquire)
|
|
return hazard_fail_barrier;
|
|
if (((first->access_acquire || first->bar_acquire) && second->bar_classes) ||
|
|
((first->access_acquire | first->bar_acquire) &
|
|
(second->access_relaxed | second->access_atomic)))
|
|
return hazard_fail_barrier;
|
|
|
|
/* everything before barrier(release) happens before the atomics/control_barriers after *
|
|
* everything before store(release) happens before the store
|
|
*/
|
|
if (first->bar_release && (second->has_control_barrier || second->access_atomic))
|
|
return hazard_fail_barrier;
|
|
if ((first->bar_classes && (second->bar_release || second->access_release)) ||
|
|
((first->access_relaxed | first->access_atomic) &
|
|
(second->bar_release | second->access_release)))
|
|
return hazard_fail_barrier;
|
|
|
|
/* don't move memory barriers around other memory barriers */
|
|
if (first->bar_classes && second->bar_classes)
|
|
return hazard_fail_barrier;
|
|
|
|
/* Don't move memory accesses to before control barriers. I don't think
|
|
* this is necessary for the Vulkan memory model, but it might be for GLSL450. */
|
|
unsigned control_classes =
|
|
storage_buffer | storage_atomic_counter | storage_image | storage_shared;
|
|
if (first->has_control_barrier &&
|
|
((second->access_atomic | second->access_relaxed) & control_classes))
|
|
return hazard_fail_barrier;
|
|
|
|
/* don't move memory loads/stores past potentially aliasing loads/stores */
|
|
unsigned aliasing_storage =
|
|
instr->isSMEM() ? query->aliasing_storage_smem : query->aliasing_storage;
|
|
if ((sync.storage & aliasing_storage) && !(sync.semantics & semantic_can_reorder)) {
|
|
unsigned intersect = sync.storage & aliasing_storage;
|
|
if (intersect & storage_shared)
|
|
return hazard_fail_reorder_ds;
|
|
return hazard_fail_reorder_vmem_smem;
|
|
}
|
|
|
|
if ((instr->opcode == aco_opcode::p_spill || instr->opcode == aco_opcode::p_reload) &&
|
|
query->contains_spill)
|
|
return hazard_fail_spill;
|
|
|
|
if (instr->opcode == aco_opcode::s_sendmsg && query->contains_sendmsg)
|
|
return hazard_fail_reorder_sendmsg;
|
|
|
|
return hazard_success;
|
|
}
|
|
|
|
void
|
|
schedule_SMEM(sched_ctx& ctx, Block* block, std::vector<RegisterDemand>& register_demand,
|
|
Instruction* current, int idx)
|
|
{
|
|
assert(idx != 0);
|
|
int window_size = SMEM_WINDOW_SIZE;
|
|
int max_moves = SMEM_MAX_MOVES;
|
|
int16_t k = 0;
|
|
|
|
/* don't move s_memtime/s_memrealtime */
|
|
if (current->opcode == aco_opcode::s_memtime || current->opcode == aco_opcode::s_memrealtime)
|
|
return;
|
|
|
|
/* first, check if we have instructions before current to move down */
|
|
hazard_query hq;
|
|
init_hazard_query(&hq);
|
|
add_to_hazard_query(&hq, current);
|
|
|
|
DownwardsCursor cursor = ctx.mv.downwards_init(idx, false, false);
|
|
|
|
for (int candidate_idx = idx - 1; k < max_moves && candidate_idx > (int)idx - window_size;
|
|
candidate_idx--) {
|
|
assert(candidate_idx >= 0);
|
|
assert(candidate_idx == cursor.source_idx);
|
|
aco_ptr<Instruction>& candidate = block->instructions[candidate_idx];
|
|
|
|
/* break if we'd make the previous SMEM instruction stall */
|
|
bool can_stall_prev_smem =
|
|
idx <= ctx.last_SMEM_dep_idx && candidate_idx < ctx.last_SMEM_dep_idx;
|
|
if (can_stall_prev_smem && ctx.last_SMEM_stall >= 0)
|
|
break;
|
|
|
|
/* break when encountering another MEM instruction, logical_start or barriers */
|
|
if (candidate->opcode == aco_opcode::p_logical_start)
|
|
break;
|
|
/* only move VMEM instructions below descriptor loads. be more aggressive at higher num_waves
|
|
* to help create more vmem clauses */
|
|
if (candidate->isVMEM() && (cursor.insert_idx - cursor.source_idx > (ctx.num_waves * 4) ||
|
|
current->operands[0].size() == 4))
|
|
break;
|
|
/* don't move descriptor loads below buffer loads */
|
|
if (candidate->format == Format::SMEM && current->operands[0].size() == 4 &&
|
|
candidate->operands[0].size() == 2)
|
|
break;
|
|
|
|
bool can_move_down = true;
|
|
|
|
HazardResult haz = perform_hazard_query(&hq, candidate.get(), false);
|
|
if (haz == hazard_fail_reorder_ds || haz == hazard_fail_spill ||
|
|
haz == hazard_fail_reorder_sendmsg || haz == hazard_fail_barrier ||
|
|
haz == hazard_fail_export)
|
|
can_move_down = false;
|
|
else if (haz != hazard_success)
|
|
break;
|
|
|
|
/* don't use LDS/GDS instructions to hide latency since it can
|
|
* significanly worsen LDS scheduling */
|
|
if (candidate->isDS() || !can_move_down) {
|
|
add_to_hazard_query(&hq, candidate.get());
|
|
ctx.mv.downwards_skip(cursor);
|
|
continue;
|
|
}
|
|
|
|
MoveResult res = ctx.mv.downwards_move(cursor, false);
|
|
if (res == move_fail_ssa || res == move_fail_rar) {
|
|
add_to_hazard_query(&hq, candidate.get());
|
|
ctx.mv.downwards_skip(cursor);
|
|
continue;
|
|
} else if (res == move_fail_pressure) {
|
|
break;
|
|
}
|
|
|
|
if (candidate_idx < ctx.last_SMEM_dep_idx)
|
|
ctx.last_SMEM_stall++;
|
|
k++;
|
|
}
|
|
|
|
/* find the first instruction depending on current or find another MEM */
|
|
UpwardsCursor up_cursor = ctx.mv.upwards_init(idx + 1, false);
|
|
|
|
bool found_dependency = false;
|
|
/* second, check if we have instructions after current to move up */
|
|
for (int candidate_idx = idx + 1; k < max_moves && candidate_idx < (int)idx + window_size;
|
|
candidate_idx++) {
|
|
assert(candidate_idx == up_cursor.source_idx);
|
|
assert(candidate_idx < (int)block->instructions.size());
|
|
aco_ptr<Instruction>& candidate = block->instructions[candidate_idx];
|
|
|
|
if (candidate->opcode == aco_opcode::p_logical_end)
|
|
break;
|
|
|
|
/* check if candidate depends on current */
|
|
bool is_dependency = !found_dependency && !ctx.mv.upwards_check_deps(up_cursor);
|
|
/* no need to steal from following VMEM instructions */
|
|
if (is_dependency && candidate->isVMEM())
|
|
break;
|
|
|
|
if (found_dependency) {
|
|
HazardResult haz = perform_hazard_query(&hq, candidate.get(), true);
|
|
if (haz == hazard_fail_reorder_ds || haz == hazard_fail_spill ||
|
|
haz == hazard_fail_reorder_sendmsg || haz == hazard_fail_barrier ||
|
|
haz == hazard_fail_export)
|
|
is_dependency = true;
|
|
else if (haz != hazard_success)
|
|
break;
|
|
}
|
|
|
|
if (is_dependency) {
|
|
if (!found_dependency) {
|
|
ctx.mv.upwards_update_insert_idx(up_cursor);
|
|
init_hazard_query(&hq);
|
|
found_dependency = true;
|
|
}
|
|
}
|
|
|
|
if (is_dependency || !found_dependency) {
|
|
if (found_dependency)
|
|
add_to_hazard_query(&hq, candidate.get());
|
|
else
|
|
k++;
|
|
ctx.mv.upwards_skip(up_cursor);
|
|
continue;
|
|
}
|
|
|
|
MoveResult res = ctx.mv.upwards_move(up_cursor);
|
|
if (res == move_fail_ssa || res == move_fail_rar) {
|
|
/* no need to steal from following VMEM instructions */
|
|
if (res == move_fail_ssa && candidate->isVMEM())
|
|
break;
|
|
add_to_hazard_query(&hq, candidate.get());
|
|
ctx.mv.upwards_skip(up_cursor);
|
|
continue;
|
|
} else if (res == move_fail_pressure) {
|
|
break;
|
|
}
|
|
k++;
|
|
}
|
|
|
|
ctx.last_SMEM_dep_idx = found_dependency ? up_cursor.insert_idx : 0;
|
|
ctx.last_SMEM_stall = 10 - ctx.num_waves - k;
|
|
}
|
|
|
|
void
|
|
schedule_VMEM(sched_ctx& ctx, Block* block, std::vector<RegisterDemand>& register_demand,
|
|
Instruction* current, int idx)
|
|
{
|
|
assert(idx != 0);
|
|
int window_size = VMEM_WINDOW_SIZE;
|
|
int max_moves = VMEM_MAX_MOVES;
|
|
int clause_max_grab_dist = VMEM_CLAUSE_MAX_GRAB_DIST;
|
|
bool only_clauses = false;
|
|
int16_t k = 0;
|
|
|
|
/* first, check if we have instructions before current to move down */
|
|
hazard_query indep_hq;
|
|
hazard_query clause_hq;
|
|
init_hazard_query(&indep_hq);
|
|
init_hazard_query(&clause_hq);
|
|
add_to_hazard_query(&indep_hq, current);
|
|
|
|
DownwardsCursor cursor = ctx.mv.downwards_init(idx, true, true);
|
|
|
|
for (int candidate_idx = idx - 1; k < max_moves && candidate_idx > (int)idx - window_size;
|
|
candidate_idx--) {
|
|
assert(candidate_idx == cursor.source_idx);
|
|
assert(candidate_idx >= 0);
|
|
aco_ptr<Instruction>& candidate = block->instructions[candidate_idx];
|
|
bool is_vmem = candidate->isVMEM() || candidate->isFlatLike();
|
|
|
|
/* break when encountering another VMEM instruction, logical_start or barriers */
|
|
if (candidate->opcode == aco_opcode::p_logical_start)
|
|
break;
|
|
|
|
/* break if we'd make the previous SMEM instruction stall */
|
|
bool can_stall_prev_smem =
|
|
idx <= ctx.last_SMEM_dep_idx && candidate_idx < ctx.last_SMEM_dep_idx;
|
|
if (can_stall_prev_smem && ctx.last_SMEM_stall >= 0)
|
|
break;
|
|
|
|
bool part_of_clause = false;
|
|
if (current->isVMEM() == candidate->isVMEM()) {
|
|
int grab_dist = cursor.insert_idx_clause - candidate_idx;
|
|
/* We can't easily tell how much this will decrease the def-to-use
|
|
* distances, so just use how far it will be moved as a heuristic. */
|
|
part_of_clause =
|
|
grab_dist < clause_max_grab_dist + k && should_form_clause(current, candidate.get());
|
|
}
|
|
|
|
/* if current depends on candidate, add additional dependencies and continue */
|
|
bool can_move_down = !is_vmem || part_of_clause || candidate->definitions.empty();
|
|
if (only_clauses) {
|
|
/* In case of high register pressure, only try to form clauses,
|
|
* and only if the previous clause is not larger
|
|
* than the current one will be.
|
|
*/
|
|
if (part_of_clause) {
|
|
int clause_size = cursor.insert_idx - cursor.insert_idx_clause;
|
|
int prev_clause_size = 1;
|
|
while (should_form_clause(current,
|
|
block->instructions[candidate_idx - prev_clause_size].get()))
|
|
prev_clause_size++;
|
|
if (prev_clause_size > clause_size + 1)
|
|
break;
|
|
} else {
|
|
can_move_down = false;
|
|
}
|
|
}
|
|
HazardResult haz =
|
|
perform_hazard_query(part_of_clause ? &clause_hq : &indep_hq, candidate.get(), false);
|
|
if (haz == hazard_fail_reorder_ds || haz == hazard_fail_spill ||
|
|
haz == hazard_fail_reorder_sendmsg || haz == hazard_fail_barrier ||
|
|
haz == hazard_fail_export)
|
|
can_move_down = false;
|
|
else if (haz != hazard_success)
|
|
break;
|
|
|
|
if (!can_move_down) {
|
|
if (part_of_clause)
|
|
break;
|
|
add_to_hazard_query(&indep_hq, candidate.get());
|
|
add_to_hazard_query(&clause_hq, candidate.get());
|
|
ctx.mv.downwards_skip(cursor);
|
|
continue;
|
|
}
|
|
|
|
Instruction* candidate_ptr = candidate.get();
|
|
MoveResult res = ctx.mv.downwards_move(cursor, part_of_clause);
|
|
if (res == move_fail_ssa || res == move_fail_rar) {
|
|
if (part_of_clause)
|
|
break;
|
|
add_to_hazard_query(&indep_hq, candidate.get());
|
|
add_to_hazard_query(&clause_hq, candidate.get());
|
|
ctx.mv.downwards_skip(cursor);
|
|
continue;
|
|
} else if (res == move_fail_pressure) {
|
|
only_clauses = true;
|
|
if (part_of_clause)
|
|
break;
|
|
add_to_hazard_query(&indep_hq, candidate.get());
|
|
add_to_hazard_query(&clause_hq, candidate.get());
|
|
ctx.mv.downwards_skip(cursor);
|
|
continue;
|
|
}
|
|
if (part_of_clause)
|
|
add_to_hazard_query(&indep_hq, candidate_ptr);
|
|
else
|
|
k++;
|
|
if (candidate_idx < ctx.last_SMEM_dep_idx)
|
|
ctx.last_SMEM_stall++;
|
|
}
|
|
|
|
/* find the first instruction depending on current or find another VMEM */
|
|
UpwardsCursor up_cursor = ctx.mv.upwards_init(idx + 1, true);
|
|
|
|
bool found_dependency = false;
|
|
/* second, check if we have instructions after current to move up */
|
|
for (int candidate_idx = idx + 1; k < max_moves && candidate_idx < (int)idx + window_size;
|
|
candidate_idx++) {
|
|
assert(candidate_idx == up_cursor.source_idx);
|
|
assert(candidate_idx < (int)block->instructions.size());
|
|
aco_ptr<Instruction>& candidate = block->instructions[candidate_idx];
|
|
bool is_vmem = candidate->isVMEM() || candidate->isFlatLike();
|
|
|
|
if (candidate->opcode == aco_opcode::p_logical_end)
|
|
break;
|
|
|
|
/* check if candidate depends on current */
|
|
bool is_dependency = false;
|
|
if (found_dependency) {
|
|
HazardResult haz = perform_hazard_query(&indep_hq, candidate.get(), true);
|
|
if (haz == hazard_fail_reorder_ds || haz == hazard_fail_spill ||
|
|
haz == hazard_fail_reorder_vmem_smem || haz == hazard_fail_reorder_sendmsg ||
|
|
haz == hazard_fail_barrier || haz == hazard_fail_export)
|
|
is_dependency = true;
|
|
else if (haz != hazard_success)
|
|
break;
|
|
}
|
|
|
|
is_dependency |= !found_dependency && !ctx.mv.upwards_check_deps(up_cursor);
|
|
if (is_dependency) {
|
|
if (!found_dependency) {
|
|
ctx.mv.upwards_update_insert_idx(up_cursor);
|
|
init_hazard_query(&indep_hq);
|
|
found_dependency = true;
|
|
}
|
|
} else if (is_vmem) {
|
|
/* don't move up dependencies of other VMEM instructions */
|
|
for (const Definition& def : candidate->definitions) {
|
|
if (def.isTemp())
|
|
ctx.mv.depends_on[def.tempId()] = true;
|
|
}
|
|
}
|
|
|
|
if (is_dependency || !found_dependency) {
|
|
if (found_dependency)
|
|
add_to_hazard_query(&indep_hq, candidate.get());
|
|
else
|
|
k++;
|
|
ctx.mv.upwards_skip(up_cursor);
|
|
continue;
|
|
}
|
|
|
|
MoveResult res = ctx.mv.upwards_move(up_cursor);
|
|
if (res == move_fail_ssa || res == move_fail_rar) {
|
|
add_to_hazard_query(&indep_hq, candidate.get());
|
|
ctx.mv.upwards_skip(up_cursor);
|
|
continue;
|
|
} else if (res == move_fail_pressure) {
|
|
break;
|
|
}
|
|
k++;
|
|
}
|
|
}
|
|
|
|
void
|
|
schedule_position_export(sched_ctx& ctx, Block* block, std::vector<RegisterDemand>& register_demand,
|
|
Instruction* current, int idx)
|
|
{
|
|
assert(idx != 0);
|
|
int window_size = POS_EXP_WINDOW_SIZE / ctx.schedule_pos_export_div;
|
|
int max_moves = POS_EXP_MAX_MOVES / ctx.schedule_pos_export_div;
|
|
int16_t k = 0;
|
|
|
|
DownwardsCursor cursor = ctx.mv.downwards_init(idx, true, false);
|
|
|
|
hazard_query hq;
|
|
init_hazard_query(&hq);
|
|
add_to_hazard_query(&hq, current);
|
|
|
|
for (int candidate_idx = idx - 1; k < max_moves && candidate_idx > (int)idx - window_size;
|
|
candidate_idx--) {
|
|
assert(candidate_idx >= 0);
|
|
aco_ptr<Instruction>& candidate = block->instructions[candidate_idx];
|
|
|
|
if (candidate->opcode == aco_opcode::p_logical_start)
|
|
break;
|
|
if (candidate->isVMEM() || candidate->isSMEM() || candidate->isFlatLike())
|
|
break;
|
|
|
|
HazardResult haz = perform_hazard_query(&hq, candidate.get(), false);
|
|
if (haz == hazard_fail_exec || haz == hazard_fail_unreorderable)
|
|
break;
|
|
|
|
if (haz != hazard_success) {
|
|
add_to_hazard_query(&hq, candidate.get());
|
|
ctx.mv.downwards_skip(cursor);
|
|
continue;
|
|
}
|
|
|
|
MoveResult res = ctx.mv.downwards_move(cursor, false);
|
|
if (res == move_fail_ssa || res == move_fail_rar) {
|
|
add_to_hazard_query(&hq, candidate.get());
|
|
ctx.mv.downwards_skip(cursor);
|
|
continue;
|
|
} else if (res == move_fail_pressure) {
|
|
break;
|
|
}
|
|
k++;
|
|
}
|
|
}
|
|
|
|
void
|
|
schedule_block(sched_ctx& ctx, Program* program, Block* block, live& live_vars)
|
|
{
|
|
ctx.last_SMEM_dep_idx = 0;
|
|
ctx.last_SMEM_stall = INT16_MIN;
|
|
ctx.mv.block = block;
|
|
ctx.mv.register_demand = live_vars.register_demand[block->index].data();
|
|
|
|
/* go through all instructions and find memory loads */
|
|
for (unsigned idx = 0; idx < block->instructions.size(); idx++) {
|
|
Instruction* current = block->instructions[idx].get();
|
|
|
|
if (block->kind & block_kind_export_end && current->isEXP() && ctx.schedule_pos_exports) {
|
|
unsigned target = current->exp().dest;
|
|
if (target >= V_008DFC_SQ_EXP_POS && target < V_008DFC_SQ_EXP_PRIM) {
|
|
ctx.mv.current = current;
|
|
schedule_position_export(ctx, block, live_vars.register_demand[block->index], current,
|
|
idx);
|
|
}
|
|
}
|
|
|
|
if (current->definitions.empty())
|
|
continue;
|
|
|
|
if (current->isVMEM() || current->isFlatLike()) {
|
|
ctx.mv.current = current;
|
|
schedule_VMEM(ctx, block, live_vars.register_demand[block->index], current, idx);
|
|
}
|
|
|
|
if (current->isSMEM()) {
|
|
ctx.mv.current = current;
|
|
schedule_SMEM(ctx, block, live_vars.register_demand[block->index], current, idx);
|
|
}
|
|
}
|
|
|
|
/* resummarize the block's register demand */
|
|
block->register_demand = RegisterDemand();
|
|
for (unsigned idx = 0; idx < block->instructions.size(); idx++) {
|
|
block->register_demand.update(live_vars.register_demand[block->index][idx]);
|
|
}
|
|
}
|
|
|
|
void
|
|
schedule_program(Program* program, live& live_vars)
|
|
{
|
|
/* don't use program->max_reg_demand because that is affected by max_waves_per_simd */
|
|
RegisterDemand demand;
|
|
for (Block& block : program->blocks)
|
|
demand.update(block.register_demand);
|
|
demand.vgpr += program->config->num_shared_vgprs / 2;
|
|
|
|
sched_ctx ctx;
|
|
ctx.mv.depends_on.resize(program->peekAllocationId());
|
|
ctx.mv.RAR_dependencies.resize(program->peekAllocationId());
|
|
ctx.mv.RAR_dependencies_clause.resize(program->peekAllocationId());
|
|
/* Allowing the scheduler to reduce the number of waves to as low as 5
|
|
* improves performance of Thrones of Britannia significantly and doesn't
|
|
* seem to hurt anything else. */
|
|
// TODO: account for possible uneven num_waves on GFX10+
|
|
unsigned wave_fac = program->dev.physical_vgprs / 256;
|
|
if (program->num_waves <= 5 * wave_fac)
|
|
ctx.num_waves = program->num_waves;
|
|
else if (demand.vgpr >= 29)
|
|
ctx.num_waves = 5 * wave_fac;
|
|
else if (demand.vgpr >= 25)
|
|
ctx.num_waves = 6 * wave_fac;
|
|
else
|
|
ctx.num_waves = 7 * wave_fac;
|
|
ctx.num_waves = std::max<uint16_t>(ctx.num_waves, program->min_waves);
|
|
ctx.num_waves = std::min<uint16_t>(ctx.num_waves, program->num_waves);
|
|
|
|
/* VMEM_MAX_MOVES and such assume pre-GFX10 wave count */
|
|
ctx.num_waves = std::max<uint16_t>(ctx.num_waves / wave_fac, 1);
|
|
|
|
assert(ctx.num_waves > 0);
|
|
ctx.mv.max_registers = {int16_t(get_addr_vgpr_from_waves(program, ctx.num_waves * wave_fac) - 2),
|
|
int16_t(get_addr_sgpr_from_waves(program, ctx.num_waves * wave_fac))};
|
|
|
|
/* NGG culling shaders are very sensitive to position export scheduling.
|
|
* Schedule less aggressively when early primitive export is used, and
|
|
* keep the position export at the very bottom when late primitive export is used.
|
|
*/
|
|
if (program->info->has_ngg_culling && program->stage.num_sw_stages() == 1) {
|
|
if (!program->info->has_ngg_early_prim_export)
|
|
ctx.schedule_pos_exports = false;
|
|
else
|
|
ctx.schedule_pos_export_div = 4;
|
|
}
|
|
|
|
for (Block& block : program->blocks)
|
|
schedule_block(ctx, program, &block, live_vars);
|
|
|
|
/* update max_reg_demand and num_waves */
|
|
RegisterDemand new_demand;
|
|
for (Block& block : program->blocks) {
|
|
new_demand.update(block.register_demand);
|
|
}
|
|
update_vgpr_sgpr_demand(program, new_demand);
|
|
|
|
/* if enabled, this code asserts that register_demand is updated correctly */
|
|
#if 0
|
|
int prev_num_waves = program->num_waves;
|
|
const RegisterDemand prev_max_demand = program->max_reg_demand;
|
|
|
|
std::vector<RegisterDemand> demands(program->blocks.size());
|
|
for (unsigned j = 0; j < program->blocks.size(); j++) {
|
|
demands[j] = program->blocks[j].register_demand;
|
|
}
|
|
|
|
live live_vars2 = aco::live_var_analysis(program);
|
|
|
|
for (unsigned j = 0; j < program->blocks.size(); j++) {
|
|
Block &b = program->blocks[j];
|
|
for (unsigned i = 0; i < b.instructions.size(); i++)
|
|
assert(live_vars.register_demand[b.index][i] == live_vars2.register_demand[b.index][i]);
|
|
assert(b.register_demand == demands[j]);
|
|
}
|
|
|
|
assert(program->max_reg_demand == prev_max_demand);
|
|
assert(program->num_waves == prev_num_waves);
|
|
#endif
|
|
}
|
|
|
|
} // namespace aco
|